JP4160000B2 - Light emitting diode and manufacturing method thereof - Google Patents

Light emitting diode and manufacturing method thereof Download PDF

Info

Publication number
JP4160000B2
JP4160000B2 JP2004036604A JP2004036604A JP4160000B2 JP 4160000 B2 JP4160000 B2 JP 4160000B2 JP 2004036604 A JP2004036604 A JP 2004036604A JP 2004036604 A JP2004036604 A JP 2004036604A JP 4160000 B2 JP4160000 B2 JP 4160000B2
Authority
JP
Japan
Prior art keywords
type gan
conductivity type
forming
nanorods
nanorod
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2004036604A
Other languages
Japanese (ja)
Other versions
JP2005228936A (en
Inventor
ファ モク キム
タエ ウォン カン
クワン ソー チュン
Original Assignee
ドンゴク ユニバーシティ インダストリー アカデミック コーポレイション ファウンデイション
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ドンゴク ユニバーシティ インダストリー アカデミック コーポレイション ファウンデイション filed Critical ドンゴク ユニバーシティ インダストリー アカデミック コーポレイション ファウンデイション
Priority to JP2004036604A priority Critical patent/JP4160000B2/en
Priority to KR1020040030014A priority patent/KR100663745B1/en
Publication of JP2005228936A publication Critical patent/JP2005228936A/en
Application granted granted Critical
Publication of JP4160000B2 publication Critical patent/JP4160000B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • EFIXED CONSTRUCTIONS
    • E02HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02BHYDRAULIC ENGINEERING
    • E02B5/00Artificial water canals, e.g. irrigation canals
    • E02B5/08Details, e.g. gates, screens
    • E02B5/082Closures
    • EFIXED CONSTRUCTIONS
    • E02HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02BHYDRAULIC ENGINEERING
    • E02B7/00Barrages or weirs; Layout, construction, methods of, or devices for, making same
    • E02B7/20Movable barrages; Lock or dry-dock gates
    • E02B7/26Vertical-lift gates
    • E02B7/28Vertical-lift gates with sliding gates
    • EFIXED CONSTRUCTIONS
    • E02HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02BHYDRAULIC ENGINEERING
    • E02B7/00Barrages or weirs; Layout, construction, methods of, or devices for, making same
    • E02B7/20Movable barrages; Lock or dry-dock gates
    • E02B7/26Vertical-lift gates
    • E02B7/36Elevating mechanisms for vertical-lift gates
    • EFIXED CONSTRUCTIONS
    • E02HYDRAULIC ENGINEERING; FOUNDATIONS; SOIL SHIFTING
    • E02BHYDRAULIC ENGINEERING
    • E02B7/00Barrages or weirs; Layout, construction, methods of, or devices for, making same
    • E02B7/20Movable barrages; Lock or dry-dock gates
    • E02B7/54Sealings for gates
    • EFIXED CONSTRUCTIONS
    • E05LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
    • E05Y2201/00Constructional elements; Accessories therefor
    • E05Y2201/60Suspension or transmission members; Accessories therefor
    • E05Y2201/622Suspension or transmission members elements
    • E05Y2201/676Transmission of human force
    • E05Y2201/68Handles, cranks
    • EFIXED CONSTRUCTIONS
    • E05LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
    • E05Y2201/00Constructional elements; Accessories therefor
    • E05Y2201/60Suspension or transmission members; Accessories therefor
    • E05Y2201/622Suspension or transmission members elements
    • E05Y2201/686Rods, links
    • EFIXED CONSTRUCTIONS
    • E05LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
    • E05Y2201/00Constructional elements; Accessories therefor
    • E05Y2201/60Suspension or transmission members; Accessories therefor
    • E05Y2201/622Suspension or transmission members elements
    • E05Y2201/71Toothed gearing
    • EFIXED CONSTRUCTIONS
    • E05LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
    • E05Y2800/00Details, accessories and auxiliary operations not otherwise provided for
    • E05Y2800/10Additional functions
    • E05Y2800/12Sealing
    • EFIXED CONSTRUCTIONS
    • E05LOCKS; KEYS; WINDOW OR DOOR FITTINGS; SAFES
    • E05YINDEXING SCHEME ASSOCIATED WITH SUBCLASSES E05D AND E05F, RELATING TO CONSTRUCTION ELEMENTS, ELECTRIC CONTROL, POWER SUPPLY, POWER SIGNAL OR TRANSMISSION, USER INTERFACES, MOUNTING OR COUPLING, DETAILS, ACCESSORIES, AUXILIARY OPERATIONS NOT OTHERWISE PROVIDED FOR, APPLICATION THEREOF
    • E05Y2900/00Application of doors, windows, wings or fittings thereof
    • E05Y2900/40Application of doors, windows, wings or fittings thereof for gates

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Structural Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Civil Engineering (AREA)
  • Led Devices (AREA)

Description

本発明は、高輝度発光ダイオード(light emitting diode;以下LEDと称する)に関す
るものであり、詳しくはナノロッド(nanorod、nanowire)構造の発光ダイオードおよびそ
の製造方法に関する。
The present invention relates to a light emitting diode (hereinafter referred to as an LED), and more particularly, to a light emitting diode having a nanorod structure and a method for manufacturing the same.

LEDは、その開発初期においては計器盤の簡単な表示素子として多く用いられていたが、最近では大規模の電光板などに用いられる高輝度、高視認性、長寿命の総天然色デイスプレー素子として注目されている。このような用途は、最近、青色および緑色の高輝度LEDが開発されたことにより可能になった。一方、このようなLEDの材料として最近幅広く研究されているものは、GaNのようなIII族-窒素化合物半導体である。これは、III-V族の窒化物半導体が広いバンドギャップ(Bandgap)を有しているため、窒化物の組
成により可視光線から紫外線までほとんどの全波長域の光が得られるからである。しかし、GaNは、現在GaNと格子整合する基板がないため、主にサファイア基板が用いられているが、不整合が相変わらず多く、熱膨張係数の差も大きい。
In the early stages of development, LEDs were widely used as simple display elements for instrument panels. Recently, however, LEDs are used for large-scale electric boards, etc. It is attracting attention as. Such applications have become possible with the recent development of blue and green high brightness LEDs. On the other hand, a group III-nitrogen compound semiconductor such as GaN has been extensively studied as a material for such an LED. This is because the group III-V nitride semiconductor has a wide bandgap, so that light in almost all wavelength ranges from visible light to ultraviolet light can be obtained depending on the composition of the nitride. However, since GaN currently has no substrate lattice-matched with GaN, a sapphire substrate is mainly used, but there are still many mismatches and the difference in thermal expansion coefficient is also large.

従って、通常のGaNのLED、即ちサファイア基板上にn型の不純物の添加されたn-GaN層と、InGaN活性層と、p型の不純物の添加されたp-GaN層とを順次に積層してなる積層フィルム状のLEDは、前述したGaNの物性または成長方法の限界上、格子不整合による多い糸状の転位(threading dislocation)が存在するため、素子の性能(輝度)に限界がある。また、通常の積層フィルム状のGaNのLEDは、設計と製造が比
較的簡単で温度依存性が低いなどの長所があるが、前記の糸状の転位の以外にも低い発光効率、広いスペクトル幅、大きい出力偏差などの短所を有している。
Therefore, an n-GaN layer doped with an n-type impurity, an InGaN active layer, and a p-GaN layer doped with a p-type impurity are sequentially stacked on a normal GaN LED, that is, a sapphire substrate. The laminated film-like LED thus formed has a limit in device performance (luminance) because of the above-mentioned limitations on the physical properties of GaN or the growth method, because there are many threading dislocations due to lattice mismatch. In addition, the ordinary laminated film-like GaN LED has advantages such as relatively simple design and manufacture and low temperature dependence, but besides the above-mentioned thread-like dislocations, low luminous efficiency, wide spectral width, It has disadvantages such as large output deviation.

一方、このような積層フィルム状のLEDの短所を克服するために、一次元の棒または線状のナノロッド(nanorod、nanowire)でp-n接合を成すことにより、LEDを形成するナノスケールのLED、またはマイクロリング(micro-ring)やマイクロディスク(micro-disc)などマイクロスケールのLEDが研究されている。しかし、不幸にもこのようなナノスケールまたはマイクロスケールのLEDでも、積層フィルム状のLEDと同様に多い糸状の転位が生成されるため、相変わらず満足できる水準の高輝度LEDは登場していないのが実情である。また、ナノロッド構造のLEDは、単なるp-n接合ダイオードである
ため、高輝度を得難い。そして、マイクロリングやマイクロディスク構造のLEDは、現在フォトリソグラフィまたは電子ビーム蒸発法により製造されているが、食刻過程でGaNの格子構造に損傷を受けるため、輝度や発光効率において満足できる水準の製品が登場されていない。
On the other hand, in order to overcome the shortcomings of the laminated film-like LED, a nanoscale LED that forms an LED by forming a pn junction with a one-dimensional rod or a linear nanorod (nanorod, nanowire). Alternatively, micro-scale LEDs such as micro-rings and micro-discs have been studied. However, unfortunately, even with such nanoscale or microscale LEDs, as many thread-like dislocations are generated as in the case of laminated film-like LEDs, no satisfactory high-brightness LEDs have yet appeared. It is a fact. Moreover, since the LED of the nanorod structure is a simple pn junction diode, it is difficult to obtain high luminance. Microring and microdisk LEDs are currently manufactured by photolithography or electron beam evaporation, but the GaN lattice structure is damaged during the etching process, so that the brightness and luminous efficiency are satisfactory. The product has not appeared.

本発明は、前記の課題に鑑みて高輝度、高発光効率のGaNのLED構造を提供することをその目的とする。また、本発明は、高輝度、高発光効率のGaNのLEDを再現性よく製造する方法を提供することをその目的とする。   In view of the above problems, an object of the present invention is to provide a GaN LED structure having high luminance and high luminous efficiency. Another object of the present invention is to provide a method for manufacturing a GaN LED having high luminance and high luminous efficiency with good reproducibility.

前記の技術的課題を達成するために、本発明によるGaNのLEDは、p-n接合Ga
Nナノロッドのp-n接合面にInGaN量子井戸(quantum well)を差し込んで、n型G
aNナノロッド、InGaN量子井戸、およびp型GaNナノロッドがこの順に長手方向に連続してなるGaNナノロッドを用いる。また、このようなGaNナノロッドを多数個
アレイ状で配置することにより、従来の積層フィルム状のGaNのLEDに比べてさらに高輝度、高発光効率のLEDを提供する。
In order to achieve the above technical problem, a GaN LED according to the present invention has a pn junction Ga.
Inserting an InGaN quantum well into the pn junction surface of the N nanorod to form an n-type G
A GaN nanorod in which an aN nanorod, an InGaN quantum well, and a p-type GaN nanorod are successively arranged in this order is used. Further, by arranging a large number of such GaN nanorods in an array, an LED having higher luminance and higher luminous efficiency than that of a conventional laminated film-like GaN LED is provided.

即ち、本発明によるLEDは、
基板と、
前記基板の垂直方向に形成された第1導電型のGaNナノロッド(nanorod)と、この第
1導電型のGaNナノロッドの上に形成されたInGaN量子井戸(quantum well)と、このInGaN量子井戸上に形成された第2導電型のGaNナノロッドを各々備える多数のナノロッドとからなるナノロッドアレイ(nanorod array)と、
前記ナノロッドアレイの第1導電型のGaNナノロッドに共通して連結されて電圧を印加する電極パッドと、
前記ナノロッドアレイの第2導電型のGaNナノロッド上に共通して連結されて電圧を印加する透明電極とを備える。ここで、第1導電型および第2導電型は、各々n型およびp型、あるいは各々p型およびn型を意味する。
That is, the LED according to the present invention is
A substrate,
A first conductivity type GaN nanorod formed in a direction perpendicular to the substrate, an InGaN quantum well formed on the first conductivity type GaN nanorod, and an InGaN quantum well on the InGaN quantum well. A nanorod array comprising a plurality of nanorods each having a GaN nanorod of the second conductivity type formed;
An electrode pad commonly connected to the first conductivity type GaN nanorods of the nanorod array to apply a voltage;
A transparent electrode that is commonly connected to the second conductivity type GaN nanorods of the nanorod array and applies a voltage. Here, the first conductivity type and the second conductivity type mean n-type and p-type, respectively, or p-type and n-type, respectively.

前記多数のナノロッド間には、例えばSOG(Spin-On-Glass)、SiO2またはエポキシ樹脂などの透明でギャップフィル特性に優れた透明絶縁物が埋め込まれる。 A transparent insulating material having excellent gap fill characteristics, such as SOG (Spin-On-Glass), SiO 2 or epoxy resin, is embedded between the plurality of nanorods.

また、前記量子井戸は、複数のInGaN層と複数のGaNバリア(barrier)層とが交
互に積層されて形成された多重量子井戸(multi quantum well)から製造できる。
The quantum well may be manufactured from a multi quantum well formed by alternately laminating a plurality of InGaN layers and a plurality of GaN barrier layers.

一方、本発明によるGaNのLEDの製造方法は、
基板の垂直方向に多数の第1導電型のGaNナノロッドをアレイ状で形成する段階と、
前記多数の第1導電型のGaNナノロッドの上に各々InGaN量子井戸を形成する段階と、
前記InGaN量子井戸の上に第2導電型のGaNナノロッドを各々形成する段階と、
前記第1導電型のGaNナノロッドに電圧を印加するための電極パッドを形成する段階と、
前記第2導電型のGaNナノロッド上に共通して連結されて電圧を印加するための透明電極を形成する段階とを含む。ここで、上記第1導電型のGaNナノロッド、InGaN量子井戸および第2導電型のGaNナノロッドは、MO-HVPE(metalorganic-hydride
vapor phase epitaxy)法によりインサイチュ(in-situ)で形成することが望ましい。
On the other hand, a method of manufacturing a GaN LED according to the present invention includes:
Forming a number of first conductivity type GaN nanorods in an array in the vertical direction of the substrate;
Forming an InGaN quantum well on each of the plurality of first conductivity type GaN nanorods;
Forming a second conductivity type GaN nanorod on each of the InGaN quantum wells;
Forming an electrode pad for applying a voltage to the first conductivity type GaN nanorod;
Forming a transparent electrode connected to the second conductivity type GaN nanorods in common and applying a voltage. Here, the GaN nanorods of the first conductivity type, the InGaN quantum wells, and the GaN nanorods of the second conductivity type are MO-HVPE (metalorganic-hydride).
It is desirable to form in-situ by vapor phase epitaxy method.

本発明に係るGaNのLEDおよびその製造方法によれば、高輝度、高発光効率のLEDを、触媒(catalyst)やテンプレート(template)を用いることなく高収率で得ることができる。   According to the GaN LED and the manufacturing method thereof according to the present invention, a high-luminance, high-luminance LED can be obtained in a high yield without using a catalyst or a template.

本発明によれば、単一のエピタキシャル成長によりInGaN量子井戸を有するGaNナノロッドを形成するため、従来の成長方法をそのまま用いながらも高輝度、高品質のダイオードが得られる。   According to the present invention, since a GaN nanorod having InGaN quantum wells is formed by a single epitaxial growth, a high-luminance and high-quality diode can be obtained while using a conventional growth method as it is.

特に、本発明によれば、InGaN量子井戸を持つナノロッドを多数個アレイ状で形成してLEDを製造することにより、側壁発光による光がそのまま生かせるため発光効率が大幅に増加して、同一面積の従来の発光ダイオードに比べて輝度が著しく高いLEDが得られる。   In particular, according to the present invention, by forming a large number of nanorods having InGaN quantum wells in an array and manufacturing an LED, the light emitted from the side wall can be used as it is, so that the light emission efficiency is greatly increased and the same area is obtained. An LED having significantly higher luminance than that of a conventional light emitting diode can be obtained.

また、本発明によれば、InGaN量子井戸の厚さ、Inの含量、蛍光物質の使用により多様な波長の可視光または白色光を出力するLEDを手軽に得ることができる。   Further, according to the present invention, an LED that outputs visible light or white light having various wavelengths can be easily obtained by using the thickness of the InGaN quantum well, the content of In, and the use of a fluorescent material.

以下添付した図面に基づいて本発明の望ましい実施の形態を詳しく説明する。   Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

図1(a)は、本発明の望ましい実施の形態に係るLEDの断面構造を示した模式図であ
り、図1(b)は図1(a)に示したLEDの平面構造を示した平面図である。
FIG. 1 (a) is a schematic view showing a cross-sectional structure of an LED according to a preferred embodiment of the present invention, and FIG. 1 (b) is a plan view showing a planar structure of the LED shown in FIG. 1 (a). FIG.

図1(a)および図1(b)を参照して本実施の形態のLED構造を説明すると、本実施の形態のLEDはサファイア(sapphire)基板10上に、n型GaNバッファー層20、アレイ状に配列された多数のGaNナノロッド31、33、35、GaNナノロッドの間を埋め込んでいる透明絶縁物層41、透明電極60、電極パッド50、70が形成されて成る。   The LED structure of this embodiment will be described with reference to FIGS. 1A and 1B. The LED of this embodiment has an n-type GaN buffer layer 20 and an array on a sapphire substrate 10. A plurality of GaN nanorods 31, 33, 35 arranged in a shape, a transparent insulating layer 41, a transparent electrode 60, and electrode pads 50, 70 embedded between GaN nanorods are formed.

基板10の上に形成されたn型GaNバッファー層20は、基板10とn型GaNナノロッド31との格子定数の不整合を緩衝し、またn型GaNナノロッド31に電極パッド50を介して共通に電圧を印加できるようにする役割を果たす。   The n-type GaN buffer layer 20 formed on the substrate 10 buffers the lattice constant mismatch between the substrate 10 and the n-type GaN nanorods 31, and is shared by the n-type GaN nanorods 31 via the electrode pads 50. It plays a role of applying voltage.

n型GaNバッファー層20の上にアレイ状で配列された多数のGaNナノロッド31、33、35は、各々n型GaNナノロッド31と、InGaN量子井戸33と、p型GaNナノロッド35とから成る。この多数のGaNナノロッドは、実質的に均一な高さと直径を有し、n型GaNバッファー層20に垂直に形成されている。   A large number of GaN nanorods 31, 33, 35 arranged in an array on the n-type GaN buffer layer 20 are each composed of an n-type GaN nanorod 31, an InGaN quantum well 33, and a p-type GaN nanorod 35. The multiple GaN nanorods have a substantially uniform height and diameter, and are formed perpendicular to the n-type GaN buffer layer 20.

ここで、InGaN量子井戸33は、これを有していない単なるp-n接合ダイオード
に比べて高輝度の可視光が得られるようにする活性層であり、本実施の形態では、図2に示したように、複数のInGaN層33aと複数のGaNバリア層33bとが交互に積層されて形成された多重量子井戸(multi quantum well)構造を有している。後述するが、特に、本実施の形態の多重量子井戸33のInGaN層33aと、GaNバリア層33bとの界面は非常にきれいで転位(dislocation)がほとんどない。
Here, the InGaN quantum well 33 is an active layer that makes it possible to obtain visible light with higher luminance than a simple pn junction diode that does not have this, and in the present embodiment, it is shown in FIG. As described above, it has a multi quantum well structure in which a plurality of InGaN layers 33a and a plurality of GaN barrier layers 33b are alternately stacked. As will be described later, in particular, the interface between the InGaN layer 33a and the GaN barrier layer 33b of the multiple quantum well 33 of the present embodiment is very clean and has almost no dislocation.

多数のGaNナノロッド31、33、35の間は、透明絶縁物層41により埋め込まれているため、各々のナノロッドを絶縁し、ナノロッドに加えられる衝撃からナノロッドを保護する。また、透明絶縁物層41は、各々のナノロッドに透明電極60が共通して連結されるようにする下地層の役割を果たす。透明絶縁物層41の材料としては特に限定されることはないが、ナノロッド間のギャップを充分に埋め込むとともに、後続するアニーリング工程などの熱に耐えられ、ナノロッドの側壁発光(図1(a)の左右方向の矢印参照)の
妨害にならないように透明なSOG、SiO2またはエポキシ樹脂が用いられる。また、
透明絶縁物層41は、p型GaNナノロッド35の高さより少し低く形成されて、p型GaNナノロッド35の先端部が透明電極60に共通して連結されるようにする。
A large number of GaN nanorods 31, 33, and 35 are embedded with a transparent insulator layer 41, so that each nanorod is insulated and the nanorods are protected from an impact applied to the nanorods. In addition, the transparent insulator layer 41 serves as a base layer that allows the transparent electrode 60 to be commonly connected to each nanorod. The material of the transparent insulating layer 41 is not particularly limited. However, the gap between the nanorods is sufficiently filled, and it can withstand heat such as a subsequent annealing process, so that the side wall light emission of the nanorod (see FIG. 1A). Transparent SOG, SiO 2 or epoxy resin is used so as not to interfere with the left and right arrows). Also,
The transparent insulator layer 41 is formed slightly lower than the height of the p-type GaN nanorod 35 so that the tip of the p-type GaN nanorod 35 is connected to the transparent electrode 60 in common.

透明電極60は、p型GaNナノロッド35に共通にオーミック(Ohmic)接合して電圧
を印加することが可能で、ナノロッドの長手方向(図面の上方向)発光に妨害にならないように透明な導電物質からなる。透明電極60としては特に限定されることはないが、薄膜のNi/Au薄膜が用いられる。
The transparent electrode 60 can be applied with an ohmic junction in common with the p-type GaN nanorod 35 to apply a voltage, and is a transparent conductive material so as not to interfere with light emission in the longitudinal direction of the nanorod (upward in the drawing). Consists of. The transparent electrode 60 is not particularly limited, but a thin Ni / Au thin film is used.

透明電極60上の所定領域には、透明電極(つまり、p型GaNナノロッド)に電圧を印加するための端子として電極パッド70が形成される。この電極パッド70は特に限定されることはないが、Ni/Au層からなり、ここにはワイヤ(図示せず)がボンディングさ
れる。また、n型GaNバッファー層20を介してn型GaNナノロッドに電圧を印加するための電極パッド50が、n型GaNバッファー層20上に形成されて、n型GaNバッファー層とオーミック接合する。この電極パッド50は特に限定されることはないが、Ti/Al層から成り、ここにもワイヤ(図示せず)がボンディングされる。
In a predetermined region on the transparent electrode 60, an electrode pad 70 is formed as a terminal for applying a voltage to the transparent electrode (that is, the p-type GaN nanorod). The electrode pad 70 is not particularly limited, but is made of a Ni / Au layer, and a wire (not shown) is bonded thereto. Further, an electrode pad 50 for applying a voltage to the n-type GaN nanorods via the n-type GaN buffer layer 20 is formed on the n-type GaN buffer layer 20 and is in ohmic contact with the n-type GaN buffer layer. The electrode pad 50 is not particularly limited, but is made of a Ti / Al layer, and a wire (not shown) is also bonded thereto.

このように構成された本実施の形態のLEDの二つの電極パッド50、70に直流電圧を印加すると(電極パッド70に(+)の電圧を、電極パッド50に(-)電圧または接地転位
を印加)、図1(a)に示したように、各々がナノLEDといえるナノロッドの側壁方向および長手方向に高輝度の光が放出される。
When a DC voltage is applied to the two electrode pads 50 and 70 of the LED of this embodiment configured as described above (a (+) voltage is applied to the electrode pad 70 and a (−) voltage or a ground dislocation is applied to the electrode pad 50). Application), as shown in FIG. 1 (a), high-luminance light is emitted in the side wall direction and the longitudinal direction of the nanorod, each of which can be said to be a nano LED.

特に、本実施の形態ではInGaN量子井戸を各ナノロッドから形成したため、単なるp-n接合ダイオードより高輝度の可視光が放出される。また、多数のナノLEDにより
発光(側壁発光)面積が飛躍的に増えて、発光効率が従来の積層フィルム状のLEDよりさらに高い発光効率が得られる。
In particular, in this embodiment, since the InGaN quantum well is formed from each nanorod, visible light with higher luminance is emitted than a simple pn junction diode. In addition, the area of light emission (side wall light emission) is dramatically increased by a large number of nano LEDs, and the light emission efficiency is higher than that of conventional laminated film LEDs.

一方、本実施の形態のLEDの放出光の波長は、InGaN量子井戸においてIn量を調節したり、量子井戸33の厚さを調節することにより多様に調節できるとともに、白色光も得られる。詳しく説明すれば次のようである。   On the other hand, the wavelength of the emitted light of the LED of the present embodiment can be variously adjusted by adjusting the amount of In in the InGaN quantum well or by adjusting the thickness of the quantum well 33, and white light can also be obtained. The details are as follows.

まず、InGaN中のInの含量を増加させると、バンドギャップが小さくなって発光波長が長くなる現象を用いて、紫外線領域から青、緑、赤など全ての可視光領域までの放出光が得られる。また、発光波長は、量子井戸、即ちInGaN層33aの厚さを調節することにより変化させることもできる。即ち、InGaN層の厚さを増加させると、バンドギャップが小さくなって赤色側の放出光が得られる。   First, when the In content in InGaN is increased, emission light from the ultraviolet region to all visible light regions such as blue, green, and red can be obtained using the phenomenon that the bandgap becomes smaller and the emission wavelength becomes longer. . Further, the emission wavelength can be changed by adjusting the thickness of the quantum well, that is, the InGaN layer 33a. That is, when the thickness of the InGaN layer is increased, the band gap is reduced, and the emitted light on the red side can be obtained.

さらに、本実施の形態のLEDは、前述したように多重量子井戸構造を有しているため、これを用いれば白色光が得られる。即ち、多重量子井戸の複数のInGaN層33aをいくつかのグループに分け、各グループごとにInGaN層中のInの含量を相異に調節することにより、例えば、青色の発光グループ、緑色の発光グループおよび赤色の発光グループを構成すれば全体として白色光が得られる。また、白色光は、蛍光物質を用いても得られるが、特に本実施の形態では透明絶縁物層41に白色光を得るための蛍光物質を添加することにより、簡単に白色の発光LEDを製造できる。例えば、ナノロッド30が青色に発光するように量子井戸を構成し、透明絶縁物層41に黄色の蛍光物質を添加すると、全体として白色光が発光するようにすることができる。   Furthermore, since the LED of this embodiment has a multiple quantum well structure as described above, white light can be obtained by using this. That is, by dividing the plurality of InGaN layers 33a of the multiple quantum well into several groups and adjusting the content of In in the InGaN layer for each group, for example, a blue light emitting group, a green light emitting group, etc. If a red light emitting group is formed, white light can be obtained as a whole. White light can also be obtained by using a fluorescent material. In particular, in the present embodiment, a white light-emitting LED is easily manufactured by adding a fluorescent material for obtaining white light to the transparent insulating layer 41. it can. For example, when the quantum well is configured so that the nanorods 30 emit blue light, and a yellow fluorescent material is added to the transparent insulator layer 41, white light can be emitted as a whole.

以上、本実施の形態のLEDの構造について説明したが、具体的な構造と材料は多様に変形できる。例えば、上記ではn型のGaN層を形成し、その上部にp型GaNナノロッドが形成される態様により説明したが、n型とp型とは逆であってもよい。また、電極パッド50、70の位置や形状も図1(a)および図1(b)に示した位置や形状に限定されずに各々n型のGaNナノロッド31とp型GaNナノロッド35とに共通に電圧を印加できれば、他の位置や形状であってもよい。   Although the structure of the LED of the present embodiment has been described above, the specific structure and material can be variously modified. For example, in the above description, an n-type GaN layer is formed and a p-type GaN nanorod is formed thereon, but the n-type and p-type may be reversed. Further, the positions and shapes of the electrode pads 50 and 70 are not limited to the positions and shapes shown in FIGS. 1A and 1B, and are common to the n-type GaN nanorod 31 and the p-type GaN nanorod 35, respectively. Any other position and shape may be used as long as a voltage can be applied to.

また、上記では基板10としてサファイアを用いたが、シリコン基板も用いることができる。この場合、絶縁物であるサファイアとは異なり、シリコンは適切な不純物(上記の
実施の形態に適用すればn型の不純物)を添加して導電体とすることができる。従って、
n型GaNバッファー層20が不要になるとともに、電極パッド50もn型GaNバッファー層20上の一部領域に形成する必要がなく、シリコン基板の下面(ナノロッド30が
形成される面の反対側の面)に形成すればよい。
In the above description, sapphire is used as the substrate 10, but a silicon substrate can also be used. In this case, unlike sapphire which is an insulator, silicon can be made into a conductor by adding an appropriate impurity (an n-type impurity if applied to the above embodiment mode). Therefore,
The n-type GaN buffer layer 20 is not required, and the electrode pad 50 does not need to be formed in a partial region on the n-type GaN buffer layer 20, and the lower surface of the silicon substrate (on the side opposite to the surface on which the nanorod 30 is formed). Surface).

次に、前述したような本実施の形態のGaNのLEDを製造する方法を説明する。   Next, a method for manufacturing the GaN LED of the present embodiment as described above will be described.

まず、GaNをエピタキシャル成長法で成長させる方法を説明する。エピタキシャル層を成長させる方法には、大別してVPE(Vapor Phase Epitaxial;気相エピタキシャル)成長法、LPE(Liquid Phase Epitaxial;液相エピタキシャル)成長法、SPE(Solid Phase Epitaxial;固相エピタキシャル)成長法がある。ここで、VPE成長法は反応ガスを基
板上に流しながら熱による分解と反応とを通じて基板上に結晶を成長させる方法で、反応ガスの原料の形態によって水素化物VPE(hydride VPE;HVPE) 成長法、ハロゲン化物V
PE(halide VPE) 成長法、有機金属VPE(metalorganic VPE;MOVPE) 成長法などに分
けられる。
First, a method for growing GaN by an epitaxial growth method will be described. The epitaxial layer growth methods are roughly classified into VPE (Vapor Phase Epitaxial) growth method, LPE (Liquid Phase Epitaxial) growth method, and SPE (Solid Phase Epitaxial) growth method. is there. Here, the VPE growth method is a method in which a crystal is grown on a substrate through thermal decomposition and reaction while flowing a reaction gas over the substrate, and a hydride VPE (hydride VPE; HVPE) growth method depending on the form of the raw material of the reaction gas. , Halide V
It can be divided into PE (halide VPE) growth method and metalorganic VPE (MOVPE) growth method.

本実施の形態では、有機金属水素化物気相エピタキシャル(MO-HVPE;metalorganic hydride VPE)成長法によりGaN層とInGaN/GaN量子井戸とを形成することと説明するが、本発明は必ずこの方法に限定されるものではなく、好適にほかの成長法でGaN層とInGaN/GaN量子井戸とを形成することもできる。   In the present embodiment, it will be described that a GaN layer and an InGaN / GaN quantum well are formed by metal organic hydride vapor phase epitaxy (MO-HVPE), but the present invention is not limited to this method. The GaN layer and the InGaN / GaN quantum well can be preferably formed by other growth methods without being limited thereto.

Ga、InおよびNの前駆体(precursor)としては各々GaCl、トリメチルインジウ
ム(trimethylindium)およびNH3を用いる。GaClは、金属ガリウムとHClとを600〜950℃の温度で反応させることにより得られる。また、n型GaNおよびp型GaNを成長させるためにドーピングされる不純物元素は、各々SiおよびMgで、これらは各々SiH4およびCp2Mg(Bis(cyclopentadienyl)magnesium)の形態で供給される。
GaCl, trimethylindium and NH 3 are used as precursors for Ga, In and N, respectively. GaCl is obtained by reacting metal gallium and HCl at a temperature of 600 to 950 ° C. Impurity elements doped to grow n-type GaN and p-type GaN are Si and Mg, respectively, which are supplied in the form of SiH 4 and Cp 2 Mg (Bis (cyclopentadienyl) magnesium), respectively.

以下に、図3(a)ないし図3(d)を参照して本実施の形態のGaNのLEDを製造する方法を詳しく説明する。   Hereinafter, a method of manufacturing the GaN LED of this embodiment will be described in detail with reference to FIGS. 3 (a) to 3 (d).

まず、図3(a)に示したように、サファイアウエハーでなる基板10を反応器(図示せず)に入れ、基板10上にn型GaNバッファー層20を形成する。このとき、n型GaN
バッファー層20は、前述したようにSiをドーピングすることにより形成できるが、人為的にドーピングしなくても成長したGaNは、窒素空孔(nitrogen vacancy)や酸素不純物などにより基本的にn型の特性を有する。この性質を用いて、人為的なドーピングなしに温度400〜500℃、大気圧または若干陽圧とし、50〜60分間GaおよびNの前駆体を各々30〜70sccmおよび1000〜2000sccmの流量で供給することにより約1.5μm程の厚さのn型GaNバッファー層20を成長させることができる。
First, as shown in FIG. 3A, a substrate 10 made of a sapphire wafer is placed in a reactor (not shown), and an n-type GaN buffer layer 20 is formed on the substrate 10. At this time, n-type GaN
The buffer layer 20 can be formed by doping Si as described above. However, GaN grown without artificial doping is basically n-type due to nitrogen vacancy, oxygen impurities, and the like. Has characteristics. Using this property, a precursor of Ga and N is supplied at a flow rate of 30 to 70 sccm and 1000 to 2000 sccm, respectively, at a temperature of 400 to 500 ° C., atmospheric pressure or slightly positive pressure without artificial doping, for 50 to 60 minutes. Thus, the n-type GaN buffer layer 20 having a thickness of about 1.5 μm can be grown.

次に、図3(b)に示したように、多数のナノロッド30でなるナノロッドアレイを形成
するが、この過程は上記のn型GaNバッファー層20を成長させたその反応器内で連続的にインサイチュ(in-situ)で行うことが望ましい。具体的にまず、n型GaNナノロッ
ド31を成長させるが、温度400〜600℃、大気圧または若干陽圧とし、20〜40分間GaおよびNの前駆体を各々30〜70sccmおよび1000〜2000sccmの流量で反応機内に供給し、同時にSiH4を5〜20sccmの流量で供給することにより約0.5μm高さのn型GaNナノロッド31をn型GaNバッファー層20上にその垂直方向に成長させることができる。
Next, as shown in FIG. 3B, a nanorod array composed of a large number of nanorods 30 is formed. This process is continuously performed in the reactor in which the n-type GaN buffer layer 20 is grown. It is desirable to do it in-situ. Specifically, first, n-type GaN nanorods 31 are grown. The temperature is set to 400 to 600 ° C., atmospheric pressure or slightly positive pressure, and Ga and N precursors are flow rates of 30 to 70 sccm and 1000 to 2000 sccm, respectively, for 20 to 40 minutes. The n-type GaN nanorods 31 having a height of about 0.5 μm can be grown on the n-type GaN buffer layer 20 in the vertical direction by simultaneously supplying SiH 4 at a flow rate of 5 to 20 sccm. it can.

一方、通常、高温(例えば、1000℃またはそれ以上)でGaNを成長させると、初期に形成されるGaNのシード(seed)が上方向にのみならず側方にも急速に成長して、ナノロッド状ではなく薄膜状に成長する。この際、シードとシードが側方に成長して合った境界では必然的に転位が生じ、その転位は薄膜の厚さ方向への成長に伴い厚さ方向に伝播して糸状転位が生じる。しかし、上記の本実施の形態のような工程条件を保つと、別途の触媒やテンプレートなしであってもシードが主に上方向に成長して、実質的に均一な高さと直径とを持つ多数のn型GaNナノロッド31を成長させることができる。   On the other hand, normally, when GaN is grown at a high temperature (for example, 1000 ° C. or higher), the initially formed GaN seed rapidly grows not only in the upward direction but also in the lateral direction. It grows in the form of a thin film rather than a film. At this time, dislocations inevitably occur at the boundary where the seeds and the seeds grow sideways, and the dislocations propagate in the thickness direction along with the growth in the thickness direction of the thin film to generate thread dislocations. However, if the process conditions as in the above-described embodiment are maintained, seeds grow mainly upwards without a separate catalyst or template, and a large number of substantially uniform heights and diameters are obtained. N-type GaN nanorods 31 can be grown.

次に、n型GaNナノロッド31上にInGaN量子井戸33を成長させるが、この過程もn型GaNナノロッド31を成長させたその反応器内で連続的にインサイチュで行うことが望ましい。具体的に、温度400〜500℃、大気圧または若干陽圧とし、Ga、InおよびNの前駆体を各々30〜70sccm、10〜40sccmおよび1000〜2000sccmの流量で反応器に供給する。そうすると、多数のn型GaNナノロッド31の上に各
々InGaN量子井戸33が形成される。このとき、InGaN量子井戸33を成長させる時間は、所望する厚さに成長するまで適当に選択されるが、この量子井戸33の厚さは、前述したように、完成したLEDの発光波長を決める要素になるため、所望する波長の光に好適な厚さとなるように設定し、それによって成長時間を決めればよい。また、発光波長はInの量によっても変化するため、所望する波長によって各前駆体の供給比率を調節する。
Next, an InGaN quantum well 33 is grown on the n-type GaN nanorod 31, and this process is also preferably performed continuously in situ in the reactor in which the n-type GaN nanorod 31 is grown. Specifically, the temperature is set to 400 to 500 ° C., atmospheric pressure or slightly positive pressure, and Ga, In and N precursors are supplied to the reactor at flow rates of 30 to 70 sccm, 10 to 40 sccm, and 1000 to 2000 sccm, respectively. As a result, InGaN quantum wells 33 are formed on the large number of n-type GaN nanorods 31. At this time, the time for growing the InGaN quantum well 33 is appropriately selected until the InGaN quantum well 33 is grown to a desired thickness. The thickness of the quantum well 33 determines the emission wavelength of the completed LED as described above. Since it becomes an element, the thickness may be set so as to be suitable for light having a desired wavelength, and the growth time may be determined thereby. Further, since the emission wavelength varies depending on the amount of In, the supply ratio of each precursor is adjusted according to the desired wavelength.

さらに、InGaN量子井戸33は、図2に示したように、複数のInGaN層33aと複数のGaNバリア層33bが交互に積層されて形成された多重量子井戸構造とすることも可能であるが、これはInの前駆体の供給と遮断とを各々所定時間周期的に繰り返すことにより得られる。   Further, as shown in FIG. 2, the InGaN quantum well 33 may have a multiple quantum well structure formed by alternately laminating a plurality of InGaN layers 33a and a plurality of GaN barrier layers 33b. This is obtained by repeating the supply and blocking of the In precursor periodically for a predetermined time.

次に、InGaN量子井戸33上にp型GaNナノロッド35を成長させる。この過程もInGaN量子井戸33を成長させたその反応器内で、連続的にインサイチュで行うことが望ましい。具体的に、温度400〜600℃、大気圧または若干陽圧とし、20〜40分間GaおよびNの前駆体を各々30〜70sccmおよび1000〜2000sccmの流量で反応器内へ供給し、同時にCp2Mgを5〜20sccm供給することにより約0.4mm高さのp型GaNナノロッド35を基板10に対し垂直方向に成長させることができる。 Next, p-type GaN nanorods 35 are grown on the InGaN quantum well 33. This process is also preferably performed in situ continuously in the reactor in which the InGaN quantum well 33 is grown. Specifically, a temperature 400 to 600 ° C., and atmospheric pressure or slightly positive pressure, fed to the reactor at a flow rate of each 30~70sccm and 1000~2000sccm precursors of 20-40 minutes Ga and N, at the same time Cp 2 By supplying 5 to 20 sccm of Mg, a p-type GaN nanorod 35 having a height of about 0.4 mm can be grown in a direction perpendicular to the substrate 10.

図4は、このように成長させたナノロッド30アレイの走査電子顕微鏡の写真である。図4からわかるように、本実施の形態の方法により成長したInGaN量子井戸を含むナノロッド30は、ほとんど均一な高さと直径を有し、かなり高密度で形成(成長)されている。一方、前述した工程条件によって成長されるナノロッド30の平均直径は、量子井戸33が形成された部位で約70〜90nmになり、ナノロッド30間の平均ギャップは100nmほどである。   FIG. 4 is a scanning electron microscope photograph of the nanorod 30 array thus grown. As can be seen from FIG. 4, the nanorod 30 including the InGaN quantum well grown by the method of the present embodiment has a substantially uniform height and diameter and is formed (grown) at a fairly high density. On the other hand, the average diameter of the nanorods 30 grown under the above-described process conditions is about 70 to 90 nm at the site where the quantum wells 33 are formed, and the average gap between the nanorods 30 is about 100 nm.

このようにナノロッド30アレイを形成したのち、図3(c)に示したように、ナノロッ
ド30間のギャップを透明絶縁物層40で埋め込む。このとき用いられる透明絶縁物としては、前述したようにSOG、SiO2またはエポキシ樹脂などが好適で、SOGやエポ
キシ樹脂を用いて埋め込む場合は、スピンコーテイングおよび硬化過程を経ることにより、図3(c)に示したような構造が得られる。このとき、透明絶縁物を用いてギャップを埋
め込む場合は、ギャップが完全に埋め込まれるようにナノロッド30間のギャップが80nm以上になることが良い。一方、透明絶縁物層40の厚さは、ナノロッド30の高さより少し低くする。
After forming the nanorod 30 array in this way, the gap between the nanorods 30 is filled with the transparent insulator layer 40 as shown in FIG. As the transparent insulator used at this time, SOG, SiO 2 or epoxy resin is suitable as described above. When embedding using SOG or epoxy resin, a spin coating and curing process is performed, so that FIG. The structure shown in c) is obtained. At this time, when the gap is filled using a transparent insulator, the gap between the nanorods 30 is preferably 80 nm or more so that the gap is completely filled. On the other hand, the thickness of the transparent insulator layer 40 is slightly lower than the height of the nanorods 30.

次に、図3(d)に示したように、電圧を印加するための電極パッド50、70と透明電
極60を形成することにより、InGaN量子井戸を備えたナノロッドアレイ構造のGaNのLEDを完成する。具体的には、図3(c)の状態でn型GaNナノロッド31に電圧
を印加する電極パッド50を形成するために、n型GaNバッファー層20が一部露出するように透明絶縁物層40およびナノロッド30の一部を除去する。次に、n型GaNバッファー層20が一部露出した領域にリフト-オフ法(lift-off process)を用いて電極パ
ッド50を形成する。この電極パッド50は、例えばTi/Al層を電子ビーム蒸発法(electron-beam evaporation)を用いて形成できる。次に、同様の方法で例えば、Ni/Au
層からなる透明電極60と電極パッド70とを形成する。
Next, as shown in FIG. 3D, electrode pads 50 and 70 for applying a voltage and a transparent electrode 60 are formed to complete a GaN LED having a nanorod array structure with InGaN quantum wells. To do. Specifically, in order to form the electrode pad 50 for applying a voltage to the n-type GaN nanorod 31 in the state of FIG. 3C, the transparent insulator layer 40 is exposed so that the n-type GaN buffer layer 20 is partially exposed. And a part of nanorod 30 is removed. Next, an electrode pad 50 is formed in a region where the n-type GaN buffer layer 20 is partially exposed using a lift-off process. The electrode pad 50 can be formed, for example, by using a Ti / Al layer by electron-beam evaporation. Next, in the same way, for example, Ni / Au
A transparent electrode 60 and an electrode pad 70 made of layers are formed.

一方、透明電極60は、透明絶縁物層41より少し突出したナノロッド30と自然に接触され、結果としてn型GaNナノロッド35と電気的に連結される。また、透明電極60は、その下の個別ナノLEDから放出された光を塞がないように充分薄くすることが好ましく、一方二つの電極パッド50、70にはワイヤなどの外部接続端子がボンディングなどの方法で連結されるように充分な厚さを持つことが好ましい。   On the other hand, the transparent electrode 60 naturally comes into contact with the nanorods 30 protruding slightly from the transparent insulator layer 41, and as a result, is electrically connected to the n-type GaN nanorods 35. The transparent electrode 60 is preferably thin enough not to block the light emitted from the individual nano-LED below it, while external connection terminals such as wires are bonded to the two electrode pads 50 and 70, etc. It is preferable to have a sufficient thickness so as to be connected by the above method.

このように本実施の形態に係るGaNのLEDの製造方法によると、特別な触媒やテンプレートなしに、連続的にn型GaNナノロッド31と、InGaN量子井戸33とp型GaNナノロッド35とからなるナノロッドをアレイ状に均一成長させることができる。   As described above, according to the method of manufacturing a GaN LED according to the present embodiment, a nanorod composed of an n-type GaN nanorod 31, an InGaN quantum well 33, and a p-type GaN nanorod 35 continuously without a special catalyst or template. Can be uniformly grown in an array.

一方、本実施の形態において本質ではない特徴はいくらでも変形可能である。例えば、電極パッド50、70と透明電極60の形成手順や方法は、公知の様々な種類の方法(蒸
着、写真食刻など)に多様に変形することができる。特に、前述した実施の形態における
各構成物質は、公知の均等なほかの材料に置換可能であり、各工程条件は反応器や使用材料によって上記例示の範囲からずれることもあり得る。
On the other hand, features that are not essential in the present embodiment can be modified in any number. For example, the formation procedure and method of the electrode pads 50 and 70 and the transparent electrode 60 can be variously modified into various known methods (evaporation, photolithography, etc.). In particular, each constituent substance in the above-described embodiment can be replaced with other known equivalent materials, and each process condition may deviate from the above-described exemplary range depending on the reactor and the material used.

また、上記では基板10としてサファイアウエハーを用いたが、シリコンウエハー(望
ましくは、リン(P)などのn型不純物がドーピングされたシリコンウエハー)が用いら
れる。この場合前述したように、n型GaNバッファー層20は不要で、電極パッド50もGaNバッファー層20上の一部領域ではなくシリコン基板の下面に形成できる。即ち、シリコンウエハーの一面にまず電極パッドを形成し、その反対面に直接ナノロッド30を形成すればよい。 次に、前述した本発明のGaNのLEDを次のように製造した実施例について発光特性を調べた。これを簡単に説明する。但し、以下の説明で提示された具体的な数値と方法は、あくまでも一例に過ぎず、本発明は以下の説明に限定されることではない。
In the above description, a sapphire wafer is used as the substrate 10, but a silicon wafer (preferably a silicon wafer doped with an n-type impurity such as phosphorus (P)) is used. In this case, as described above, the n-type GaN buffer layer 20 is unnecessary, and the electrode pad 50 can be formed not on a partial region on the GaN buffer layer 20 but on the lower surface of the silicon substrate. That is, an electrode pad is first formed on one surface of a silicon wafer, and the nanorods 30 may be formed directly on the opposite surface. Next, the light emission characteristics were examined for an example in which the above-described GaN LED of the present invention was manufactured as follows. This will be briefly described. However, the specific numerical values and methods presented in the following description are merely examples, and the present invention is not limited to the following description.

まず、基板10としてサファイア(0001)ウエハーを用意し、前述したMO-HVP
E法と前述した前駆体を用いて、インサイチュでn型GaNバッファー層20、GaNナノロッド30を成長させた。ここで、ナノロッド30中のInGaN量子井戸33は、完成したLEDの発光波長が470nm以下になるようInxGa1-xNの組成比はIn0.25Ga0.75Nになるようにした。また、InGaN/GaNを6周期繰り返した多重量子井戸
とし、各々の具体的な工程条件とその結果は次の表のようである。
First, a sapphire (0001) wafer is prepared as the substrate 10 and the MO-HVP described above is prepared.
The n-type GaN buffer layer 20 and the GaN nanorods 30 were grown in situ using the E method and the precursor described above. Here, in the InGaN quantum well 33 in the nanorod 30, the composition ratio of In x Ga 1-x N was set to In 0.25 Ga 0.75 N so that the emission wavelength of the completed LED was 470 nm or less. Further, a multiquantum well in which InGaN / GaN is repeated for six periods is used, and specific process conditions and results thereof are as shown in the following table.

Figure 0004160000
Figure 0004160000

このようにして33mm2面積の多重量子井戸ナノロッドアレイを得た。このナノロッド
アレイの密度は、1mm2の面積内にナノロッド30が約8×107個程存在し、ナノロッド30の平均直径は量子井戸層部位で70nmほど、高さは約1μmであった。n型およびp型GaNナノロッド31、35のキャリア濃度は各々1×1018cm-3、5×1017cm-3程であり、InGaN量子井戸の組成比はIn0.25Ga0.75Nであった。
In this way, a 33 mm 2 area multiple quantum well nanorod array was obtained. The density of the nanorod array was about 8 × 10 7 nanorods 30 in an area of 1 mm 2 , the average diameter of the nanorods 30 was about 70 nm at the quantum well layer portion, and the height was about 1 μm. The carrier concentrations of the n-type and p-type GaN nanorods 31 and 35 were about 1 × 10 18 cm −3 and 5 × 10 17 cm −3 , respectively, and the composition ratio of the InGaN quantum well was In 0.25 Ga 0.75 N.

次に、高い縦横比のナノロッド30間のギャップをボイド(void)なしに均一に埋め
込むようにSOG(Honeywell Electronic Materials社の商品名ACCUGLASS T-12B)を30
00rpmの回転速度で30秒間スピンコーテイングし、大気中で260℃、90秒間アニ
ーリングして硬化させた。一方、本実施例ではSOGがギャップを充分埋め込むようにスピンコーテイングおよび硬化過程を2回に分けて実施した。その後、窒素雰囲気の炉(furnace)内で440℃、20分間アニーリングすることにより、厚さ約0.8〜0.9mm程の
透明絶縁物層40を形成した。
Next, SOG (trade name ACCUGLASS T-12B of Honeywell Electronic Materials Co., Ltd.) 30 so that the gaps between the high aspect ratio nanorods 30 are uniformly filled without voids.
Spin coating was performed for 30 seconds at a rotation speed of 00 rpm, and the film was cured by annealing at 260 ° C. for 90 seconds in the atmosphere. On the other hand, in this example, the spin coating and the curing process were performed in two steps so that the SOG sufficiently filled the gap. Then, the transparent insulator layer 40 having a thickness of about 0.8 to 0.9 mm was formed by annealing at 440 ° C. for 20 minutes in a furnace in a nitrogen atmosphere.

次に、フォトリソグラフィと乾式食刻を用いるリフト-オフ法と電子ビーム蒸発法によ
り、20/200nm厚さのTi/Al電極パッド50を一部領域が露出したn型GaNバッファー層20上に形成し、20/40nm厚さのNi/Au透明電極60を各々のナノスケールLED30とオーミック接合するように蒸着した。そして、最後に電極パッド50と同様の方法で20/200nm厚さのNi/Au電極パッド70を形成した。
Next, a Ti / Al electrode pad 50 having a thickness of 20/200 nm is formed on the n-type GaN buffer layer 20 with a partial region exposed by a lift-off method using photolithography and dry etching and an electron beam evaporation method. Then, a 20/40 nm thick Ni / Au transparent electrode 60 was deposited so as to be in ohmic contact with each nanoscale LED 30. Finally, a 20/200 nm thick Ni / Au electrode pad 70 was formed in the same manner as the electrode pad 50.

一方、比較例として、同一の大きさの積層フィルム状のGaNのLEDを製造した。比較例のLEDにおける各層の厚さと構成は、本発明の実施例と同一にし、但しナノロッドではないという点のみ異なる。   On the other hand, as a comparative example, a GaN LED having the same size and a laminated film shape was manufactured. The thickness and the configuration of each layer in the LED of the comparative example are the same as those of the embodiment of the present invention, except that they are not nanorods.

図5(a)は、上記のように製造した本実施例のLEDに対して20〜100mAの直流電
流を供給した場合のEL(electroluminescence)スペクトルを示したグラフである。図5(a)に示したように、本実施例のLEDは約465nm波長の青色発光LEDであることがわかる。また、図5(b)に示したように、本実施例のLEDは供給電流が増えるほどピーク
波長が少なくなる青色-シフト現象を見せる。これは、注入されたキャリアによる量子井
戸内の内部分極フィールド(built-in internal polarization field)のスクリーン効果に起因すると思われる。
FIG. 5A is a graph showing an EL (electroluminescence) spectrum when a direct current of 20 to 100 mA is supplied to the LED of this example manufactured as described above. As shown in FIG. 5A, it can be seen that the LED of this example is a blue light emitting LED having a wavelength of about 465 nm. In addition, as shown in FIG. 5B, the LED of this example shows a blue-shift phenomenon in which the peak wavelength decreases as the supply current increases. This may be due to the screen effect of the built-in internal polarization field in the quantum well due to the injected carriers.

図6は、本実施例のLEDと比較例のLEDに対して常温でのI-V特性を示したグラ
フである。図6に示したように、ターン-オン電圧は本実施例のLEDが比較例に比べて
少し高い。これは、有効接触面積が本実施例のほうが比較例よりはるかに小さく(本実施
例のLEDは多数のナノLEDの集合とみなすことができる。従って、各ナノLEDの電極60との接触面積が比較例に比べてはるかに小さい)、従って抵抗がそのほど大きいか
らであると考えられる。
FIG. 6 is a graph showing IV characteristics at room temperature for the LED of this example and the LED of the comparative example. As shown in FIG. 6, the turn-on voltage of the LED of this example is slightly higher than that of the comparative example. This is because the effective contact area of the present example is much smaller than that of the comparative example (the LED of this example can be regarded as a collection of a large number of nano LEDs. Therefore, the contact area of each nano LED with the electrode 60 is small. This is considered to be because the resistance is so large compared to the comparative example.

図7は、順方向電流に対する光出力を示したグラフであり、本実施例のLEDが比較例のLEDに比べて光出力が飛躍的に大きいことがわかる(20mAの電流では4.3倍であり、それさえも光検出機の検出面積が1mm2である場合の差で、実際に感じる光出力はこれ
より大きい差が生じるのであろう)。これは、前述したようにナノロッドアレイを形成す
ることにより、同一面積の積層薄膜型LEDに比べて側壁発光が有効に用いられるからである。また、温度依存的なPL(Photoluminescence)実験から本実施例のLEDがより著
しく量子効率性があることを確認できた。
FIG. 7 is a graph showing the light output with respect to the forward current, and it can be seen that the light output of the LED of this example is remarkably higher than that of the LED of the comparative example (4.3 times at 20 mA current). Yes, even if the detection area of the light detector is 1 mm 2 , the light output actually felt will be larger than this). This is because, as described above, by forming the nanorod array, the side wall light emission is effectively used as compared with the laminated thin film LED having the same area. Moreover, it was confirmed from the temperature-dependent PL (Photoluminescence) experiment that the LED of this example has a significantly higher quantum efficiency.

一方、図8は、一つのInGaN量子井戸ナノロッドに電極を形成した場合を示したものであり、図9はこの場合のI-V特性を示したグラフである。図8に示した構造のナノ
LEDは、上記のように製造されたナノロッドアレイをメタノールに分散させた後、これを酸化されたシリコン基板のような基板に附着させ、n型GaNナノロッド131側にはTi/Al電極パッド150を、p型GaNナノロッド135側にはNi/Au電極パッド170を形成することにより得られる。このように得られたナノロッド一つで成るナノLEDに対してI-V特性を調べた。図9からわかるように、このナノLEDは非常にきれ
いで正確な整流特性を見せる。これはp、n型ナノロッドと量子井戸とを単一エピタキシャル成長で形成したからであると考えられる。
On the other hand, FIG. 8 shows a case where an electrode is formed on one InGaN quantum well nanorod, and FIG. 9 is a graph showing IV characteristics in this case. In the nano LED having the structure shown in FIG. 8, after the nanorod array manufactured as described above is dispersed in methanol, the nanorod array is attached to a substrate such as an oxidized silicon substrate, on the n-type GaN nanorod 131 side. Is obtained by forming the Ti / Al electrode pad 150 and the Ni / Au electrode pad 170 on the p-type GaN nanorod 135 side. The IV characteristics of the nano LED composed of one nanorod thus obtained were examined. As can be seen from FIG. 9, this nano LED exhibits a very clean and accurate rectification characteristic. This is presumably because p and n-type nanorods and quantum wells were formed by single epitaxial growth.

以上、望ましい実施の形態を挙げて本発明を説明したが、本明細書および図面に記載された実施の形態は本発明の最も望ましい実施の形態に過ぎず、本発明の技術的思想を制限するものではなく、本出願のときにこれらを代替可能な多様な均等物と変形例とがあり得ることを理解すべきである。   Although the present invention has been described with reference to the preferred embodiments, the embodiments described in this specification and the drawings are only the most desirable embodiments of the present invention, and limit the technical idea of the present invention. It should be understood that there are a variety of equivalents and variations that can be substituted at the time of this application.

図1(a)は、本発明の望ましい実施の形態に係る発光ダイオードの断面構造を示した模式図である。FIG. 1A is a schematic diagram showing a cross-sectional structure of a light emitting diode according to a preferred embodiment of the present invention. 図1(b)は、図1(a)に示した発光ダイオードの平面構造を示した平面図である。FIG. 1B is a plan view showing a planar structure of the light emitting diode shown in FIG. 図2は、図1(a)に示した発光ダイオードの多重量子井戸構造を示した断面図である。FIG. 2 is a cross-sectional view showing a multiple quantum well structure of the light emitting diode shown in FIG. 図3(a)は、本発明の一実施の形態により発光ダイオードを製造する過程を示した断面図である。FIG. 3A is a cross-sectional view illustrating a process of manufacturing a light emitting diode according to an embodiment of the present invention. 図3(b)は、本発明の一実施の形態により発光ダイオードを製造する過程を示した断面図である。FIG. 3B is a cross-sectional view illustrating a process of manufacturing a light emitting diode according to an embodiment of the present invention. 図3(c)は、本発明の一実施の形態により発光ダイオードを製造する過程を示した断面図である。FIG. 3C is a cross-sectional view illustrating a process of manufacturing a light emitting diode according to an embodiment of the present invention. 図3(d)は、本発明の一実施の形態により発光ダイオードを製造する過程を示した断面図である。FIG. 3D is a cross-sectional view illustrating a process of manufacturing a light emitting diode according to an embodiment of the present invention. 本発明の一実施の形態により製造されたナノロッドアレイの走査電子顕微鏡(SEM)写真である。1 is a scanning electron microscope (SEM) photograph of a nanorod array manufactured according to an embodiment of the present invention. 図5(a)は、本発明の一実施の形態により製造された発光ダイオードにおいて各電流に対する発光波長のEL強度を示したグラフである。FIG. 5A is a graph showing the EL intensity of the emission wavelength with respect to each current in the light-emitting diode manufactured according to the embodiment of the present invention. 図5(b)は、図5(a)のグラフにおいて各電流に対するピーク波長を示したグラフである。FIG. 5 (b) is a graph showing the peak wavelength for each current in the graph of FIG. 5 (a). 図6は、本発明の一実施の形態により製造された発光ダイオードと従来の発光ダイオードのI-V特性を示したグラフである。FIG. 6 is a graph showing IV characteristics of a light emitting diode manufactured according to an embodiment of the present invention and a conventional light emitting diode. 図7は、本発明の一実施の形態により製造された発光ダイオードと従来の発光ダイオードの光出力-順方向電流特性を示したグラフである。FIG. 7 is a graph showing light output-forward current characteristics of a light emitting diode manufactured according to an embodiment of the present invention and a conventional light emitting diode. 図8は、本発明による一つのGanNナノロッドからなる発光ダイオードを示した模式図である。FIG. 8 is a schematic view showing a light emitting diode composed of one GanN nanorod according to the present invention. 図9は、図8に示した発光ダイオードのI−V特性を示したグラフである。FIG. 9 is a graph showing IV characteristics of the light emitting diode shown in FIG.

符号の説明Explanation of symbols

10..基板
20..バッファー層
31..n型GaNナノロッド
33..InGaN量子井戸
33a..InGaN層
33b..GaNバリア層
35..p型GaNナノロッド
41..透明絶縁物層
50..電極パッド
60..透明電極
70..電極パッド
10. . Substrate 20. . Buffer layer 31. . n-type GaN nanorods 33. . InGaN quantum well 33a. . InGaN layer 33b. . GaN barrier layer 35. . p-type GaN nanorods 41. . Transparent insulator layer 50. . Electrode pad 60. . Transparent electrode 70. . Electrode pad

Claims (8)

基板の垂直方向に多数の第1導電型のGaNナノロッドを、温度400〜600℃で大気圧または若干の陽圧下に、アレイ状で形成する段階と、
前記多数の第1導電型のGaNナノロッドの上に各々InGaN量子井戸を、温度400〜500℃で大気圧または若干の陽圧下に、形成する段階と、
前記InGaN量子井戸の上に第2導電型のGaNナノロッドを、温度400〜600℃で大気圧または若干の陽圧下に、各々形成する段階と、
前記第1導電型のGaNナノロッドに電圧を印加するための電極パッドを形成する段階と、
前記第2導電型のGaNナノロッド上に共通して連結されて電圧を印加するための透明電極を形成する段階とを含む発光ダイオードの製造方法。
Forming a large number of first conductivity type GaN nanorods in a vertical direction of the substrate in an array at a temperature of 400 to 600 ° C. under atmospheric pressure or slightly positive pressure;
Forming an InGaN quantum well on each of the first conductivity type GaN nanorods at a temperature of 400 to 500 ° C. under atmospheric pressure or slightly positive pressure;
Forming GaN nanorods of the second conductivity type on the InGaN quantum well, respectively, at a temperature of 400 to 600 ° C. under atmospheric pressure or slightly positive pressure;
Forming an electrode pad for applying a voltage to the first conductivity type GaN nanorod;
Forming a transparent electrode connected to the second conductivity type GaN nanorods in common and applying a voltage.
前記第2導電型のGaNナノロッドを形成する段階に続いて、第1導電型のGaNナノロッドと、InGaN量子井戸と、第2導電型のGaNナノロッドとからなるナノロッドの間に透明絶縁物を埋め込む段階をさらに含むことを特徴とする請求項1に記載の発光ダイオードの製造方法。   Subsequent to the step of forming the second conductivity type GaN nanorod, a step of embedding a transparent insulator between nanorods composed of the first conductivity type GaN nanorod, the InGaN quantum well, and the second conductivity type GaN nanorod. The method of manufacturing a light emitting diode according to claim 1, further comprising: 前記透明絶縁物は、SOG(Spin-On-Glass)、SiO2またはエポキシ樹脂であることを特徴とする請求項2に記載の発光ダイオードの製造方法。 The transparent insulating material, SOG (Spin-On-Glass ), The method as claimed in claim 2, characterized in that a SiO 2 or an epoxy resin. 前記透明絶縁物には、前記発光ダイオードの放出光が全体として白色光になるように蛍光物質が添加されていることを特徴とする請求項2に記載の発光ダイオードの製造方法。   3. The method of manufacturing a light emitting diode according to claim 2, wherein a fluorescent material is added to the transparent insulator so that light emitted from the light emitting diode becomes white light as a whole. 前記量子井戸を形成する段階は、InGaN層を形成する段階と、GaNバリア(barrier)層を形成する段階とを交互に繰り返すことにより多重量子井戸を形成する段階である
ことを特徴とする請求項1に記載の発光ダイオードの製造方法。
The step of forming the quantum well is a step of forming a multiple quantum well by alternately repeating a step of forming an InGaN layer and a step of forming a GaN barrier layer. 2. A method for producing a light-emitting diode according to 1.
前記第1導電型のGaNナノロッドと、InGaN量子井戸と、第2導電型のGaNナノロッドとは、MO-HVPE(metalorganic-hydride vapor phase epitaxy)法によりイ
ンサイチュ(in-situ)で形成されることを特徴とする請求項1に記載の発光ダイオードの
製造方法。
The first conductivity type GaN nanorod, the InGaN quantum well, and the second conductivity type GaN nanorod are formed in-situ by an MO-HVPE (metalorganic-hydride vapor phase epitaxy) method. The method of manufacturing a light emitting diode according to claim 1, wherein
前記基板はサファイア基板であり、上記第1導電型のGaNナノロッドを形成する段階の以前に、前記サファイア基板上に第1導電型のGaNバッファー層を、温度400〜500℃で大気圧または若干の陽圧下に、形成する段階をさらに含み、前記電極パッドは前記GaNバッファー層上の一部領域に形成されることを特徴とする請求項1に記載の発光ダイオードの製造方法。   The substrate is a sapphire substrate, and before the step of forming the first conductivity type GaN nanorods, the first conductivity type GaN buffer layer is placed on the sapphire substrate at a temperature of 400 to 500 ° C. at atmospheric pressure or slightly. The method of claim 1, further comprising forming under a positive pressure, wherein the electrode pad is formed in a partial region on the GaN buffer layer. 前記基板はシリコン基板であり、前記電極パッドは前記シリコン基板のナノロッドが形成される面と反対側の面に形成されることを特徴とする請求項1に記載の発光ダイオードの製造方法。

The method of claim 1, wherein the substrate is a silicon substrate, and the electrode pad is formed on a surface of the silicon substrate opposite to a surface on which nanorods are formed.

JP2004036604A 2004-02-13 2004-02-13 Light emitting diode and manufacturing method thereof Expired - Lifetime JP4160000B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004036604A JP4160000B2 (en) 2004-02-13 2004-02-13 Light emitting diode and manufacturing method thereof
KR1020040030014A KR100663745B1 (en) 2004-02-13 2004-04-29 Super Bright Light Emitting Diode of Nanorod Array Structure Having InGaN Quantum Well and Method for Manufacturing the Same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004036604A JP4160000B2 (en) 2004-02-13 2004-02-13 Light emitting diode and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JP2005228936A JP2005228936A (en) 2005-08-25
JP4160000B2 true JP4160000B2 (en) 2008-10-01

Family

ID=35003402

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004036604A Expired - Lifetime JP4160000B2 (en) 2004-02-13 2004-02-13 Light emitting diode and manufacturing method thereof

Country Status (2)

Country Link
JP (1) JP4160000B2 (en)
KR (1) KR100663745B1 (en)

Families Citing this family (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100621918B1 (en) * 2004-06-10 2006-09-14 학교법인 포항공과대학교 Light emitting device comprising conductive nanorod as transparent electrode
EP2410582B1 (en) * 2005-05-24 2019-09-04 LG Electronics Inc. Nano rod type light emitting diode and method for fabricating a nano rod type light emitting diode
KR100654533B1 (en) * 2005-05-24 2006-12-06 엘지전자 주식회사 Light emitting device hanving nano rod for light extraction and method for manufacturing the same
US8022432B2 (en) * 2005-08-19 2011-09-20 Lg Display Co., Ltd. Light-emitting device comprising conductive nanorods as transparent electrodes
KR20070021671A (en) * 2005-08-19 2007-02-23 서울옵토디바이스주식회사 Light emitting diode employing an array of nonorods and method of fabricating the same
KR100643473B1 (en) * 2005-09-06 2006-11-10 엘지전자 주식회사 Light emitting device with nano-rod and method for fabricating the same
KR100661960B1 (en) * 2005-09-28 2006-12-28 엘지전자 주식회사 Light emitting diode and manufacturing method thereof
KR101316415B1 (en) 2005-10-17 2013-10-08 엘지이노텍 주식회사 Nitride semiconductor light-emitting device and manufacturing method thereof
JP4552828B2 (en) * 2005-10-26 2010-09-29 パナソニック電工株式会社 Manufacturing method of semiconductor light emitting device
KR100668351B1 (en) * 2006-01-05 2007-01-12 삼성코닝 주식회사 Nitride-based light emitting device and method of manufacturing the same
JP2008034482A (en) * 2006-07-26 2008-02-14 Matsushita Electric Works Ltd Compound semiconductor light-emitting element, illumination apparatus using the same and method of manufacturing the compound semiconductor element
KR100810146B1 (en) * 2006-09-28 2008-03-06 전북대학교산학협력단 Light emitting diode including nitride-based semiconductor nanowires and method of fabricating the same
JP2008108757A (en) * 2006-10-23 2008-05-08 Matsushita Electric Works Ltd Compound semiconductor light-emitting element, illumination apparatus employing the same and manufacturing method of compound semiconductor element
JP4965293B2 (en) * 2007-03-19 2012-07-04 パナソニック株式会社 Semiconductor light emitting device, illumination device using the same, and method for manufacturing semiconductor light emitting device
JP2008258297A (en) * 2007-04-03 2008-10-23 Matsushita Electric Ind Co Ltd Light-emitting element
WO2008129861A1 (en) * 2007-04-18 2008-10-30 Panasonic Corporation Light-emitting device
JP5042715B2 (en) * 2007-06-11 2012-10-03 パナソニック株式会社 Manufacturing method of semiconductor light emitting device
KR20090012493A (en) * 2007-07-30 2009-02-04 삼성전기주식회사 Photonic crystal light emitting device
FR2922685B1 (en) * 2007-10-22 2011-02-25 Commissariat Energie Atomique AN OPTOELECTRONIC DEVICE BASED ON NANOWIRES AND CORRESPONDING METHODS
US8304979B2 (en) 2007-12-06 2012-11-06 Panasonic Corporation Light emitting device having inorganic luminescent particles in inorganic hole transport material
CN101971369B (en) * 2008-03-14 2012-05-23 松下电器产业株式会社 Compound semiconductor light-emitting element and illumination device using the same, and method for manufacturing compound semiconductor light-emitting element
JP5145120B2 (en) 2008-05-26 2013-02-13 パナソニック株式会社 COMPOUND SEMICONDUCTOR LIGHT EMITTING ELEMENT, LIGHTING DEVICE USING SAME, AND COMPOUND SEMICONDUCTOR LIGHT EMITTING DEVICE MANUFACTURING METHOD
KR20100028412A (en) 2008-09-04 2010-03-12 삼성전자주식회사 Light emitting diode using nano-rod and method for manufacturing the same
KR101603777B1 (en) 2009-04-16 2016-03-15 삼성전자주식회사 White light emitting diode
KR101148444B1 (en) 2009-06-19 2012-05-21 순천대학교 산학협력단 White Nano Light Emitting Diode and Method for Making the Same
KR101611412B1 (en) 2009-10-28 2016-04-11 삼성전자주식회사 Light emitting device
KR101652793B1 (en) * 2009-11-25 2016-08-31 삼성전자주식회사 Light emitting device having a current-limiting layer
AU2011268135B2 (en) * 2010-06-18 2014-06-12 Glo Ab Nanowire LED structure and method for manufacturing the same
US8242523B2 (en) * 2010-07-29 2012-08-14 National Tsing Hua University III-Nitride light-emitting diode and method of producing the same
WO2012029381A1 (en) * 2010-09-01 2012-03-08 シャープ株式会社 Light emitting element and production method for same, production method for light-emitting device, illumination device, backlight, display device, and diode
JP4927223B2 (en) * 2010-09-01 2012-05-09 シャープ株式会社 LIGHT EMITTING ELEMENT AND ITS MANUFACTURING METHOD, LIGHT EMITTING DEVICE MANUFACTURING METHOD, LIGHTING DEVICE, BACKLIGHT AND DISPLAY DEVICE
KR20150098246A (en) * 2010-09-01 2015-08-27 샤프 가부시키가이샤 Light emitting element and production method for same, production method for light-emitting device, illumination device, backlight, display device, and diode
EP2618388B1 (en) 2012-01-20 2019-10-02 OSRAM Opto Semiconductors GmbH Light-emitting diode chip
KR101352958B1 (en) * 2012-11-22 2014-01-21 전북대학교산학협력단 Manufacturing method of nanowire and diode comprising nanowire munufactured using the same
DE102013100291B4 (en) 2013-01-11 2021-08-05 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Optoelectronic semiconductor chip
FR3004000B1 (en) * 2013-03-28 2016-07-15 Aledia ELECTROLUMINESCENT DEVICE WITH INTEGRATED SENSOR AND METHOD FOR CONTROLLING THE TRANSMISSION OF THE DEVICE
FR3015772B1 (en) * 2013-12-19 2017-10-13 Aledia OPTICAL ELECTROLUMINESCENT DIODE DEVICE WITH IMPROVED LIGHT EXTRACTION
JP6330486B2 (en) * 2014-05-29 2018-05-30 富士通株式会社 Semiconductor nanowire optical device and manufacturing method thereof
CN104360425B (en) 2014-11-24 2017-02-22 京东方科技集团股份有限公司 Optical film layer, light emitting device and display device
KR101783104B1 (en) 2015-10-30 2017-09-28 연세대학교 산학협력단 Nanowire bundle array, broadband and ultrahigh optical film and method for manufacturing of the same
EP3807925A4 (en) * 2018-06-13 2022-03-02 Lawrence Livermore National Security, LLC Strain control in optoelectronic devices
KR102518610B1 (en) * 2019-10-23 2023-04-05 미쓰비시덴키 가부시키가이샤 Semiconductor wafer and its manufacturing method
CN116014043B (en) * 2023-03-24 2023-06-02 江西兆驰半导体有限公司 Deep ultraviolet light-emitting diode epitaxial wafer, preparation method thereof and LED

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100411573B1 (en) * 2000-03-04 2003-12-18 주식회사 엔엠씨텍 Method for forming semiconductor light emitting device by using quantum holes
KR100462468B1 (en) * 2002-03-02 2004-12-17 학교법인 포항공과대학교 Single nano wire and nano devices using thereof
KR100644166B1 (en) * 2004-02-12 2006-11-10 학교법인 포항공과대학교 Heterojunction structure of nitride semiconductor and nano-devices or their array comprising same

Also Published As

Publication number Publication date
KR100663745B1 (en) 2007-01-02
JP2005228936A (en) 2005-08-25
KR20050081139A (en) 2005-08-18

Similar Documents

Publication Publication Date Title
JP4160000B2 (en) Light emitting diode and manufacturing method thereof
US7132677B2 (en) Super bright light emitting diode of nanorod array structure having InGaN quantum well and method for manufacturing the same
US20080191191A1 (en) Light Emitting Diode of a Nanorod Array Structure Having a Nitride-Based Multi Quantum Well
US8330173B2 (en) Nanostructure having a nitride-based quantum well and light emitting diode employing the same
JP4552828B2 (en) Manufacturing method of semiconductor light emitting device
JP5280004B2 (en) Light emitting device and manufacturing method thereof
KR100644166B1 (en) Heterojunction structure of nitride semiconductor and nano-devices or their array comprising same
TWI381554B (en) Light emitting diode structure, multiple quantum well structure thereof, and method for fabricating the multiple quantum well structure
JP4965294B2 (en) Semiconductor light emitting device, illumination device using the same, and method for manufacturing semiconductor light emitting device
TWI310963B (en) Epitaxial substrate for compound semiconductor light-emitting device, method for producing the same and light-emitting device
KR20120028104A (en) Group iii nitride nanorod light emitting device and manufacturing method for the same
JPH11354839A (en) Gan semiconductor light emitting element
JP2010098336A (en) GaN SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD THEREOF
US8334156B2 (en) Nitride semiconductor single crystal substrate, and methods of fabricating the same and a vertical nitride semiconductor light emitting diode using the same
TWI493747B (en) Light emitting diodes and manufacture thereof
KR100682873B1 (en) Semiconductor emitting device and manufacturing method for the same
JP2008108924A (en) Compound semiconductor light-emitting element, illumination apparatus employing the same and manufacturing method of compound semiconductor light-emitting element
JPH11354842A (en) Gan semiconductor light emitting element
KR100820836B1 (en) Method for manufacturing light emitting diode
TW200541115A (en) Group Ⅲ nitride semiconductor light-emitting device
KR20080030042A (en) Light emitting diode of a nanorod array structure having a nitride-baseed multi quantum well
JPH11354843A (en) Fabrication of group iii nitride quantum dot structure and use thereof
KR102099877B1 (en) Method for fabricating nitride semiconductor device
JP3541775B2 (en) Group III nitride semiconductor light emitting device wafer, method of manufacturing the same, and group III nitride semiconductor light emitting device
KR100693129B1 (en) Method for fabricating single-rod GaN pn junction LED

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20051227

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060118

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20060417

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20060420

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20060906

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070215

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20070319

A912 Re-examination (zenchi) completed and case transferred to appeal board

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20070413

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20080502

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20080716

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

Ref document number: 4160000

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110725

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120725

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120725

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130725

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term