KR101652793B1 - Light emitting device having a current-limiting layer - Google Patents

Light emitting device having a current-limiting layer Download PDF

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KR101652793B1
KR101652793B1 KR1020090114636A KR20090114636A KR101652793B1 KR 101652793 B1 KR101652793 B1 KR 101652793B1 KR 1020090114636 A KR1020090114636 A KR 1020090114636A KR 20090114636 A KR20090114636 A KR 20090114636A KR 101652793 B1 KR101652793 B1 KR 101652793B1
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South Korea
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layer
current
sio
junction
junction diodes
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KR1020090114636A
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Korean (ko)
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KR20110057988A (en
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최준희
박성수
안드레이 줄카니브
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삼성전자주식회사
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Abstract

The light emitting device having the current confined layer may include a substrate, a first electrode layer, a current confined layer, a pn junction diode, and a second electrode layer. The current confined layer may be connected in series with the pn junction diode to limit the current flowing across the pn junction diode to within the limiting current, even if the pn junction diode is shorted or operating abnormally.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a light-emitting device having a current-

This disclosure relates to a light emitting device having a current confined layer.

A light emitting diode (LED) is a light emitting device having a pn junction semiconductor layer, and a pn junction in which an electron-hole is coupled to emit light. In order to overcome the disadvantages of low luminous efficiency, wide spectrum width and large output deviation of conventional laminated film type LEDs, a nanoscale LED or nanoscale LED forming a pn junction with a nanorod, LEDs are being studied. Nanostructured LEDs have high specific surface area and high light-extraction efficiency.

A light-emitting element having a current confined layer is provided.

A light emitting device having a current confined layer according to an aspect of the present invention includes:

Board;

A first electrode layer provided on a substrate;

A current confinement layer provided on the first electrode layer;

A plurality of pn junction diodes provided on the current confined layer;

and a second electrode layer provided to cover an upper portion of the pn junction diode.

The plurality of pn junction diodes may include a p-type semiconductor layer, an active layer, and an n-type semiconductor layer.

the p-type semiconductor layer may be a p-type GaN layer, the active layer may be an InGaN active layer, and the n-type semiconductor layer may be an n-type GaN layer.

The plurality of pn junction diodes may be nano bars or micro-bar-shaped pn junction diodes.

The plurality of pn junction diodes may be poly-crystalline pn junction diodes.

And may further include an insulating layer insulating the plurality of pn junction diodes from each other.

The resistance of the current confined layer may be between 30 OMEGA and 100 M [Omega].

Current confined layer is SiO x N y: consisting of P, SiN y, or SiO x: B, SiO x N y: P, SiO x N y, SiN y: B, SiN y: P, SiO x: B, SiO x May be formed of any one selected from the group.

x can satisfy 0.05? x? 2.

The current confined layer can be determined by heating any one selected from the group.

The current confining layer may include a plurality of resistance regions provided under the plurality of pn junction diodes and an insulating region surrounding the plurality of resistance regions.

A light emitting device having a current confined layer according to another aspect of the present invention includes:

Board;

A micro heater capable of locally heating at a high temperature, the micro heater including a heating part provided on the substrate and a supporting part supporting the heating part;

A current confinement layer provided on the micro-heater;

A plurality of pn junction diodes provided on the current confined layer;

And a second electrode layer covering the upper portion of the pn junction diode.

When the light emitting device having the current limiting layer is used, the current flowing across the LEDs can be limited to a limit current even if some LEDs are shorted or operating abnormally, and the deviation of the current flowing across the LEDs of the light emitting device is reduced .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals refer to like elements, and the size and thickness of each element may be exaggerated for clarity of explanation.

 1 is a cross-sectional view schematically showing a light emitting device having a current confined layer according to an embodiment. 1, the light emitting device according to the present embodiment includes a substrate 100, a first electrode layer 110, a current confinement layer 120, a rod-shaped pn junction diode 125, and a second electrode layer 170 .

The first electrode layer 110 is provided on the substrate 100. The substrate 100 may be formed of, for example, glass or metal. The first electrode layer 110 may be formed of a metal such as Mo, Ni, or Ti. The current confined layer 120 is provided on the first electrode layer 110. Current confined layer 120 includes SiO x N y: B, SiO x N y: P, SiO x N y, SiN y: B, SiN y: P, SiO x: B, SiO x: P, SiN y , or SiO x And the like. Here, x may have a value of 0.05 or more and 2 or less. y may have a value of 0.01 or more and 1.33 or less. The current confining layer 120 can be formed by crystallizing by heating the materials to a high temperature. The materials can be heat treated to obtain the desired current-limiting layer 120 resistance. When the materials are heated to a high temperature, the resistance of the current confining layer 120 becomes small. Therefore, the resistance of the current confining layer 120 can be adjusted by heating the materials to a high temperature. The resistance of the current confining layer 120 may be between 30 OMEGA and 100 M [Omega].

On the current confining layer 120, a plurality of pn junction diodes 125 are provided. The pn junction diode 125 may be a nano rod or a micro-rod-shaped pn junction diode. The rod-shaped pn junction diode 125 may include an n-type semiconductor layer 130, an active layer 140, and a p-type semiconductor layer 150. For example, the n-type semiconductor layer 130 may be an n-type GaN layer, the active layer 140 may be an InGaN active layer, and the p-type semiconductor layer 150 may be a p-type GaN layer. The active layer 140 may be a single or multi-quantum well layer. 1 shows a diode having a pn junction formed in a vertical direction, but the present invention is not limited thereto. The rod-shaped pn junction diode 125 may be formed using, for example, MOCVD (Metal-Organic Chemical Vapor Deposition). The insulating layer 160 may be further provided on the same layer as the rod-shaped pn junction diode 125 to insulate the rod-shaped pn junction diodes 125 from each other. The upper end of the rod-shaped pn junction diode 125 may protrude above the insulating layer 160. The insulating layer 160 may be formed of, for example, a polymer, a polyamide, or a spin on glass (SOG) material. The insulating layer 160 may be formed using PECVD (Plasma Enhanced Chemical Vapor Deposition) or spin coating (Spin Coating). The upper portion of the p-type semiconductor layer 150 of the rod-shaped pn junction diode 125 is covered with the second electrode layer 170. The second electrode layer 170 may be formed by etching the insulating layer 160 by wet etching and then depositing Ni / Au. As the wet etching solution, for example, BOE (Buffered Oxide etchant) can be used. The second electrode layer 170 may be formed of a transparent electrode, for example, indium tin oxide (ITO).

Next, the operation of the light emitting device according to the present embodiment will be described. 2A is a diagram illustrating an equivalent circuit of a light emitting device having a current confined layer according to an embodiment. Referring to FIG. 2A, the light emitting device of the present embodiment may be an LED array 10 having a plurality of LEDs. Each of the LEDs of the LED array 10 is connected in series with a current-limiting layer having a resistance value R. In addition, a voltage V app is applied to the LED and current limiting layer of the LED array 10. Figure 2b schematically shows the current-voltage characteristic between the LEDs improved by the light emitting device with the current confined layer. Referring to FIG. 2B, the V LED axis represents the voltage applied to the LED, and the I axis represents the current flowing through the LED. The first straight line is a straight line showing the current-voltage relationship at both ends of the shorted LED1. If the LED1 is shorted or broken, the slope of the first straight line may be very large, since the resistance at both ends of the LED1 may approach almost zero. And Curves 2, 3 and 4 are curves showing the current-voltage relationship at both ends of the normally operating LED2 to LED4. Line 5 is a straight line showing the current-voltage relationship across the LED when the current-limiting layer is connected in series to each LED. I limit is the maximum limit current at which the LED can operate normally. The current and voltage across the shorted LED1 are determined at the intersection 20 where the first straight line and the fifth straight line meet. When a current of i 1 (A) flows through the current limiting layer having the resistance value R and the LED 1 , a voltage of i 1 R (V) is applied to the current limiting layer and a voltage applied to the current limiting layer The voltage V app -i 1 R (V) is applied. The current and voltage across the remaining LED2 through LED4 are determined at the intersection of curves 2, 3 and 4 and line 5. The current deviation is calculated from the difference between the current value at the intersection 30 of the curve 4 and the curve 5 at the LED 4 in which the minimum current flows from the current value at the intersection 20 of the first straight line and the fifth straight line at the LED 1, Minus the current value. The relationship between the voltage across the LED (V LED ) and the current across the LED (I) is as follows.

V app = IR + V LED

Where V app is the voltage supplied to the LED array, I is the current flowing across the LED, R is the resistance of the current limiting layer, and V LED is the voltage across the LED. When a current limiting layer having a specific resistance value (R) is connected in series to the LED, current is limited so that the current flowing through the LED and the current flowing through the current confining layer are equal. That is, the current flowing across the LEDs is determined by Equation (1).

3A is a diagram showing an equivalent circuit of a nanostructured LED array or a poly-crystalline LED array, which is a comparative example. FIG. 3B is a graph showing a relationship between a current flowing across each LED and a voltage across each LED in a nanorod shaped LED array or polycrystalline LED array of a comparative example. Referring to FIG. 3B, the V LED axis represents the voltage applied to the LED, and the I axis represents the current flowing through the LED. The first straight line is a straight line showing the current-voltage relationship at both ends of the shorted LED1. When LED1 is shorted, since the resistance at both ends of LED1 is close to zero, the slope can be large enough so that the first straight line converges to the I axis. And curves 2, 3, and 4 are curves showing the current-voltage relationship between the LEDs 2 to 4, which are normal. I limit is the maximum limit current at which the LED can operate normally. Nanostructured LED arrays or polycrystalline LED arrays are difficult to fully control for uniformity, and many surface defects can cause shorts in some LEDs. Therefore, there is a problem that the current-voltage characteristics between the both ends of the LED are uneven and the performance of the entire device is deteriorated. When the LED 1 is short-circuited, there is a problem that the current flowing in the LED 1 exceeds the limit current, or the current deviation becomes large and the operation of the device becomes impossible or the power consumption becomes large. According to the light emitting device according to this embodiment, even if some of the LED arrays are short-circuited or abnormally operated, the current flowing across the LEDs is limited to the limit current I limit and the current deviation between the LEDs is reduced, And the performance of the LED array is improved. In the LED of the light emitting device having the current confining layer 120, the current confining layer 120 is connected in series to the pn junction diode 125. the current flowing across the pn junction diode 125 becomes equal to the current flowing through the current confinement layer 120 having a specific resistance value. Therefore, the current flowing across the pn junction diode 125 is limited to the limit current I limit , and the current deviation between the currents flowing through the plurality of pn junction diodes 125 is also reduced. the surface leakage current of the pn junction diode 125 also flows through the current confining layer 120 and is limited to within the limit current I limit .

4 is a cross-sectional view schematically showing a light emitting device having a current confined layer according to another embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to FIG. 4, the light emitting device of this embodiment may include a substrate 200, a first electrode layer 210, a current confining layer 220, a pn junction diode 225, and a second electrode layer 270. The first electrode layer 210 is provided on the substrate 200. The current confining layer 220 is provided on the first electrode layer 210. Current confined layer 220 includes SiO x N y: B, SiO x N y: P, SiO x N y, SiN y: B, SiN y: P, SiO x: B, SiO x: P, SiN y , or SiO x And the like. Here, x may have a value of 0.05 or more and 2 or less. y may have a value of 0.01 or more and 1.33 or less. The current confining layer 220 may be formed by crystallizing by heating the materials to a high temperature. The materials may be heat treated to obtain the desired current-limiting layer 220 resistance. When the materials are heated to a high temperature, the resistance of the current confining layer 220 becomes small. Accordingly, the resistance of the current confining layer 220 can be adjusted by heating the materials to a high temperature. The resistance of the current confining layer 220 may be 30 [Omega] to 100 M [Omega].

On the current confinement layer 220, a plurality of pn junction diodes 225 are provided. The pn junction diode 225 shown in Fig. 4 is a polycrystalline pn junction diode. The polycrystalline pn junction diode 225 may include an n-type semiconductor layer 230, an active layer 240, and a p-type semiconductor layer 250. For example, the n-type semiconductor layer 230 may be an n-type GaN layer, the active layer 240 may be an InGaN active layer, and the p-type semiconductor layer 250 may be a p-type GaN layer. The active layer 240 may be a single or multi-quantum well layer. The insulating layer 260 may be further provided on the same layer as the polycrystalline pn junction diode 225 to isolate the polycrystalline pn junction diodes 225 from each other. The upper end of the polycrystalline pn junction diode 225 may protrude above the insulating layer 260. The upper portion of the p-type semiconductor layer 250 of the polycrystalline pn junction diode 225 is covered with the second electrode layer 270.

The operation of the light emitting device according to this embodiment is as described above. the current flowing across the pn junction diode 225 becomes equal to the current flowing through the current limiting layer 220 having a specific resistance value. Therefore, the current flowing across the pn junction diode 225 is limited to the limit current I limit , and the current deviation between the currents flowing through the plurality of pn junction diodes 225 is also reduced. the surface leakage current of the pn junction diode 225 is also limited to the limit current I limit since it flows through the current limiting layer 220.

5 is a cross-sectional view schematically showing a light emitting device having a current confined layer according to another embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

Referring to FIG. 5, the light emitting device of this embodiment may include a substrate 300, a first electrode layer 310, a current confinement layer 320, a pn junction diode 327, and a second electrode layer 360.

The first electrode layer 310 is provided on the substrate 300. The current confinement layer 320 is provided on the first electrode layer 310. The current confining layer may include a plurality of resistive regions 325 and isolation regions 323 spaced apart. A plurality of resistance regions 325 may be provided below the pn junction diode 327. The insulating region 323 may be provided to surround the plurality of resistance regions 325. The resistance region 325 may be formed by performing at least one of a heat treatment and a chemical treatment locally on the current confining layer 320 of the portion where the pn junction diode 327 is to be grown. Resistance region 325 is SiO x N y: B, SiO x N y: P, SiO x N y, SiN y: B, SiN y: P, SiO x: B, SiO x: P, SiN y , or SiO x And the like. Here, x may have a value of 0.05 or more and 2 or less. y may have a value of 0.01 or more and 1.33 or less. The resistive region 325 may be formed by crystallizing by heating the materials to a high temperature. The materials can be heat treated to obtain the resistance of the desired resistance region 325. When the materials are heated to a high temperature, the resistance of the resistance region 325 becomes small. Thus, the materials can be heated to a high temperature to regulate the magnitude of the resistance in the resistive region 325. The resistance of the resistive region 325 may be between 30 OMEGA and 100 M [Omega].

A plurality of pn junction diodes 327 are provided in the plurality of resistance regions 325, respectively. The pn junction diode 327 may include an n-type semiconductor layer 330, an active layer 340, and a p-type semiconductor layer 350. For example, the n-type semiconductor layer 330 may be an n-type GaN layer, the active layer 340 may be an InGaN active layer, and the p-type semiconductor layer 350 may be a p-type GaN layer. The active layer 140 may be a single or multi-quantum well layer. The pn junction diode 327 shown in Fig. 5 is a polycrystalline pn junction diode. Although not shown in the figure, the pn junction diode 327 may be a nano-bar or a micro-rod-shaped pn junction diode. The pn junction of the nanorod or micro-rod-shaped pn junction diode may be formed in a radial direction. The p-type semiconductor layer 350 of the polycrystalline pn junction diode 327 is surrounded by the second electrode layer 360. The operation of the light emitting device according to this embodiment is as described above. The role of the resistance region 325 is the same as the role of the current confinement layer described above.

6 is a cross-sectional view schematically showing a light emitting device having a current confined layer according to another embodiment. Hereinafter, differences from the above-described embodiment will be mainly described.

6, the light emitting device according to the present exemplary embodiment may include a substrate 400, a micro-heater 410, a current confining layer 420, a pn junction diode 425, and a second electrode layer 470 . The micro heater 410 is provided on the substrate 400. The micro heater 410 may include a heating part 410a in the form of a flat plate and a supporting part 410b supporting the heating part 410a provided on the substrate 400. The heating portion 410a may be formed of, for example, molybdenum, tungsten, silicon carbide, or the like, and may emit light and generate heat by power application. The support portion 410b may be formed of a material having a low thermal conductivity to prevent heat loss from the heating portion 410a. The support 410b may be, for example, SiO x Or Si 3 N 4 or the like. The microheater 410 may be used to form a pn junction requiring a high temperature process. The microheater 410 can heat only the portion where the pn junction is formed to locally high temperature while maintaining the temperature inside the chamber, especially the temperature of the substrate, at room temperature. In this case, since the temperature of the glass substrate can be maintained at room temperature, a high-quality pn junction can be formed on the glass substrate. Thereby forming a large-area pn junction. In addition, the micro-heater 410 may be used as the first electrode layer. A current limiting layer 420 is provided on the microheater 410. On the current confining layer 420, a plurality of pn junction diodes 425 are provided. The pn junction diode 425 may be a pn junction diode in the form of a nanorod or microstrip or a polycrystalline pn junction diode. The pn junction diode 425 shown in FIG. 6 is a rod-shaped pn junction diode, but not limited thereto. The pn junction diode 425 may include an n-type semiconductor layer 430, an active layer 440, and a p-type semiconductor layer 450. For example, the n-type semiconductor layer 430 may be an n-type GaN layer, the active layer 440 may be an InGaN active layer, and the p-type semiconductor layer 450 may be a p-type GaN layer. The active layer 140 may be a single or multi-quantum well layer. The insulating layer 460 may be further provided on the same layer as the rod-shaped pn junction diode 425 to insulate the rod-shaped pn junction diodes 425 from each other. The upper end of the rod-shaped pn junction diode 425 may protrude above the insulating layer 460. The upper portion of the p-type semiconductor layer 450 of the rod-shaped pn junction diode 425 is covered with the second electrode layer 470. The operation of the light emitting device according to the present embodiment and the role of the current confining layer 420 are as described above.

The light emitting device having the current confined layer according to the present invention has been described with reference to the embodiments shown in the drawings for the sake of understanding. However, those skilled in the art will appreciate that various modifications and variations It will be appreciated that other embodiments are possible. Accordingly, the true scope of the present invention should be determined by the appended claims.

1 is a cross-sectional view schematically showing a light emitting device according to an embodiment of the present invention.

2A is a diagram illustrating an equivalent circuit of an LED array according to an embodiment of the present invention.

2B is a graph schematically illustrating the current-voltage characteristic across the LED improved by the LED array shown in FIG. 2A.

3A is a diagram showing an equivalent circuit of the LED array of the comparative example.

FIG. 3B is a graph showing a relationship between a current flowing through the LED and a voltage across the LED according to the short-circuit of the LED 1 in the LED array of the comparative example.

4 is a cross-sectional view schematically showing a light emitting device according to another embodiment of the present invention.

5 is a cross-sectional view schematically showing a light emitting device according to another embodiment of the present invention.

6 is a cross-sectional view schematically showing a light emitting device according to another embodiment of the present invention.

Claims (13)

Board; A first electrode layer provided on the substrate; A current confinement layer provided on the first electrode layer; A plurality of pn junction diodes provided on the current confined layer; And a second electrode layer covering the upper portion of the pn junction diode, The current limiting layer is SiO x N y: with P, SiN y, or SiO x: B, SiO x N y: P, SiO x N y, SiN y: B, SiN y: P, SiO x: B, SiO x , ≪ / RTI > Wherein the current confined layer has a resistance determined by heating any one of the groups selected from the group. The method according to claim 1, Wherein each of the plurality of pn junction diodes includes a p-type semiconductor layer, an active layer, and an n-type semiconductor layer. 3. The method of claim 2, Wherein the p-type semiconductor layer is a p-type GaN layer, the active layer is an InGaN active layer, and the n-type semiconductor layer is an n-type GaN layer. 3. The method according to claim 1 or 2, Wherein the plurality of pn junction diodes are nano rod or micro rod-shaped pn junction diodes. 5. The method of claim 4, And an insulating layer for insulating the plurality of pn junction diodes from each other. 3. The method according to claim 1 or 2, Wherein the plurality of pn junction diodes are poly-crystalline pn junction diodes. The method according to claim 6, And an insulating layer for insulating the plurality of pn junction diodes from each other. 3. The method according to claim 1 or 2, And the resistance of the current confining layer is 30 to 100 M ?. delete The method according to claim 1, X is 0.05? X? 2. delete The method according to claim 1, Wherein the current confining layer includes a plurality of resistance regions provided under the plurality of pn junction diodes and an insulating region surrounding the plurality of resistance regions. Board; A micro heater capable of locally heating at a high temperature, the micro heater including a heating part provided on the substrate and a supporting part supporting the heating part; A current confinement layer provided on the micro-heater; A plurality of pn junction diodes provided on the current confined layer; And a second electrode layer covering the upper portion of the pn junction diode.
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479831A (en) 1980-09-15 1984-10-30 Burroughs Corporation Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment
KR100317989B1 (en) * 1999-12-27 2001-12-24 오길록 High luminance blue dc-electroluminescent display
KR100658938B1 (en) * 2005-05-24 2006-12-15 엘지전자 주식회사 Light emitting device with nano-rod and method for fabricating the same

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4160000B2 (en) * 2004-02-13 2008-10-01 ドンゴク ユニバーシティ インダストリー アカデミック コーポレイション ファウンデイション Light emitting diode and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4479831A (en) 1980-09-15 1984-10-30 Burroughs Corporation Method of making low resistance polysilicon gate transistors and low resistance interconnections therefor via gas deposited in-situ doped amorphous layer and heat-treatment
KR100317989B1 (en) * 1999-12-27 2001-12-24 오길록 High luminance blue dc-electroluminescent display
KR100658938B1 (en) * 2005-05-24 2006-12-15 엘지전자 주식회사 Light emitting device with nano-rod and method for fabricating the same

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