JP6330486B2 - Semiconductor nanowire optical device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a semiconductor nanowire optical device and a method for manufacturing the same.

  An optical device using vertical semiconductor nanowires is expected as an optical device that has a small in-plane size and can be integrated at a high density. For example, light emitting elements such as LEDs using optical integrated circuit nanowires or optical integrated circuit nanocolumns have been proposed (see, for example, Patent Document 1). Or the application to a solar cell is proposed by using as a light absorption layer (for example, refer patent document 2).

  All of these applications are devices that emit light in and out of the long axis direction of the nanowire. On the other hand, in optical communication applications, an active device such as a light emitting / receiving element is often integrated with another waveguide type optical device such as an optical modulator or multiplexer / demultiplexer to constitute an optical device.

  In particular, from the viewpoint of miniaturization and cost reduction, there is a technology for manufacturing an optical modulator or multiplexer / demultiplexer recently called silicon photonics on a Si wafer with a Si-based material or a material system that matches the Si-CMOS process. It is developing.

  However, since Si-based semiconductors are indirect transition semiconductors, it is necessary to integrate compound semiconductor elements for active elements, particularly light emitting elements, from the viewpoint of efficiency, and use of compound semiconductor nanowires is also expected.

JP 2008-108924 A JP 2010-028092 A

  Light input / output from a light emitting / receiving element made of a compound semiconductor nanowire must be coupled laterally with the optical waveguide. However, the conventional surface incident type nanowire optical device has a problem that light cannot be directly coupled to the optical waveguide connected in the lateral direction.

  Therefore, when forming a light emitting device or the like with compound semiconductor nanowires, it is conceivable to sequentially stack a lower cladding layer / active layer / upper cladding layer in the growth direction and extract light in the lateral direction. However, there is a problem that light cannot be extracted with high efficiency in the structure in which the lower clad layer / active layer / upper clad layer are sequentially laminated in the growth direction. This situation will be described with reference to FIG.

FIG. 12 is an explanatory view of a vertical semiconductor nanowire light emitting device, FIG. 12 (a) is a perspective view of the vertical semiconductor nanowire light emitting device, and FIG. 12 (b) is an explanatory view of optical coupling efficiency. As shown in FIG. 12A, in order to extract light from the lateral direction, an SiO ₂ film 82 having an opening is provided in an n-type Si substrate 81, and the n-type cladding layer 84 / active layer 85 / The vertical semiconductor nanowire light emitting element 83 may be formed by sequentially stacking the p-type cladding layer 86.

  As shown in FIG. 12A, the vertical semiconductor nanowire light-emitting element 83 having a small cross-sectional area in the lateral direction and high symmetry in shape emits light isotropically in all directions in the lateral direction. Furthermore, there is a component that emits light in the vertical direction, that is, in the nanowire major axis direction. Here, it is assumed that the active layer 85 exists in the center of the nanowire as a region that is sufficiently shorter than the length of the nanowire and does not have special polarization dependency.

  As shown in FIG. 12 (b), in the configuration in which the dielectric optical waveguide 87 is simply placed on the vertical semiconductor nanowire light emitting element 83, the proportion of light that can be extracted from the dielectric optical waveguide 87 is small. Even if the vertical semiconductor nanowire light emitting element 83 that is sufficiently thinner than the dielectric optical waveguide 87 is used and reflection at the end face of the dielectric optical waveguide is sufficiently suppressed, the dielectric optical waveguide 87 out of the light emitted in the lateral direction A small percentage can be combined.

For example, as shown in FIG. 12 (b), 2θ is the expected angle of the dielectric optical waveguide 87 from the center of the vertical semiconductor nanowire light-emitting element 83, and the dielectric optical waveguide from the center of the vertical semiconductor nanowire light-emitting element 83 is used. When the distance to the end face of 87 is d and the width of the dielectric optical waveguide 87 is w, the optical coupling efficiency η is 2θ / 2π. Here, since tan θ is w / 2d, θ is tan ⁻¹ (w / 2d). Therefore, the optical coupling efficiency η is
η = 2θ / 2π = 2 tan ⁻¹ (w / 2d) / 2π
It becomes.

For example, when the dielectric optical waveguide 87 having a width w of 1 μm is disposed 500 nm away from the vertical semiconductor nanowire light emitting device 83, the optical coupling efficiency η is η = 2 tan ⁻¹ (1) / 2π = 2 × (π / 4) / 2π = 1/4
And stays at 25%. The same applies to the vertical semiconductor nanowire light receiving element.

  Accordingly, an object of the semiconductor nanowire optical device is to increase the optical coupling efficiency between the nanowire and the dielectric optical waveguide with respect to lateral light.

From one aspect to be disclosed, a semiconductor substrate of a first conductivity type, a dielectric optical waveguide provided on the semiconductor substrate, and in the vicinity of one light input / output end face of the dielectric optical waveguide on the semiconductor substrate. The width of the dielectric optical waveguide in which a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer opposite to the first conductive type are sequentially stacked in a grid pattern at a constant pitch. The first of the at least one vertical semiconductor nanowire including a plurality of smaller vertical semiconductor nanowires of the same size and the vertical semiconductor nanowire directly opposed to the light input / output end face of the dielectric optical waveguide among the vertical semiconductor nanowires A first electrode provided on a two-conductivity-type semiconductor layer and a second electrode provided on the semiconductor substrate, wherein a refractive index of a dielectric core layer of the dielectric optical waveguide is equal to that of the active layer; Refractive index and the vertical half Have a refractive index between the refractive index of the surrounding covering the outer periphery of the body nanowires, said constant pitch is a half a cycle of the optical path length of the emission wavelength of the vertical semiconductor nanowire having a first electrode A semiconductor nanowire optical device characterized in that the pitch is the same is provided.

According to another aspect of the disclosure, a step of laminating a multilayer dielectric film including a dielectric core layer on a first conductivity type semiconductor substrate, and etching the multilayer dielectric film to form a dielectric optical waveguide And a dielectric thin film serving as a selective growth mask, and the dielectric optical waveguide arranged in a lattice at a constant pitch on the dielectric thin film in the vicinity of one light input / output end face of the dielectric optical waveguide Forming an opening of the same size smaller than the width of the first conductive type semiconductor layer, an active layer, and a first conductive type opposite to the first conductive type on the semiconductor substrate exposed in the opening. sequentially laminating a second conductivity type semiconductor layer have a forming a vertical semiconductor nanowires, wherein the predetermined pitch is the pitch and one cycle half the optical path length of the emission wavelength of the vertical semiconductor nanowires With features That the method for manufacturing a semiconductor nanowire light device is provided.

  According to the disclosed semiconductor nanowire optical device and the manufacturing method thereof, it is possible to increase the optical coupling efficiency between the nanowire and the dielectric optical waveguide with respect to lateral light.

It is explanatory drawing of the semiconductor nanowire optical apparatus of embodiment of this invention. It is explanatory drawing of the condensing principle of the semiconductor nanowire optical apparatus of embodiment of this invention. It is explanatory drawing of the semiconductor nanowire light-emitting device of Example 1 of this invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor nanowire light-emitting device of Example 1 of this invention. It is explanatory drawing to the middle after FIG. 4 of the manufacturing process of the semiconductor nanowire light-emitting device of Example 1 of this invention. It is explanatory drawing after FIG. 5 of the manufacturing process of the semiconductor nanowire light-emitting device of Example 1 of this invention. It is a notional top view of the semiconductor nanowire light-emitting device of Example 2 of this invention. It is a notional sectional view of a semiconductor nanowire optical integrated circuit device of Example 3 of the present invention. It is explanatory drawing to the middle of the manufacturing process of the semiconductor nanowire optical integrated circuit device of Example 3 of this invention. It is explanatory drawing to the middle after FIG. 9 of the manufacturing process of the semiconductor nanowire optical integrated circuit device of Example 3 of this invention. It is explanatory drawing after FIG. 10 of the manufacturing process of the semiconductor nanowire optical integrated circuit device of Example 3 of this invention. It is explanatory drawing of a vertical semiconductor nanowire light emitting element.

  Here, with reference to FIG.1 and FIG.2, the semiconductor nanowire optical apparatus of embodiment of this invention is demonstrated. FIG. 1 is an explanatory diagram of a semiconductor nanowire optical device according to an embodiment of the present invention, FIG. 1 (a) is a schematic plan view, and FIG. 1 (b) is an AA ′ in FIG. 1 (a). It is sectional drawing along the dashed-dotted line to connect. As shown in the figure, a dielectric optical waveguide 15 is provided on a semiconductor substrate 11 of the first conductivity type, and a plurality of vertical types are arranged in a lattice pattern at a constant pitch in the vicinity of one light input / output end face of the dielectric optical waveguide 15. Semiconductor nanowires 17 are arranged.

  The semiconductor substrate 11 is typically a group IV semiconductor substrate, and in particular, a Si substrate, a Ge substrate, a C substrate, a SiGe substrate, or the like having a (111) plane as a main surface is used. The vertical semiconductor nanowire 17 has a second conductivity type opposite to the first conductivity type that becomes the first conductivity type semiconductor layer, the active layer 19, and the upper clad layer 20 that becomes the lower cladding layer 18. It has a stacked structure in which semiconductor layers are sequentially stacked. The active layer may be either a light-emitting layer or a light-receiving layer. In particular, by making the active layer a III-V compound semiconductor quantum well structure active layer having a quantum well layer having tensile strain, highly efficient semiconductor nanowire light emission It can be set as an element. In other words, in tensile strained quantum wells, the emission transition occurs between the conduction band and the valence band of light holes, so the TM mode light that can propagate only in the lateral direction is dominant in the major axis direction of the nanowire. This is because it occurs. When a quantum well structure is used, a single quantum well structure may be used, but it is desirable to employ a multiple quantum well structure (MQW) in order to increase the light intensity.

  A first electrode 22 is provided on the upper cladding layer 20 of at least one vertical semiconductor nanowire 17 facing the input / output end face of the dielectric optical waveguide 15 among the plurality of vertical semiconductor nanowires 17 to form an active element. A second electrode 23 is provided on the semiconductor substrate 11.

At this time, the material is selected so that the refractive index of the dielectric core layer 13 of the dielectric optical waveguide 15 has a refractive index between the refractive index of the active layer 19 and the refractive index around the vertical semiconductor nanowire 17. . Typically, the dielectric optical waveguide 15 has a laminated structure in which the lower cladding layer 12 is an SiO ₂ film, the dielectric core layer 13 is an SiN film, and the upper cladding layer 14 is an SiO ₂ film. Further, it is desirable from the viewpoint of strength and the like to provide a resin embedding layer such as BCB (benzocyclobutene) resin around the vertical semiconductor nanowire 17.

  As the semiconductor substrate, a single crystal Si substrate of an SOI substrate may be used. In this case, a Si core layer that processes the single crystal Si layer of the SOI substrate and connects it to the dielectric optical waveguide 15 and optical modulation. A vessel may be provided. A typical example of the optical modulator in this case is a Mach-Zehnder type Si optical modulator comprising a branch arm.

  In order to form such a semiconductor nanowire, a multilayer dielectric film including a dielectric core layer 13 is stacked on the first conductivity type semiconductor substrate 11, and the multilayer dielectric film is etched to produce a dielectric optical waveguide. A dielectric thin film to be the waveguide 15 and the selective growth mask 16 is formed. Next, openings arranged in a lattice at a constant pitch are formed in the selective growth mask in the vicinity of one light input / output end face of the dielectric optical waveguide 15. Next, a vertical semiconductor nanowire 17 is formed by sequentially laminating a first conductive type semiconductor layer that becomes the lower clad layer 18, an active layer 19, and a second conductive type semiconductor layer that becomes the upper clad layer 20 in the opening. What is necessary is just to form.

  In the case of using an SOI substrate, a part of the embedded insulating single crystal Si layer is removed before the dielectric multilayer film is stacked, and a dielectric multilayer film including the dielectric core layer 13 is formed in the removed portion. Just do it. At that time, the single crystal Si layer may be processed to form an Si core layer connected to the dielectric optical waveguide 15 and an Si optical modulator connected to the Si optical waveguide.

  Next, the light collection principle of the semiconductor nanowire optical device according to the embodiment of the present invention will be described with reference to FIG. FIG. 2 is an explanatory diagram of the light collection principle of the semiconductor nanowire optical device according to the embodiment of the present invention. Generally, it is known that when structures having different refractive indexes with respect to the surrounding environment are regularly arranged, light having a wavelength that satisfies a certain relationship with the period is modulated. In particular, when the optical distance half of the target wavelength is repeated as one period, the periodic structure acts as a reflecting mirror. Here, the optical distance is expressed by nxd obtained by multiplying the thickness d of the material by the refractive index n of the material.

  As a result of intensive studies, when a semiconductor nanowire is regarded as such a structure, it is configured to be a reflector for the near-infrared wavelength region of 1.3 μm or 1.55 μm expected for silicon photonics applications. I found out. For example, by arranging InP nanowires with a refractive index of 3.2 and a diameter of 100 nm in a BCB resin with a refractive index of 1.5 in a lattice shape at intervals of 220 nm, a structure that reflects with respect to a wavelength of 1.3 μm is obtained. I found it.

  Based on this knowledge, as shown in FIG. 2A, semiconductor nanowires 32 are arranged in a lattice pattern around the semiconductor nanowire light emitting element 31, and the semiconductor nanowires 32 are removed only in one direction. Then, it was found that the light emitted in the lateral direction from the semiconductor nanowire light emitting element 31 can be collected in the removed direction.

  Furthermore, in order to guide this light well into the waveguide, as shown in FIG. 2B, it is essential to dispose the optical waveguide in a linear gap. At this time, the optical waveguide is a core having a refractive index intermediate between the active layer of the semiconductor nanowire light emitting element 31 and the surrounding environment (in the case of providing an embedded resin layer, the refractive index of the embedded resin layer). As a result of examination, it was found for the first time that it was necessary to be configured.

  As an optical waveguide satisfying such conditions, a dielectric optical waveguide 33 having a dielectric core layer is suitable. Si optical waveguides are not suitable because the refractive index of Si is too high. With the arrangement shown in FIG. 2B, it is possible to couple the component emitted in the lateral direction from the semiconductor nanowire light emitting element 31 to the dielectric optical waveguide 33 with high efficiency.

  In the present invention, a semiconductor wire having a diameter of less than 500 nm is defined as the semiconductor nanowire 32. Considering the positional relationship between the size (diameter and length) of the semiconductor nanowire 32 and the dielectric optical waveguide 33, the scale is difficult in a top-down process such as dry etching. Can only be manufactured.

Next, with reference to FIG. 3 thru | or FIG. 6, the semiconductor nanowire light-emitting device of Example 1 of this invention is demonstrated. FIG. 3 is an explanatory diagram of the semiconductor nanowire light-emitting device of Example 1 of the present invention, FIG. 3 (a) is a schematic plan view, and FIG. 3 (b) is an A-A ′ in FIG. It is sectional drawing along the dashed-dotted line to connect. As shown in the figure, a dielectric optical waveguide 45 comprising a SiO ₂ film 42 / SiN film 43 / SiO ₂ film 44 is provided on an n-type Si substrate 41, and in the vicinity of one light input / output end face of the dielectric optical waveguide 45. A plurality of semiconductor nanowires 48 are arranged in a lattice pattern at a constant pitch.

The dielectric optical waveguide 45 includes a SiO ₂ film 42 having a thickness of 2000 nm, a SiN film 43 having a thickness of 400 nm, and a SiO ₂ film 44 having a thickness of 2000 nm, and has a width of 400 nm. Note that the refractive index of SiO ₂ is 1.4, and the refractive index of SiN is 2.0.

  The semiconductor nanowire 48 is formed by sequentially growing an n-type InP cladding layer 49 having a thickness of 2000 nm, an MQW active layer 50 having a thickness of 400 nm, and a p-type InP cladding layer 51 having a thickness of 2000 nm. The MQW active layer 50 has an InGaAsP barrier with a wavelength composition of 1.05 μm, and a tensile strained quantum well structure with an In composition ratio of 45% and an InGaAs well layer with an emission wavelength of 1.3 μm band. Here, ten InGaAs well layers are provided.

  The semiconductor nanowire 48 has a diameter of 80 nm to 120 nm and a pitch of 200 nm to 220 nm. Further, a BCB resin embedding layer 52 is provided by filling a gap between adjacent semiconductor nanowires 48 with a BCB resin having a refractive index of 1.5. Finally, the p-side electrode 53 is provided on the p-type InP cladding layer 51 of one semiconductor nanowire 48 facing the dielectric optical waveguide 45, and the n-side electrode 54 is provided on the exposed portion of the n-type Si substrate 41.

  The semiconductor nanowire 48 provided with the p-side electrode 53 serves as a semiconductor nanowire light-emitting element, and the other semiconductor nanowires 48 serve as reflectors. When a forward bias is applied between the p-side electrode 53 and the n-side electrode 54, recombination light emission occurs in the MQW active layer 50, and the emitted light is reflected directly or by the surrounding semiconductor nanowire 48 to be a dielectric optical waveguide. 45.

Next, with reference to FIG. 4 thru | or FIG. 6, the manufacturing process of the semiconductor nanowire light-emitting device of Example 1 of this invention is demonstrated. In addition, the upper figure in each figure is a top view, and the lower figure is a side view including a partial cross section. First, as shown in FIG. 4A, an SiO ₂ film 42 having a thickness of 2000 nm and an SiN film having a thickness of 400 nm are formed on an n-type Si substrate 41 having a (111) plane as a main surface using a CVD method. 43 and a SiO ₂ film 44 having a thickness of 2000 nm are sequentially deposited.

Next, as shown in FIG. 4B, a dielectric waveguide 45 having a width of 400 nm is formed by lithography and etching. At this time, the selective growth mask 46 is formed by leaving the SiO ₂ film 42 by 50 nm.

  Next, as shown in FIG. 5C, an opening 47 is formed in the nanowire forming portion by etching to expose the surface of the n-type Si substrate 41. The diameter of the opening 47 is 80 nm to 120 nm, and the pitch is 200 nm to 220 nm.

  Next, as shown in FIG. 5D, an n-type InP cladding layer 49 having a thickness of 2000 nm and a thickness of 350 nm to 450 ° C. using a MOVPE (metal organic chemical vapor deposition) method. A 400 nm MQW active layer 50 and a 2000 nm thick p-type InP cladding layer 51 are sequentially grown to form a semiconductor nanowire 48. The MQW active layer 50 is grown alternately with an InGaAsP barrier with a wavelength composition of 1.05 μm and an InGaAs well layer with an In composition ratio of 45% so that there are 10 InGaAs well layers.

At this time, when the n-type InP clad layer 49 is grown, TMIn (trimethylindium), PH ₃ as a raw material, H ₂ S as a dopant source, and an S concentration of 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 are used. ^The flow rate is controlled to be ¹⁹ cm ⁻³ . On the other hand, when growing the p-type InP cladding layer 51, TMIn and PH ₃ are used as raw materials, DEZn (diethyl zinc) is used as a dopant source, and the Zn concentration is 5 × 10 ¹⁷ cm ⁻³ to 2 × 10 ¹⁸ cm ^{−. The} flow rate is controlled to be ³ . Further, when the MQW active layer 50 is grown, TEGa (triethylgallium) is used as the Ga material, and AsH ₃ is used as the As material.

  Next, as shown in FIG. 6E, the gap between adjacent semiconductor nanowires 48 is filled with BCB resin to form a BCB resin buried layer 52. Next, as shown in FIG. 6D, a p-side electrode 53 is provided on the p-type InP cladding layer 51 of one semiconductor nanowire 48 facing the dielectric optical waveguide 45. On the other hand, by forming an opening in the selective growth mask 46 and forming the n-side electrode 54 for the n-type Si substrate 41, the basic configuration of the semiconductor nanowire light-emitting device of Example 1 of the present invention is completed.

  In the first embodiment of the present invention, since the semiconductor nanowires are arranged in a lattice pattern at a constant pitch around one semiconductor nanowire 48 to be a light emitting element, the light from one semiconductor nanowire 48 is obtained. Can be efficiently guided to the dielectric optical waveguide 45. In order to reduce the contact resistance of the p-side electrode 53, a p-type InGaAs contact layer having a thickness of about 10 nm to 50 nm may be formed on the p-type InP cladding layer 51.

  Next, the semiconductor nanowire light-emitting device according to the second embodiment of the present invention will be described with reference to FIG. 7. The basic structure and the manufacturing process are the same as those described above only by forming a plurality of semiconductor nanowires serving as light-emitting elements. Since it is similar to Example 1, only a plan view is shown. FIG. 7 is a conceptual plan view of the semiconductor nanowire light-emitting device according to the second embodiment of the present invention. The diameter and pitch of the semiconductor nanowires 48 so that the two rows of semiconductor nanowires 48 face the width of the dielectric optical waveguide 45. And a p-side electrode 53 is provided on a total of four semiconductor nanowires 48 to form a semiconductor nanowire light-emitting element.

  In Example 2, since the four semiconductor nanowires are semiconductor nanowire light emitting elements, the derived light intensity can be increased. In the figure, four semiconductor nanowire light emitting elements are used, but the number is arbitrary.

  Next, with reference to FIGS. 8 to 11, a semiconductor nanowire optical integrated circuit device according to Example 3 of the present invention will be described. Since the basic configuration is the same as that of the first embodiment, only a side view including a partial cross section is shown. FIG. 8 is a schematic side view of the semiconductor nanowire optical integrated circuit device according to the third embodiment of the present invention, in which an SOI substrate is used and Si core layers 64 and 66 are provided so as to be connected to the dielectric optical waveguide 69. A Si optical waveguide and a Si optical modulator 65 are provided. As the Si optical modulator, a Mach-Zehnder type optical modulator is used.

  The continuous light (CW light) generated by the semiconductor nanowire 72 provided with the p-side electrode 78 and propagated through the dielectric optical waveguide 69 having the SiN core layer 67 propagates to the Si core layer 64, and the Si light ahead of it. It is converted into a modulated optical signal by the optical modulator. In this case, alignment of the SiN core layer 67 and the Si core layer 64 is important so that light is not lost.

Next, a manufacturing process of the semiconductor nanowire optical integrated circuit device according to the third embodiment of the present invention will be described with reference to FIGS. First, as shown in FIG. 9A, an SiO ₂ film having a thickness of 2000 nm is provided as a BOX layer 62 on an n-type Si substrate 61 having a (111) plane as a main surface, and a (100) plane is formed thereon. An SOI substrate 60 provided with a single-crystal Si layer 63 having a thickness of 500 nm to 1000 nm with a main surface of 1 is prepared.

  Next, as shown in FIG. 9B, the single crystal Si layer 63 in the region where the dielectric optical waveguide and the semiconductor nanowire are formed is removed, and the single crystal Si layer 63 in the other region is patterned to increase the width. The 500 nm Si core layers 64 and 66 and the Si optical modulator 65 are formed. In this case, the Si optical modulator 65 is a Mach-Zehnder optical modulator.

Next, as shown in FIG. 9C, a 500 nm thick SiN core layer 67 and a 2000 nm thick SiO ₂ upper cladding layer 68 are deposited on the entire surface by CVD.

Next, as shown in FIG. 10D, the SiO ₂ upper cladding layer 68 through the BOX layer 62 are etched to form a dielectric optical waveguide 69 having a width of 500 nm. At this time, the selective growth mask 70 is formed by leaving the BOX layer 62 by 50 nm.

  Next, as shown in FIG. 10E, the selective growth mask of the nanowire forming part is etched to form an opening 71 to expose the surface of the n-type Si substrate 61. The diameter of the opening 71 is 80 nm to 120 nm, and the pitch is 200 nm to 220 nm.

  Next, as shown in FIG. 10 (f), using the MOVPE method, an n-type InP cladding layer 73 having a thickness of 2000 nm, an MQW active layer 74 having a thickness of 400 nm, and a growth temperature of 350 to 450 ° C. A semiconductor nanowire 72 is formed by sequentially growing a p-type InP clad layer 75 having a thickness of 2000 nm. The MQW active layer 74 is alternately grown with an InGaAsP barrier having a wavelength composition of 1.05 μm and an InGaAs well layer having an In composition ratio of 45% so that there are 10 InGaAs well layers. At this time, since the SiN core layer 67 is deposited on the entire surface, the Si core layers 64 and 66 and the Si optical modulator 65 can be protected in the process of forming the dielectric optical waveguide 69 and the semiconductor nanowire 72.

Next, as shown in FIG. 11G, the gap between adjacent semiconductor nanowires 72 is filled with BCB resin to form a BCB resin buried layer 76. Next, as shown in FIG. 11H, unnecessary SiN core layer 67 and SiO ₂ upper cladding layer 68 deposited on Si core layers 64 and 66 and Si optical modulator 65 are removed.

Then, as shown in FIG. 11 (i), after the entire surface to a thickness was formed an SiO ₂ upper clad layer 77 of 2000 nm, SiO ₂ upper clad layer deposited on the dielectric optical waveguide 69 and the semiconductor nanowire formation region 77 Remove. Next, a part of the selective growth mask 70 is removed to expose the n-type Si substrate 61. Next, a p-side electrode 78 is provided on the p-type InP clad layer (75) of one semiconductor nanowire 72 facing the dielectric optical waveguide 69, and an n-side electrode 79 is formed on the exposed portion of the n-type Si substrate 61. To do. Although not shown here, a contact hole is formed in the SiO ₂ upper cladding layer 77 and an electrode for the Si optical modulator 65 is formed, so that the semiconductor nanowire light according to the third embodiment of the present invention is used. The basic configuration of the integrated circuit device is completed.

  In the third embodiment of the present invention, since the BOX layer of the SOI substrate is the lower clad layer common to the dielectric optical waveguide 69 and the Si optical waveguide, the SiN core layer is also used when integrating the Si optical modulator 65 and the like. 67 and the Si core layer 64 can be satisfactorily aligned with each other.

Here, the following supplementary notes are attached to the embodiments of the present invention including Examples 1 to 3.
(Appendix 1) A semiconductor substrate of a first conductivity type, a dielectric optical waveguide provided on the semiconductor substrate, and a constant pitch on the semiconductor substrate in the vicinity of one light input / output end face of the dielectric optical waveguide. A plurality of smaller than the width of the dielectric optical waveguide, which is arranged in a grid pattern, and in which a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer opposite to the first conductive type are sequentially stacked. The second conductivity type of at least one vertical semiconductor nanowire including a vertical semiconductor nanowire of the same size and a vertical semiconductor nanowire directly opposed to the light input / output end face of the dielectric optical waveguide among the vertical semiconductor nanowires A first electrode provided on the semiconductor layer; and a second electrode provided on the semiconductor substrate, wherein a refractive index of a dielectric core layer of the dielectric optical waveguide is equal to a refractive index of the active layer. The vertical semiconductor nanowire Have a refractive index between the refractive index of the surrounding covering the outer periphery of the pitch said constant pitch is, that the one cycle half the optical path length of the emission wavelength of the vertical semiconductor nanowire having a first electrode the semiconductor nanowire light and wherein the at.
(Supplementary note 2) The semiconductor nanowire optical device according to supplementary note 1, wherein the active layer is a quantum well structure active layer including a quantum well layer having tensile strain.
(Supplementary note 3) The semiconductor nanowire optical device according to Supplementary note 1 or 2, wherein a resin embedding layer is provided around the periphery of the vertical semiconductor nanowire.
(Appendix 4) The appendix 1 to appendix 3, wherein the dielectric optical waveguide has a laminated structure of SiO ₂ lower cladding layer / SiN core layer / SiO ₂ upper cladding layer. Semiconductor nanowire optical device.
(Supplementary note 5) The semiconductor according to any one of supplementary notes 1 to 4, wherein the semiconductor substrate is a group IV semiconductor substrate, and the vertical semiconductor nanowire is a group III-V compound semiconductor nanowire. Nanowire optical device.
(Supplementary Note 6) The semiconductor substrate is the single crystal Si substrate of an SOI substrate in which a single crystal Si layer is provided on a single crystal Si substrate via a buried insulating film, and the single crystal Si layer is removed at the removal portion. 6. The semiconductor nanowire optical device according to any one of appendix 1 to appendix 5, wherein a dielectric optical waveguide and the plurality of vertical semiconductor nanowires are provided.
(Additional remark 7) It has Si optical waveguide connected to the dielectric optical waveguide, and Si optical modulator connected to the Si optical waveguide, Si core layer of the Si optical waveguide and Si optical modulator part, The semiconductor nanowire optical device according to appendix 6, wherein the semiconductor nanowire optical device is a Si core layer and a Si optical modulator formed by processing the single crystal Si layer.
(Appendix 8) A step of laminating a multilayer dielectric film including a dielectric core layer on a semiconductor substrate of the first conductivity type, and etching the multilayer dielectric film to form a dielectric optical waveguide and a selective growth mask Forming a dielectric thin film, and having the same size as the width of the dielectric optical waveguide arranged in a lattice at a constant pitch on the dielectric thin film in the vicinity of one light input / output end face of the dielectric optical waveguide And forming a first conductivity type semiconductor layer, an active layer, and a second conductivity type semiconductor layer opposite to the first conductivity type on the semiconductor substrate exposed in the opening. have a forming sequentially laminated to a vertical semiconductor nanowire, wherein the constant pitch, characterized in that half of the optical path length of the emission wavelength of the vertical semiconductor nanowire is a pitch and one cycle semiconductor Nanowire Manufacturing method of the device.
(Supplementary note 9) The semiconductor nanowire optical device according to supplementary note 8, comprising a step of embedding a periphery covering the outer periphery of the vertical semiconductor nanowire with a resin layer having a refractive index lower than that of the dielectric core layer. Manufacturing method.
(Supplementary Note 10) In the step of laminating the dielectric multilayer film, the semiconductor substrate is the single crystal Si substrate of an SOI substrate in which a single crystal Si layer is provided on a single crystal Si substrate via a buried insulating film. The method according to appendix 8 or appendix 9, wherein a multilayer dielectric film including the dielectric core layer is formed in the removal portion before the step of removing a part of the single crystal Si layer. Manufacturing method of semiconductor nanowire optical device.
(Additional remark 11) It has the process of processing the said single crystal Si layer, and forming the Si core layer of Si optical waveguide connected to the said dielectric optical waveguide, and Si optical modulator connected to the said Si optical waveguide The method for manufacturing a semiconductor nanowire optical device according to appendix 10, wherein:

DESCRIPTION OF SYMBOLS 11 Semiconductor substrate 12 Lower clad layer 13 Dielectric core layer 14 Upper clad layer 15 Dielectric optical waveguide 16 Selective growth mask 17 Vertical semiconductor nanowire 18 Lower clad layer 19 Active layer 20 Upper clad layer 21 Insulating buried layers 22 and 23 Electrode 31 Semiconductor nanowire light-emitting element 32 Semiconductor nanowire 33 Dielectric optical waveguide 41 N-type Si substrate 42 SiO ₂ film 43 SiN film 44 SiO ₂ film 45 Dielectric optical waveguide 46 Selective growth mask 47 Opening 48 Semiconductor nanowire 49 n-type InP cladding Layer 50 MQW active layer 51 p-type InP cladding layer 52 BCB resin buried layer 53 p-side electrode 54 n-side electrode 60 SOI substrate 61 n-type Si substrate 62 BOX layer 63 single crystal Si layer 64, 66 Si core layer 65 Si light modulator 67 SiN core layer 68 SiO ₂ upper clad layer 69 Collector optical waveguide 70 selective growth mask 71 opening 72 semiconductor nanowire 73 n-type InP cladding layer 74 MQW active layer 75 p-type InP cladding layer 76 BCB resin buried layer 77 SiO ₂ upper clad layer 78 p-side electrode 79 n-side electrode 81 n-type Si substrate 82 SiO ₂ film 83 vertical semiconductor nanowire light-emitting element 84 n-type cladding layer 85 active layer 86 p-type cladding layer 87 dielectric optical waveguide

Claims (5)

A first conductivity type semiconductor substrate;
A dielectric optical waveguide provided on the semiconductor substrate;
A first conductive semiconductor layer, an active layer, and a conductive material opposite to the first conductive type are arranged on the semiconductor substrate in a lattice pattern at a constant pitch in the vicinity of one optical input / output end face of the dielectric optical waveguide. A plurality of vertical semiconductor nanowires of the same size smaller than the width of the dielectric optical waveguide, in which second conductive semiconductor layers of the same type are sequentially stacked, and the light input / output end face of the dielectric optical waveguide of the vertical semiconductor nanowires A first electrode provided on the second conductive semiconductor layer of at least one vertical semiconductor nanowire including a vertical semiconductor nanowire directly opposed to
A second electrode provided on the semiconductor substrate,
It said dielectric optical waveguide of the dielectric core layer refractive index of, have a refractive index between the refractive index of the surrounding covering the outer periphery of the refractive index the vertical semiconductor nanowires of the active layer,
2. The semiconductor nanowire optical device according to claim 1, wherein the constant pitch is a pitch with one optical cycle half the emission wavelength of the vertical semiconductor nanowire provided with the first electrode as one cycle .   2. The semiconductor nanowire optical device according to claim 1, wherein the active layer is a quantum well structure active layer including a quantum well layer having tensile strain. 3. The semiconductor nanowire optical device according to claim 1, further comprising a resin embedding layer around an outer periphery of the vertical semiconductor nanowire. 4. The semiconductor substrate is the single crystal Si substrate of an SOI substrate in which a single crystal Si layer is provided on a single crystal Si substrate via a buried insulating film,
The semiconductor nanowire optical device according to any one of claims 1 to 3, wherein the dielectric optical waveguide and the plurality of vertical semiconductor nanowires are provided in a removal portion of the single crystal Si layer. Laminating a multilayer dielectric film including a dielectric core layer on a first conductivity type semiconductor substrate;
Etching the multilayer dielectric film to form a dielectric optical waveguide and a dielectric thin film serving as a selective growth mask;
A step of having openings of the same size smaller than the width of the dielectric optical waveguide arranged in a lattice at a constant pitch in the dielectric thin film in the vicinity of one light input / output end face of the dielectric optical waveguide ;
A vertical semiconductor nanowire is formed by sequentially stacking a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer opposite to the first conductive type on the semiconductor substrate exposed in the opening. possess and forming,
The method of manufacturing a semiconductor nanowire optical device, wherein the constant pitch is a pitch with an optical distance that is half the emission wavelength of the vertical semiconductor nanowire as one period .

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