JP4159187B2 - Carrier synchronous demodulator for PSK signal - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a contactless IC card (hereinafter referred to as “PICC (Proximity IC Card)”), and in particular, a PICC read / write device (PICC-R) for writing data into the PICC and reading data from the PICC. / W) relates to a carrier synchronous demodulator for receiving a PSK signal from a PICC.
[0002]
[Prior art]
The standards of PICC are defined in ISO (International Organization for Standardization) / IEC (International Electrotechnical Commission) 14443. Here, non-contact coupling devices such as the above PICC-R / W (hereinafter referred to as “ A type B of the PICC communication interface that defines the power and bidirectional nature of the field between the PICC (Proximity Coupling Device) and the PICC and the characteristics thereof will be briefly described.
[0003]
(1) Power transfer from PCD to PICC RF (Radio Frequency) A carrier (fc = 13.56 MHz) is sent from the PCD to the PICC in order to supply effective power to the PICC within the operation field. PICC rectifies the received carrier and creates a power supply necessary for the operation of the internal circuit.
[0004]
(2) Communication from PCD to PICC The PCD transmits data to the PICC by modulating the amplitude value of the carrier by 10% ASK (Amplitude Shift Keying) at a data bit rate of 106 Kbps (fc / 128).
[0005]
(3) PICC communication from the PICC to the PCD The PICC generates a subcarrier (fs = 847 KHz) by load-modulating the reception load of the carrier with a frequency 1/16 of the carrier frequency (fs = fc / 16). The subcarrier phase is modulated by BPSK (Binary Phase Shift Keying) at a data bit rate of 106 Kbps (fc / 128) to transmit data to the PCD.
[0006]
FIG. 1 shows an example of the configuration outline of the PICC.
In the example of FIG. 1, two chips constituting the CPU unit 11 and the RF unit 12 are incorporated in the card body 10, and an antenna (AT) 13 wound around the card body 10 in a coil shape. Is arranged. The CPU unit 11 is constituted by a so-called one-chip type computer, which includes a CPU (Central Processing Unit), a memory ROM, a RAM, an EEPROM, an input / output interface (I / O), and the like.
[0007]
FIG. 2 shows a configuration example of a communication interface between the PCD and the PICC.
In the communication from the PCD to the PICC described in the above (2), the signal obtained by modulating the amplitude value of the carrier (fc = 13.56 MHz) by 10% ASK by the modulation unit (MOD) 20 of the PCD is output by the output amplifiers 22 and 23 and the antenna. 24 is transmitted to the PICC.
[0008]
On the other hand, in the communication from the PICC to the PCD described in the above (3), the reception load 26 of the RF signal is varied by the control from the modulation unit (MOD) 28 of the PICC that constitutes a part of the RF unit 12 in FIG. Then, BPSK modulation is performed in which binary phase information (0 degree or 180 degrees) is further given to the subcarrier (fs = 847 KHz) generated by the load modulation (resulting in AM (Amplitude Modulation) modulation).
[0009]
The modulated signal is transmitted to the PCD through the antenna 25 (13 in FIG. 1). In practice, as shown in FIG. 2, the PCD itself detects the carrier modulated by the PCD and subjected to the load modulation (including BPSK modulation) by its detection unit (DET) 21.
[0010]
FIG. 3 shows an example of a conventional demodulator.
The demodulator 30 is placed after the detection unit 21 in FIG. 2 and receives a PSK-modulated subcarrier signal (fs = 847 KHz) and a received signal whose waveform has been shaped into a digital value (binary) by the detection unit 21. Is done. The demodulator 30 first doubles the received signal by a doubler 31 in the first stage in order to regenerate the received subcarrier.
[0011]
Next, by a PLL (Phase lock Loop) circuit comprising a phase comparator 32, a low-pass filter (LPF) 33, and a voltage controlled oscillator (VCO) 34, a double-cycle signal of a double-cycle signal of a subcarrier generated inside the apparatus is obtained. And divide it by a half-divider 35. As a result, a demodulation clock whose phase is synchronized with the reception subcarrier is generated.
[0012]
The received signal is sampled with the rising or falling edge signal of the in-device subcarrier signal, thereby demodulating a BPSK-modulated data signal (data bit rate 106 Kbps) having a 1-bit width of 8 subcarrier periods. The
[0013]
[Problems to be solved by the invention]
FIG. 4 shows an example of the demodulation operation by the sampling.
FIG. 4A shows the case of normal reception, and the 8 subcarriers constituting each 1-bit width of the received PSK signal are each sampled at a correct logic level. On the other hand, (b) of FIG. 4 shows the case where the influence of the external noise is exerted. The level of the received PSK signal fluctuates due to the noise, and as a result, the received signal (comparator output) that has been waveform-shaped incorrectly is sampled. Is done. In this example, an extra waveform crack occurs in the data bit of logic “0”, thereby causing erroneous reception or device malfunction due to the erroneous reception.
[0014]
As described above, the conventional demodulator has a problem that when it is affected by the noise of the space, the demodulated signal is broken in waveform and is low in noise resistance. Further, as apparent from the apparatus configuration of FIG. 4, if a phase delay or the like occurs in the received PSK signal, there is a case where the demodulation by the VCO output fails due to the relationship with the follow-up time of the PLL. There was a problem of outputting. Since this phase lag occurs constantly, a phase compensation circuit is required to compensate for it in a circuit, and there is a problem that various requirements such as reduction in device cost and size reduction cannot be satisfied.
[0015]
In view of the above-described various problems, the object of the present invention is to focus on the fact that the received subcarrier signal is synchronized with the carrier signal output from the PCD side in the case of the PSK signal demodulator in PICC. To provide a carrier synchronous demodulator for a PSK signal that performs sampling using a signal that is synchronized with its own carry signal without using a signal, and detects the sampling start point and determines the majority of the sampling results in order to ensure stable demodulation. It is in.
[0016]
Another object of the present invention is to provide a carrier synchronous demodulator for a PSK signal capable of stably receiving continuous reception data with an indefinite data interval by appropriately executing the sampling start point detection process. is there.
[0017]
Furthermore, an object of the present invention is to provide a carrier synchronous demodulator that satisfies various requirements such as low cost and downsizing applicable to various fields of non-contact type IC cards by eliminating the need for a conventional PLL circuit. It is to provide.
[0018]
[Means for Solving the Problems]
According to the present invention, there is provided a carrier synchronous demodulator for a PSK signal that receives and demodulates a PSK modulated signal of a subcarrier superimposed in synchronization with a transmitted carrier signal, and detects the subcarrier that is continuous for a predetermined period. Subcarrier detection means to perform,
After the detection of the subcarrier, phase change point detection means for detecting the phase change point of the subcarrier, and the detection time of the phase change point is set as a synchronization start point for data reception, and the transmission is started from that time as the starting point. There is provided a carrier synchronous demodulator for a PSK signal composed of data reception control means for controlling reception of data of a predetermined format using a clock inside the apparatus synchronized with a carrier signal.
[0019]
The apparatus further performs a majority decision of logical values “0” and “1” for a plurality of subcarrier sampling values giving a logical value of each received data bit during data reception, and has a large logical value “0” or Majority determination means for determining “1” as the logical value of the received data bit is provided.
[0020]
The majority decision judging means outputs reception error information when the numbers of the logical values “0” and “1” are equal to each other in the majority decision, or the logical values “0” and “1” in the majority decision. A comparison ratio of numbers is obtained, and reception error information is output when the ratio is within a predetermined range.
[0021]
The apparatus further includes a determination unit immediately after the end of reception for determining the start of reception of the next data frame immediately after the end of reception of one data frame having the predetermined format, and when the start of reception of the next data frame cannot be detected. Immediately, the phase change point detection means starts detecting the phase change point of the subcarrier.
[0022]
The data in the predetermined format is asynchronous data, and the determination unit immediately after the end of reception is when the predetermined number of subcarrier sampling values immediately after the stop bit indicating the end of the data frame have the same logical value as the stop bit. It is determined that the reception start of the next data frame cannot be detected.
[0023]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 5 shows the basic configuration of a carrier synchronous demodulator for PSK signals according to the present invention. 6 to 11 show the operation of each major part in FIG.
As described above, this demodulator does not use a conventional PLL circuit. Since the carrier signal frequency (fc = 13.56 MHz) output from the apparatus is generated by the internal clock of the apparatus, the operation by the internal clock of the apparatus is synchronized with the carrier signal. On the other hand, the PICC outputs a subcarrier (fs = fc / 16 = 847 KHz), but the subcarrier is output in synchronization with the carrier signal.
[0024]
Therefore, if even the phase change point of the PSK signal superimposed on the subcarrier, particularly the start bit, can be detected correctly, an accurate sampling point in subsequent data reception is guaranteed. Further, for spatial noise and the like during data reception not related to the signal synchronization, the majority of N (N: integer) PSK signals sampled within 1 bit width is determined to determine whether data is being received. Noise immunity is enhanced. Hereinafter, these operations will be described in detail with reference to examples.
[0025]
Each circuit example described below is for exemplifying the operation of the present invention and a specific circuit scale. In actual circuit construction, a logic design is performed using a programmable device, software for the device, and the like. .
[0026]
In FIG. 5, the PSK synchronization circuit 41 further shapes the PSK signal (see the received signal in FIG. 3) converted to the logic level by the detector 21 into a PSK signal synchronized with the internal clock of the apparatus. FIG. 6A shows an example of the configuration of the PSK synchronization circuit 41, and the received signal is converted into a received signal synchronized with the internal clock by sampling using the two-stage D-type flip-flop circuits 51 and 52. Converted. This compensates for phase fluctuations caused by spatial propagation, the circuit of the detection unit 21, and the like.
[0027]
The subcarrier detection circuit 43 detects whether the PICC is in the RF field and is activated under the control of the state control circuit 47 based on the presence or absence of the subcarrier. The state control circuit 47 recognizes this initial state as the SeekSubCarrier state as shown in (b) and (iii) of FIG. When the subcarrier detection circuit 43 correctly receives the PSK signal from the PICC continuously for a predetermined period (in this example, a period of 150 μsec corresponding to 128 PSK signals), it is determined that carrier synchronization is established with the PICC. Then, the subcarrier detection signal is notified to the state control circuit 47.
[0028]
As a result, the state control circuit 47 makes a transition from the SeekSubCarrier state to the SubCarrierFIND state. The state control circuit 47 may be constituted by a sequential circuit including a general flip-flop circuit or the like, or may be constituted as microprocessor firmware or software.
[0029]
When in the SubCarrier FIND state, the start bit detection circuit 44 starts a start bit detection operation. The start bit detection circuit 44 monitors the change in the phase of the PSK signal in the SubCarrier FIND state, and notifies the state control circuit 47 of the change when the phase change is detected. The state control circuit 47 makes a transition from the SubCarrierFIND state to the NRZStart state by the notification.
[0030]
At the same time, a phase change detection signal (synchronization start point signal) from the start bit detection circuit 44 is supplied to the sampling synchronization signal generation circuit 42. FIG. 7 shows a configuration example of the sampling synchronization signal generation circuit 42. In this example, the counter 61 operated by the internal clock is reset by the synchronization start point signal.
[0031]
As a result, the counter 61 restarts counting from the time when the synchronization start point signal is input, and the bit synchronization signal having a 1-bit width (for example, 8 subcarrier cycles) based on the time when the synchronization start point signal is input by the decoder 62 of the next stage. In addition, a frame synchronization signal from start bit to start bit of start-stop synchronization is generated.
Using the clock from the sampling synchronization signal generation circuit 42, the NRZ signal generation circuit 48 outputs the received PSK signal as NRZ reception data of the predetermined format.
[0032]
FIG. 8 shows an example of a PSK signal reception timing chart when transitioning from the SubCarrierFIND state to the NRZStart state. When the start bit detection circuit 44 detects the first phase change point in the SubCarrierFIND state, the circuit state transitions to the NRZStart state using that as the synchronization start point (iii). As described in FIG. 7A, the frame of the received PSK signal is assembled using a bit synchronization signal, a frame synchronization signal, or the like created based on the synchronization start point.
[0033]
In the present invention, the majority decision judging circuit 45 (FIG. 5) uses the PSK signal sampling included in each 1-bit width for the received PSK signal after the NRZStart state as shown in (iv) and (v) of FIG. A majority vote is determined between the sum of the “0” state and the “1” state of the data. In the example of FIG. 8, first, a majority decision of the start bit composed of 8 PSK signals from the synchronization start point is performed. Since the start bit has the logical value “0”, the Low state count value is “8”. The Hi state count value is “0”.
[0034]
In this case, since “Low state count value> Hi state count value”, the Low state count value side is selected, and the start bit value “0” is output after sampling of the last PSK signal (8th) within 1 bit width. The Thereafter, a similar majority decision process is performed for each subsequent received bit. FIG. 7B shows a simple configuration example of the majority decision circuit 45. The received data is supplied to a counter 63 that counts the sampling value “0” of the PSK signal and a counter 64 that counts the sampling value “1” of the PSK signal, respectively. A “1” value is output.
[0035]
The latch circuit 66 at the final stage performs a latch operation with a bit synchronous clock, and as a result, a majority output of “0” or “1” is obtained in received bit units. In this example, a configuration example in which only two counter values are compared is shown. However, for example, when the number of “0” and “1” states is the same, determination is impossible, and the NRZ signal maintains the previous state. However, a simple decoder circuit or the like may be added to output an error notification signal.
[0036]
Also, instead of simple size comparison, a determination is made based on a predetermined ratio such as “0” if “0”: “1” is greater than or equal to N: M (N, M; integer), “1” otherwise. You may comprise as follows. Instead of the counters 63 and 64, a shift register or the like that shifts by the number of “0” values or “1” values may be used.
[0037]
FIG. 8 also shows an example of how the above-described majority decision circuit 45 functions against noise and the like. In this example, during the reception of the second bit following the start bit, the sampling values of the eight PSK signals that should be “1” values correctly due to external noise are the fourth and seventh signals. The value is “0”. As is apparent from the above description, the majority decision circuit 45 correctly outputs the second bit as “1” from the count value “2” of “0” <the count value “6” of “1”. As described above, in the configuration of the present invention, the noise tolerance is remarkably improved as compared with the conventional one, and the malfunction of the apparatus due to noise or the like is remarkably reduced.
[0038]
FIG. 9 shows an example of reception state transition in the state control circuit 47. FIGS. 10 and 11 show examples of timing charts of the stop bit reception process.
FIG. 9 is mainly shown for explaining the stop bit reception processing of the present invention to be described. Therefore, the transition between the respective states of the SeekSubCarrier state (S71) → SubCarrierFIND state (S72) → NRZStart state (S73) described so far will not be further described.
[0039]
According to the present invention, the determination circuit 46 immediately after the stop bit shown in FIG. 5 starts the next bit value, more precisely, the next bit at the end of reception of the stop bit having the logical value “1” in the NRZStart state (S73). The sampling value of the first PSK signal immediately after the point is determined. If the sampling value is “0”, it is determined that reception of the next frame has started, and the current NRZStart state (S73) is maintained.
[0040]
On the other hand, if the sampling value continues to be “1”, it is determined that there is an indefinite period until the next frame is received, and the state control circuit 47 is notified accordingly. Thereby, the state control circuit 47 shifts the reception state to the SubCarrier FIND state (S72). As a result, the detection operation of the synchronization start point described so far is resumed, and the next frame that arrives after an indefinite period can be immediately synchronized, and the reception operation is started.
[0041]
FIG. 10 shows an example of a reception time chart when the stop bit is 1 bit wide.
As shown in (iv) to (vi) of FIG. 10, after receiving a stop bit having a logical value “1” (Low state count value “0”, Hi state count value “8”), a determination circuit 46 immediately after the stop bit is determined. Determines the start bit, and when the start bit (Low state count value “8”, Hi state count value “0”) of logical value “0” continues as in this example, the circuit state (iii) is in the NRZStart state. Maintained. As a result, continuous frames can be received.
[0042]
On the other hand, FIG. 11 shows an example of a reception time chart when the stop bit is 1 bit wide or more.
In this example, after receiving stop bits (Low state count value “0”, Hi state count value “8”) of logical value “1”, sampling values (Low) of three PSK signals having the same logical value “1” are received. State count value “0”, Hi state count value “8”). In this case, the determination circuit 46 immediately after the stop bit notifies the state control circuit 47 of completion or interruption of frame reception based on the three first sampling results.
[0043]
As shown in the circuit state (iii), the state control circuit 47 immediately transitions the reception state to the SubCarrierFIND state, whereby the start bit detection circuit 44 starts its operation. As a result, when the synchronization start point of the start bit that starts immediately after the sampling values of the three PSK signals is detected, the sampling synchronization signal generation circuit 42 is initialized (reset) as described above, and a new one is newly set. Immediately synchronize to the correct received frame.
[0044]
The state control circuit 47 starts the reception operation by changing the reception state from the SubCarrierFIND state to the NRZStart state. As a result, an accurate reception operation can be performed even when the period between frames to be received is indefinite. In the above embodiment, the reception state is determined based on the sampling value of one PSK signal immediately after reception of the stop bit. However, in consideration of the influence of noise and the like, a plurality of bits are used for the determination. Also good.
[0045]
【The invention's effect】
As described above, according to the present invention, sampling is performed using a signal synchronized with its own carry signal without using a conventional PLL circuit, and further, the influence of noise is avoided and stable demodulation is performed to avoid sampling. Carrier-synchronous type that satisfies various requirements such as enhanced noise resistance, low cost, downsizing, etc. required for application to various fields of non-contact type IC cards to perform majority decision of detection and sampling results A demodulator can be provided.
[0046]
In addition, according to the present invention, it is possible to provide a carrier synchronous demodulator for a PSK signal that can stably receive continuous received data with an indefinite data interval by appropriately executing the sampling start point detection process. .
[Brief description of the drawings]
FIG. 1 shows an example of a configuration outline of a PICC.
FIG. 2 is a diagram illustrating a configuration example of a communication interface between a PCD and a PICC.
FIG. 3 is a diagram illustrating an example of a conventional demodulator.
4 is a diagram showing an example of a demodulation operation by sampling in FIG.
FIG. 5 is a diagram showing a basic configuration of a PSK signal carrier synchronization demodulator according to the present invention.
FIG. 6 shows an example of PSK synchronization / subcarrier detection.
FIG. 7 is a diagram illustrating a configuration example of a sampling synchronization signal generation / majority determination circuit.
FIG. 8 is a diagram showing an example of a start bit detection / majority determination time chart.
FIG. 9 is a diagram illustrating an example of a reception state transition of the state control circuit.
FIG. 10 is a diagram illustrating an example of a data reception time chart in which a stop bit has a 1-bit width.
FIG. 11 is a diagram showing an example of a data reception time chart in which a stop bit has a width of 1 bit or more.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Non-contact IC card 11 ... CPU part 12 ... RF part 13, 24, 25 ... Antenna 20, 28 ... Modulation part 21, 27 ... Detection part 30, 40 ... Demodulator 31 ... Double multiplier 32 ... Phase comparator 33 ... Low-pass filter 34 ... Voltage controlled oscillator 35 ... 1/2 frequency divider 41 ... PSK synchronization circuit 42 ... Sampling synchronization signal generation circuit 43 ... Subcarrier detection circuit 44 ... Start bit detection circuit 45 ... Major decision circuit 46 ... Stop bit Immediately after determination circuit 47... State control circuit 48... NRZ generation circuit 51, 52... D type flip-flop circuit 61, 63, 64.

Claims (10)

A carrier synchronous demodulator for a PSK signal that receives and demodulates a subcarrier PSK modulated signal superimposed in synchronization with a transmitted carrier signal,
Subcarrier detection means for detecting the subcarriers continuous for a predetermined period;
Phase change point detecting means for detecting a phase change point of the subcarrier after the detection of the subcarrier;
Data reception control for controlling reception of data in a predetermined format using a clock in the apparatus synchronized with the transmitted carrier signal as a starting point from the time point of detection of the phase change point as a synchronization start point for data reception And a carrier synchronous demodulator for a PSK signal. Further, during data reception, the majority decision of the logical values “0” and “1” is performed for a plurality of subcarrier sampling values that give the logical value of each received data bit, and a large number of logical values “0” or “1” are determined. 2. An apparatus according to claim 1, further comprising a majority decision judging means for judging that a logical value of the received data bit. 3. The apparatus according to claim 2, wherein the majority decision judging means outputs reception error information when the numbers of the logical values “0” and “1” are equal to each other in the majority decision. The apparatus according to claim 2, wherein the majority decision determination unit obtains a comparison ratio of the numbers of the logical values “0” and “1” in the majority decision and outputs reception error information when the ratio is within a predetermined range. Furthermore, it has a determination unit immediately after the end of reception for determining the start of reception of the next data frame immediately after the end of reception of one data frame having the predetermined format. The apparatus according to claim 1 or 2, wherein the change point detection means starts detecting the phase change point of the subcarrier. The data in the predetermined format is asynchronous data, and the determination unit immediately after the end of reception is when the predetermined number of subcarrier sampling values immediately after the stop bit indicating the end of the data frame have the same logical value as the stop bit. 6. The apparatus according to claim 5, wherein it is determined that the start of receiving the next data frame cannot be detected. The apparatus of claim 5, wherein the predetermined number is one. A carrier synchronous demodulator for a PSK signal that receives and demodulates a subcarrier PSK modulated signal superimposed in synchronization with a transmitted carrier signal,
A PSK synchronization circuit that converts a received PSK signal into a PSK signal synchronized with a clock inside the device that is synchronized with the transmitted carrier signal;
A subcarrier detection circuit for detecting subcarriers continuous for a predetermined period given from the PSK synchronization circuit;
A start bit detection circuit for detecting a phase change point of the subcarrier after the detection of the subcarrier;
A sampling synchronization signal generation circuit that uses the detection time of the phase change point as a synchronization start point for data reception, and generates a reception data sampling clock of a predetermined format using a clock inside the device from that time as a starting point;
An NRZ signal generation circuit that outputs a PSK signal received using a clock from the sampling synchronization signal generation circuit as NRZ reception data of the predetermined format;
The period until the subcarrier detection by the subcarrier detection circuit is the SeekSubCarrier state, the period until the subcarrier phase change point detection by the start bit detection circuit is the SubCarrierFIND state, and the subsequent data reception period is the NRZStart A carrier synchronous demodulator for a PSK signal, comprising: a state control circuit configured to control a transition between the states. Further, in the NRZStart state, a majority decision of logical values “0” and “1” is performed on a plurality of subcarrier sampling values giving logical values of the respective received data bits, and a large number of logical values “0” or “1” are determined. 9. A device according to claim 8, further comprising a majority decision circuit that determines a logical value of the received data bit. Further, the data of the predetermined format is asynchronous data, and has a determination unit immediately after the stop bit for determining the stop bit width of the one data frame, and when the determination is 1 bit width or more, The apparatus according to claim 8 or 9, wherein a control circuit immediately changes the reception state to the SubCarrier FIND state, whereby the start bit detection circuit starts detection of a phase change point of a subcarrier.

Images