KR100383517B1 - Data transmission/reception device of proximity card - Google Patents

Abstract

The present invention relates to a transmission / reception apparatus for a contactless card that satisfies ISO14443 Type B, which is an international standard for proximity contactless cards.

The apparatus for transmitting and receiving data of a non-contact proximity card of the present invention includes a data transmitter, a received data frame detector, a receiver data converter, and a clock generator.

The data transfer unit converts the input byte data into bit data, and serially synchronizes with the transmission clock in addition to the front and rear of the data frame to transmit a signal indicating the start area (SOF) and end area (EOF) of the frame. send. The frame detector detects a valid frame by detecting a start of a frame and an end of a frame of data received from the card. The receiving data converter converts the serially received data frame into byte data in synchronization with the receiving clock and loads the converted byte data onto a data bus or port. The clock generator receives the main clock and generates a clock required by the data transmitter, the received data frame detector, and the received data converter.

Description

Data Transceiver for Contactless Proximity Card {DATA TRANSMISSION / RECEPTION DEVICE OF PROXIMITY CARD}

The present invention relates to a data transmission / reception apparatus for a contactless proximity card, and more particularly, to a transmission / reception apparatus for a contactless card that satisfies ISO14443 Type B, which is an international standard for proximity contactless cards.

According to the international standard ISO14443 Type B, data transmission from the terminal to the card uses a 13.56 MHz carrier to transmit data frames at a data rate of 106 Kbps, and data reception from the card uses a 847 KHz subcarrier to shift the phase. A modulation scheme (PSK) is used to receive 106 Kbps of data.

In order to transmit and receive data satisfying such international standards, conventionally, the functions of the data transmission / reception device have been implemented in software using a microcontroller, or a data transmission / reception device and method are implemented using a custom semiconductor product of a specific company.

However, software-implemented products have advantages in terms of price, but they are difficult to match the data rate of 106Kbps as defined by the ISO14443 standard in time, and have to be completely redeveloped when the development platform changes.

On the other hand, when implementing a data transceiver using a specific company's custom-made semiconductor products, the cost is expensive, there is a problem that can not be analyzed when a problem occurs in the data transmission and reception.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and an object of the present invention is to provide a data transmission / reception apparatus designed in hardware to exchange data with all cards that meet the ISO14443 type B standard. will be.

In addition, an object of the present invention is to provide a data transmitting and receiving device that can be easily analyzed when a problem occurs with low manufacturing cost.

1 is a diagram showing a data frame structure used for a type B card of ISO14443.

2 is a view showing a data transmission and reception apparatus according to an embodiment of the present invention.

3 is a diagram illustrating a clock generator in detail according to an exemplary embodiment of the present invention.

4 is a view showing in detail a data transmission unit according to an embodiment of the present invention.

5 is a diagram illustrating in detail a received data frame detector according to an embodiment of the present invention.

6 is a view showing in detail a received data conversion unit according to an embodiment of the present invention.

7 is a timing diagram of a data transmission unit according to an embodiment of the present invention.

8 is a timing diagram of a reception data frame detector and a reception data converter according to an exemplary embodiment of the present invention.

9 is a flowchart of data transmission according to an embodiment of the present invention.

10 is a flowchart of data reception according to an embodiment of the present invention.

Apparatus for transmitting and receiving data of a proximity card according to a feature of the present invention for achieving the above object

Data that is converted into bit data into bit data, and serially transmitted in synchronization with the transmission clock in addition to the front and rear of the data frame to transmit a signal indicating the start area (SOF) and end area (EOF) of the frame. A transmission unit; A received data frame detector for detecting a valid frame by detecting a start and an end of a frame of data received from the card; A reception data conversion unit for converting serially received data frames into byte data in synchronization with a reception clock and loading the converted byte data on a data bus or a port; And a clock generator which receives a main clock and generates a clock required by the data transmitter, the received data frame detector, and the received data converter.

Here, it is preferable that the transmission clock used by the data transmission unit and the reception clock used by the reception data converter are 106 KHz.

The clock generator

A transmission clock generation unit generating a transmission clock (TX_106KHz) of 106 KHz for use in the data transmission unit in bytes and generating a prohibition signal (INHIBIT) for prohibiting data transmission of the data transmission unit; And a reception clock generator for generating a reception clock (RX_106KHz) of 106 KHz used by the reception data frame detector and the reception data converter.

The data transmission unit

The transmission frame which receives the transmission clock generated by the clock generator and converts the byte data to be transmitted into serial bit data, and adds the start and end of the frame to the converted serial data to generate a data frame to be transmitted. Generation unit; And a byte transfer check unit which generates a byte end signal and stops generation of the transmission clock of the clock generator when the byte of data is ended by checking the transmitted data.

The receiving frame detector

It is preferable to output the frame detection signal DET_SOF_EOF which is at a high level between the end time of the start area of the frame and the end time of the end area of the frame and low level in the remaining areas.

The received data converter

A byte data detector which receives the frame detection signal and the received data and converts a serial received data frame in units of bits into byte data; And a byte ready signal generator for generating a signal DATA_READY indicating completion of conversion of byte data.

On the other hand, the apparatus for transmitting data of a proximity card according to one aspect of the present invention

Converts the input byte data into bit data and transmits serially in synchronization with the transmit clock of 106KHz in addition to the front and rear of the data frame to transmit a signal indicating the start area (SOF) and end area (EOF) of the frame. A data transmission unit; And a transmission clock generation unit configured to receive a main clock and generate a transmission clock TX_106KHz of 106 KHz for use in the data transmission unit by a byte unit, and generate an INHIBIT to prohibit data transmission of the data transmission unit. do.

On the other hand, the apparatus for receiving data of a proximity card according to an aspect of the present invention

A reception data frame detection unit for detecting a valid frame by detecting a start and an end of a frame of data received from the card; A receiving data converter for converting serially received data frames into byte data by synchronizing with a receiving clock of 106 KHz and loading the converted byte data on a data bus or a port; And a reception clock generator for receiving a main clock and generating a clock required by the reception data frame detector and the reception data converter.

Hereinafter, with reference to the drawings will be described an embodiment of the present invention;

First, a data frame structure used for a type B card of ISO14443 will be described with reference to FIG.

As shown in Fig. 1, the data frame structure used for the Type B card of ISO14443 has a start of frame (SOF), a data area (DATA1, DATA2, ..., DATAn) and an end frame (EOF). ; end of frame). The frame start area and the frame end areas SOF and EOF have a value in which 10 bits (or 11 bits) are all zero. Each data area is 10 bits, and each consists of one bit of start bits, eight bits of data bits, and one bit of stop bits. At this time, the value of the start bit is 0 and the value of the stop bit is l.

The data transmission and reception apparatus according to the embodiment of the present invention transmits a bit data frame in synchronization with a transmission clock of 106KHz according to the international standard, and receives received data of 106KHz detected by a phase shift modulation method and synchronizes with an internal clock. Detect.

2 is a view showing a data transmission and reception apparatus according to an embodiment of the present invention.

As shown in FIG. 2, the apparatus for transmitting and receiving data according to the embodiment of the present invention includes a clock generator 100, a data transmitter 200, a received data frame detector 300, and a received data converter 400. do.

The clock generator 100 receives a main clock of 13.56 MHz and supplies clocks of 847 KHz and 106 KHz required by the data transmitter 200, the received data frame detector 300, and the received data converter 400. The data transmission unit 200 is connected to the clock generation unit 100 to convert byte data into bit data, and in addition to the front and rear of the data frame to transmit the signal (SOF, EOF) indicating the start and end of the frame 106Kbps Serial transmission The received data frame detector 300 is connected to the clock generator 100 to detect valid frames (that is, start and end of the frame) from the received data. The reception data conversion unit 400 is connected to the clock generation unit 100 and the reception data frame detection unit 300 to convert serially received data frames into 106 bytes in synchronization with 106 KHz, and convert the converted byte data into a data bus or Put it on the port.

Next, the clock generator 100, the data transmitter 200, the received data frame detector 300, and the received data converter 400 according to the embodiment of the present invention will be described in detail with reference to FIGS. 3 to 8. do.

3, 4, 5, and 6 are diagrams showing details of a clock generator, a data transmitter, a received data frame detector, and a received data converter according to an exemplary embodiment of the present invention. 7 and 8 illustrate timing diagrams of a data transmission unit and timing diagrams of a reception data frame detector and a reception data converter according to an exemplary embodiment of the present invention.

2 and 3, the clock generator 100 receives a clock signal of 13.56 MHz, a byte transfer start signal STARTBYTE *, a byte transfer end signal ENDBYTE, a hardware initialization signal CLEAR *, and a reception signal. The clock TX_106KHz for receiving the data RX_DATA and using it in the data transmission unit 200, the prohibition signal INHIBIT for the data transmission unit 200 to inhibit byte transmission, the reception data detection unit 300, and the reception data The converter 400 generates clocks RX_106KHz and 847KHz for use.

As shown in FIG. 3, the clock generation unit 100 generates a clock signal TX_106KHz for use in the data transmission unit 200 in units of bytes, and generates a prohibition signal INHIBIT. And a reception clock generator 140 for generating reception clocks RX_106KHz and 847KHz for use in the transmission clock generator 120, the reception data detector 300, and the reception data converter 400.

The transmission clock generator 120 receives a clock of 13.56 MHz and generates a clock of 847 KHz, and is connected to the counter C1 to receive a clock of 847 KHz and generates a 106 KHz clock (TX_106 KHz) for transmission. It consists of an OR gate OR1 which receives a counter C2, a STARTBYTE * signal and an ENDBYTE signal, and supplies an output to a clear terminal CRL of the counter C2. As shown in FIG. 7, the microcontroller (not shown) of the card terminal transmits the STARTBYTE * signal, which is an input signal of the OR gate OR1 of the transmission clock generator 120, at a high level to transmit one byte of data. At a low level, a TX_106KHz clock is generated. When one-byte data transfer is completed, ENDBYTE is changed from low level to high level as described later to stop TX_106KHz clock generation. That is, when at least one of the STARTBYTE * signal and the ENDBYTE signal is at a high level, the transmission clock generator 120 generates an INHIBIT signal to stop generation of the transmission clock. It is input to 200.

The reception clock generator 140 includes an OR gate OR2, counters C3 and C4, an inverter IN2, and a flip-flop FF1. The 847 KHz clock generated by the transmission clock generator 120 is input to generate a 106 KHz clock (RX_106 KHz) necessary for detecting received data. In the ISO14443 type B standard, the received data frame is received at a high level for a predetermined time before the frame start signal (SOF). Before the frame is received, the clear signal CLEAR * is set to the low level and the output of the flip-flop FF1 is initialized to the high level, and then the clear signal CLEAR * is set to the high level. The output terminal of the flip-flop FF1 is connected to the input of the OR gate OR2 so that the output of the OR gate OR2 is at a high level. The high level output of the OR gate OR2 is input to the cree terminal CLR of the counter C3 to bring the output of the counter C3 to a low level. If there is no receiving frame, the RX_DATA signal is at a low level, and thus goes high through the inverter IN1. This signal is input to the cree terminal of the counter C4 so that the outputs of the counter C3 are all at the low level. If the received data RX_DATA continues at a high level for more than 8 cycles of 847 kHz, the output of the counter C4 connected to the flip-flop FF1 changes from a low level to a high level and is input to the OR gate OR2. The inverter IN1, the counter C4, and the flip-flop FF1 are used to prevent a malfunction of the counter C3 due to noise in the received data RX_DATA. If the received data signal RX_DATA is at a high level for less than eight periods at a period of 847 KHz, the clock of RX_106 KHz is not generated. When the received data signal RX_DATA is at a high level for at least 8 cycles and then changed to a low level, the counter C3 operates to generate a clock RX_106 KHz necessary for detecting the received data. This clock is input to the reception frame detection unit 300 and used to detect a valid received data frame.

As shown in FIG. 4, the data transmitter 200 includes a transmission frame generator 220 and a byte transmission checker 240.

The transmission frame generator 220 includes flip-flops FF2 and FF3, a parallel-serial shift register RG1, and an AND gate AND1, and is connected to the clock generator 100 to input a clock TX_106KHz for transmission. Convert the byte data (P2 [0 ... 7]) to be received and converted into serial bit data (DATA), and use the serially converted bit data (DATA) and SOFEOF signal to transmit the data frame (TX_DATA). )

Although the data input to the transmission frame generator 220 of the data transmitter 200 is composed of 8 bits, in order to transmit data serially according to the international standard ISO14443 Type B, as shown in FIG. Bit and Stop Bit should be added. As shown in Fig. 4, in the embodiment of the present invention, the H terminal of the register RG1, which is transmitted first, is fixed at a low level (ground) in order to make a start bit (always a value of "0"). Flip-flop FF2 was used to convey data bits and stop bits (which are always values of "1"). In the embodiment of the present invention, since the register RG1 using eight input terminals is used, the eighth data bit is input to the clear terminal CL of the flip-flop FF2, and the output signal of the flip-flop FF2 is input. Is designed to be input to the input terminal (SER) of the register. That is, the input terminal SER of the register RG1 is designed such that the eighth data bit and the stop bit are input together. However, when a register having nine or more input terminals is used, it is possible to design such that eight bits of data bits and stop bits are input to separate input terminals. The inhibit signal INHIBIT signal generated by the transmission clock generator is input to the INH terminal of the register RG1. When the inhibit signal is at a high level as shown in FIG. 7, the operation of the register RG1 is stopped. The flip-flop FF3 is used to synchronize the bit data coming out of the register RG1 in series with a transmission clock of 106 KHz.

The AND gate AND1 of the transmission frame generator 220 transmits the converted data DATA0 synchronized with the transmission clock output from the flip-flop FF3 and the signal SOFEOF indicating the start and end of the frame. The transmission data frame TX_DATA is generated by receiving the input signal.

The byte transfer checker 240 includes a counter C5, an AND gate AND2, and a flip-flop FF4. The byte transfer checker 240 generates a ENDBYTE signal when one byte of data ends by checking the data to be transmitted. Generation of TX_106KHz in 100) is stopped. The AND gate AND2 of the byte transfer checker 240 inputs a high level pulse signal to the clock terminal of the flip-flop FF4 whenever 10 transmission clocks TX_106Khz are input, thereby bringing the ENDBYTE signal to the high level. do. This ENDBYTE signal is input to the OR gate OR1 of the transmission clock generator 120 as shown in FIG.

As shown in Figs. 2 and 5, the reception data frame detection unit 300 is composed of an inverter IN2, a counter C6, an AND gate AND3, and a flip-flop FF5, and a clock signal RX_106KHz for reception. And receive data RX_DATA and initialization signal CLEAR * to detect the received data frame, and maintain a high level DET_SOF_EOF, which is a waveform for checking valid frames while the received data frame is detected.

In FIG. 5, when the low level of the received data becomes 10 bits or more, the output of the AND gate AND3 is changed from the low level to the high level, and the output of the flip-flop FF5 is toggled. That is, the output waveform DET_SOF_EOF of the flip-flop FF5 becomes high level when the start region SOF of the frame ends, as shown in FIG. 8, and becomes low level when the end region EOF of the frame ends. Therefore, the case where the output of the flip-flop FF5 is at a high level is recognized as a valid received data frame.

As shown in FIG. 6, the received data converter 400 includes a byte data detector 420 and a byte ready signal generator 440. As shown in FIG.

The byte data detector 420 includes an AND gate AND4 and AND5, an inverter IN3, a flip-flop FF6, a series-parallel shift register RG2, and a latch L1, and a frame detection signal DET_SOF_EOF. Receives the receive data RX_DATA and converts the serial receive data frame in bit units into byte data.

The byte ready signal generator 440 includes counters C7 and C8, an AND gate AND6, an inverter IN4, and a flip-flop FF7, and generates a signal DATA_READY indicating completion of conversion of byte data. When the byte preparation signal generator 440 generates a DATA_READY signal to notify data preparation, the microcontroller (not shown) of the terminal reads the byte data converted by the byte data detector 420.

Specifically, the register RG2 of the byte data detector 420 stores 8-bit data except for the start bit among the received data and outputs the data to the latch L1. When the received data reaches the ninth bit, the AND gate AND6 of the byte ready signal generator 440 converts the output from the low level to the high level, and the output of the flip-flop FF7 changes from the low level to the high level so that the byte The data ready signal DATA_READY signal is generated and input to the clock terminal CLK of the latch L1 so that 8 bits of data stored in the shift register RG2 are stored in the latch L1. The microcontroller (not shown) checks the DATA_READY signal to indicate that one byte of data has been received at a high level, and therefore reads data from the latch L1 with RCV_EN * at the low level. After reading the data, the microcontroller clears the registers RG2 and flip-flop FF7 with the DATA_CLEAR * signal at the low level.

The inverter IN3 and the flip-flop FF6 of the byte data detector 420 detect the start bit of each data after the SOF to operate the counter C7. When EOF is detected, the output of the AND gate AND5 becomes low level, the low level is also input to the clear terminal CL of the flip-flop FF6, and the output is cleared. This signal is input to the clear stage of the counters C7 and C8 at a high level to clear the output and the operation of the receiver circuit is stopped.

Next, a flow of data transmission and data reception according to an embodiment of the present invention will be described with reference to FIGS. 9 and 10.

First, the flow of data transmission will be described with reference to FIGS. 7 and 9.

As shown in Fig. 7, the microcontroller (not shown) of the terminal makes the SOFEOF signal low level for a specific time to make the start area SOF of the frame. At this time, the time maintained at the low level is determined by the data frame structure of ISO14443 type B shown in FIG.

Then, the microcontroller writes the 1-byte data to be transferred to the port or data bus, generates a LOAD * signal, loads the data into the register RG1, and then (S110) sets the STARTBYTE * signal from high level to low level. The transmission clock generator generates a clock TX_106 KHz for transmission. (S120) Then, the byte data stored in the register RG1 is synchronized with TX_106KHz to come out as serial bit data TX_DATA. (S130)

The microcontroller checks whether the ENDBYTE signal output from the byte transfer checker 240 is at a high level (that is, whether transmission of 1 byte of data has been completed) (S140), and if the ENDBYTE signal is at a high level, STARTBYTE * is set to a low level. To the high level. (S150) Then, the microcontroller checks whether the transmitted one byte of data is the last byte (S160), and if it is not the last byte, returns to the step S110, and if it is the last byte, the SOFEOF signal is brought to a specific low level level. To create the end region (SOF) of the timeframe. (S170)

First, the flow of data reception will be described with reference to FIGS. 8 and 10.

As shown in Fig. 8, the microcontroller of the terminal initializes the hardware for data reception by transmitting a data frame and then setting the CLEAR * signal from high level to low level to high level for data reception. (S200)

Then, the microcontroller checks whether a valid frame has been detected from the valid frame detection waveform DET_SOF_EOF output from the reception data detector. (S210) If no valid frame is detected in step S210, it is determined whether a predetermined time has elapsed (S230). If a predetermined time has elapsed, a reception error process is performed (S235). Return to

When the valid frame is detected in step S210, the microcontroller checks whether the DATA_READY signal output from the reception data conversion unit 400 is high level (S220). In the case of the high level, RCV_EN * is set from high level to low level. After reading one byte of data from the port, set RCV_EN * high. (S240) The microcontroller clears DATA_READY by reading DATA of 1 byte and then setting DATA_CLEAR * to High Level ⇒ Low Level ⇒ High Level. (S250)

Then, the microcontroller determines whether the valid frame has ended (S260), when it is finished, recognizes that the received data frame is over, processes the received data (S270), and returns to step S220 when it is not finished.

As mentioned above, although the Example of this invention was described, this invention is not limited only to the Example mentioned above, A various other deformation | transformation and a change are possible.

For example, the embodiment of the present invention has been described using logic circuits such as or gate, end gate, inverter, counter, flip-flop, register, and latch, but may be implemented through other logic circuits. It can also be implemented by modifying the logic circuit mentioned.

In addition, in the above-described embodiment, the data transmission / reception apparatus may be integrated, but the data transmission apparatus and the data reception apparatus may be separately implemented. In this case, those skilled in the art can easily implement a data transmission device and a data reception device from the above-described embodiment.

As described above, in the present invention, since the data transmission / reception portion is designed in hardware to transmit and receive data with all cards that meet the ISO14443 Type B standard, which is an international standard for a contactless proximity card, there is no problem in adjusting the data rate. It works reliably and can be applied regardless of development platform.

In addition, by developing a transceiver using general components, it is more cost-effective than the product of a specific company and can be easily analyzed when a problem occurs. It can also be applied to custom semiconductor designs to reduce the cost and size of future products.

Claims (25)

Data that is converted into bit data into bit data, and serially transmitted in synchronization with the transmission clock in addition to the front and rear of the data frame to transmit a signal indicating the start area (SOF) and end area (EOF) of the frame. A transmission unit; A reception data frame detection unit for detecting a valid frame by detecting a start and an end of a frame of data received from the card; A reception data conversion unit for converting serially received data frames into byte data in synchronization with a reception clock and loading the converted byte data on a data bus or a port; And And a clock generator configured to receive a main clock and generate a clock required by the data transmitter, the received data frame detector, and the received data converter. The method of claim 1, And a transmission clock used in the data transmission unit and a reception clock used in the reception data conversion unit are 106 KHz. The method of claim 2, The clock generator A transmission clock generation unit generating a transmission clock (TX_106KHz) of 106 KHz for use in the data transmission unit in bytes and generating a prohibition signal (INHIBIT) for prohibiting data transmission of the data transmission unit; And And a reception clock generation unit for generating a reception clock (RX_106 KHz) of 106 KHz used by the reception data frame detection unit and the reception data conversion unit. The method of claim 3, The transmission clock generator A first counter receiving a main clock of 13.56 KHz and generating a clock of 847 KHz; A second counter that receives a clock of 847KHz output from the first counter and generates a transmit clock (TX_106KHz) of 106KHz; The start signal of the byte (STARTBYTE *) and the end signal of the byte (ENDBYTE) are input, and a prohibition signal (INHIBIT) is generated before the start of the byte or after the end of the byte, and the prohibition signal is input to the clear terminal of the second counter. Apparatus for transmitting and receiving data of a proximity card comprising an OR gate. The method of claim 2, The data transmission unit The transmission frame which receives the transmission clock generated by the clock generator and converts the byte data to be transmitted into serial bit data, and adds the start and end of the frame to the converted serial data to generate a data frame to be transmitted. Generation unit; And And a byte transfer check unit for generating a byte end signal to stop generation of the transmission clock of the clock generator when a byte of data ends by checking the transmitted data. The method of claim 5, The transmission frame generation unit A parallel-serial shift register configured to receive a low level start bit, byte data to be transmitted and a high level stop bit in parallel, and convert the serial bits into serial; A flip-flop for synchronizing serial bit data output from the parallel-serial shift register to a transmit clock of 106 KHz; And And an AND gate receiving data synchronized with a 106 KHz transmission clock output from the flip-flop and a signal (SOFEOF) indicating a start region and an end region of a frame and outputting a transmission data frame. The method of claim 5, The byte transfer check unit An end gate for generating a high level pulse signal whenever 10 transmission clocks of 106 KHz are inputted; And And a flip-flop for outputting the byte termination signal by inputting a pulse signal output from the AND gate to a clock terminal. The method of claim 2, The receiving frame detector And a frame detection signal (DET_SOF_EOF) which is at a high level between the end time of the start area of the frame and the end time of the end area of the frame and low level in the remaining areas. The method of claim 8, The receiving frame detector A counter for inputting a receive clock and receive data of 106 KHz to an input terminal and a clear terminal, respectively; An AND gate receiving the output of the counter and outputting a high pulse value when a low level of the received data is 10 bits or more; And a flip-flop that is toggled whenever a high level pulse value is input from the AND gate to output the frame detection signal. The method of claim 8, The received data converter A byte data detector which receives the frame detection signal and the received data and converts a serial received data frame in units of bits into byte data; A data transmitting / receiving device for a proximity card comprising a byte ready signal generator for generating a signal (DATA-READY) indicating conversion of byte data. The method of claim 10, The byte ready signal generation unit A first counter that receives a clock of 847 kHz and outputs a clock of 106 kHz; A second counter that receives the output of the first count and counts the output; A first AND gate receiving the output signal of the second counter and outputting a high level pulse value when the received data reaches the ninth bit; And a first flip-flop for outputting a data preparation signal by inputting the output signal of the AND gate as a clock signal. The method of claim 11, The byte data detection unit A second AND gate configured to receive received data and a frame detection signal; A serial-parallel shift register for storing 8-bit data excluding a start bit among serial output signals output from the second and gate; And And a latch configured to store data stored in the shift register and to transfer the stored data to the microcontroller by controlling the microcontroller. The method of claim 12, The byte data detection unit A third AND gate configured to receive a signal corresponding to an output of the second AND gate and the frame detection signal; And a second flip-flop for receiving the output signal of the third end gate as a clear terminal, the output signal of the second end gate as a clock signal, and the output signal being input to the clear terminal of the shift register. Device for transmitting and receiving data of a proximity card. The method according to any one of claims 1 to 13, The data transmitting / receiving apparatus of the proximity card is used for the ISO14443 type B card. Converts the input byte data into bit data and transmits serially in synchronization with the transmission clock of 106KHz in addition to the front and rear of the data frame to transmit a signal indicating the start area (SOF) and end area (EOF) of the frame. A data transmission unit; And A transmission clock generator for generating a 106KHz transmission clock TX_106KHz for receiving the main clock in bytes and generating a prohibition signal INHIBIT for prohibiting data transmission of the data transmission unit; Data transmission device of proximity card. The method of claim 15, The transmission clock generator A first counter receiving a main clock of 13.56 KHz and generating a clock of 847 KHz; A second counter that receives a clock of 847KHz output from the first counter and generates a transmit clock (TX_106KHz) of 106KHz; The start signal of the byte (STARTBYTE *) and the end signal of the byte (ENDBYTE) are input, and a prohibition signal (INHIBIT) is generated before the start of the byte or after the end of the byte, and the prohibition signal is input to the clear terminal of the second counter. Apparatus for transmitting data of a proximity card comprising an OR gate. The method of claim 15, The data transmission unit The transmission clock receives the transmission clock generated by the transmission clock generation unit, converts the byte data to be transmitted into serial bit data, and adds the beginning and end of the frame to the converted serial data to generate a data frame for transmission. A frame generator; And And a byte transfer check unit which checks the data to be transmitted and generates a byte end signal to stop generation of the transmit clock of the transmit clock generator when one byte of data ends. The method of claim 17, The transmission frame generation unit A parallel-serial shift register configured to receive a low level start bit, byte data to be transmitted and a high level stop bit in parallel, and convert the serial bits into serial; A flip-flop for synchronizing serial bit data output from the parallel-serial shift register to a transmit clock of 106 KHz; And And an AND gate for receiving data synchronized with a transmission clock of 106 KHz output from the flip-flop and a signal (SOFEOF) indicating a start area and an end area of a frame and outputting a transmission data frame. The method of claim 17, The byte transfer check unit An AND gate for generating a high level pulse signal every time 10 transmission clocks of 106 KHz are inputted; And And a flip-flop for outputting the byte termination signal by inputting a pulse signal output from the AND gate to a clock terminal. A reception data frame detection unit for detecting a valid frame by detecting a start and an end of a frame of data received from the card; A receiving data converter for converting serially received data frames into byte data by synchronizing with a receiving clock of 106 KHz and loading the converted byte data on a data bus or a port; And And a receiving clock generator for receiving a main clock and generating a clock required by the receiving data frame detector and the receiving data converter. The method of claim 20, The receiving frame detector And a frame detection signal (DET_SOF_EOF) which is at a high level between the end time of the start area of the frame and the end time of the end area of the frame and low level in the remaining areas. The method of claim 21, The receiving frame detector A counter for inputting a receive clock and receive data of 106 KHz to an input terminal and a clear terminal, respectively; An AND gate receiving the output of the counter and outputting a high pulse value when a low level of the received data is 10 bits or more; And a flip-flop that is toggled whenever a high level pulse value is input from the AND gate to output the frame detection signal. The method of claim 21, The received data converter A byte data detector which receives the frame detection signal and the received data and converts a serial received data frame in units of bits into byte data; And a byte ready signal generator for generating a signal (DATA-READY) indicating completion of conversion of byte data. The method of claim 23, wherein The byte ready signal generation unit A first counter that receives a clock of 847 kHz and outputs a clock of 106 kHz; A second counter that receives the output of the first count and counts the output; A first AND gate receiving the output signal of the second counter and outputting a high level pulse value when the received data reaches the ninth bit; And a first flip-flop for outputting a data preparation signal by inputting the output signal of the AND gate as a clock signal. The method of claim 24, The byte data detection unit A second AND gate configured to receive received data and a frame detection signal; A serial-parallel shift register for storing 8-bit data excluding a start bit among serial output signals output from the second and gate; And And a latch for storing data stored in the shift register and transferring the stored data to the microcontroller by controlling the microcontroller.