JPH05236031A - Data transmission system - Google Patents

Data transmission system

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Publication number
JPH05236031A
JPH05236031A JP32150391A JP32150391A JPH05236031A JP H05236031 A JPH05236031 A JP H05236031A JP 32150391 A JP32150391 A JP 32150391A JP 32150391 A JP32150391 A JP 32150391A JP H05236031 A JPH05236031 A JP H05236031A
Authority
JP
Japan
Prior art keywords
circuit
carrier signal
data
digital data
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP32150391A
Other languages
Japanese (ja)
Inventor
Toshiatsu Iegi
Yosuke Katayama
Kazuo Takasugi
Takashi Takeuchi
俊温 家木
洋介 片山
隆 竹内
和夫 高杉
Original Assignee
Hitachi Maxell Ltd
N T T Data Tsushin Kk
エヌ・ティ・ティ・データ通信株式会社
日立マクセル株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP3-205702 priority Critical
Priority to JP20570291 priority
Application filed by Hitachi Maxell Ltd, N T T Data Tsushin Kk, エヌ・ティ・ティ・データ通信株式会社, 日立マクセル株式会社 filed Critical Hitachi Maxell Ltd
Publication of JPH05236031A publication Critical patent/JPH05236031A/en
Priority claimed from US08/325,643 external-priority patent/US5418353A/en
Withdrawn legal-status Critical Current

Links

Abstract

(57) [Summary] [Object] To enable a data demodulation circuit to have a simple circuit configuration suitable for integration into an IC. [Structure] "1" of digital data (FIG. 1A),
At the boundary of the "0" bit, the time width of the 1/2 cycle of the carrier signal is twice the time width T of the 1/2 cycle before modulation, that is, 2T (FIG. 1B). In the case of demodulating digital data from such a carrier signal, first, the carrier signal is waveform-shaped (FIG. 1 (c)), and a 1/2 cycle having a time width of 2T is detected to detect an edge pulse (see FIG. d)) is formed, and the data whose level is inverted by this edge pulse is created (FIG. 1 (e)). This data is the carrier signal (Fig. 1
It is digital data demodulated from (b)).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transmission system suitable for use in a system using a non-contact type information medium such as a non-contact type IC card.

[0002]

2. Description of the Related Art When data is transmitted wirelessly between a transmitter and a receiver, a high frequency carrier signal is used, and this carrier signal is modulated by digital data and transmitted. Even in an IC card system using a non-contact type IC card, which has been receiving attention in recent years, a coil provided in the non-contact type IC card and a reader / writer are magnetically coupled to each other so that a data transmission path therebetween is formed. The data transmission between them is also performed by modulating a carrier signal with digital data.

An example of an IC card system using a non-contact type IC card will be described below with reference to FIG. However, in the figure, 1 is an external interface, 2 is a reader / writer, 3 is a contactless IC card, 4 is a data processing circuit,
5 is a modulation circuit, 6 is a drive circuit, 7 is a coupling coil, 8
Is a receiving circuit, 9 is a clock generating circuit, 10 is a coupling coil, 11 is a rectifying circuit, 12 is a power circuit, 13 is a transmitting circuit, 14 is a receiving circuit, 15 is a clock generating circuit, 16 is a data processing circuit, and 17 is reset. The generation circuit, 18 is a memory.

When data is sent from the reader / writer 2 to a non-contact type IC card (hereinafter, simply referred to as an IC card) 3, the data is supplied to the reader / writer 2 from a host (not shown) or the like via an external interface 1. To be done. In the reader / writer 2, this data is processed by the data processing circuit 4 which operates with the clock from the clock generation circuit 9, and then supplied to the modulation circuit 5 to be supplied to the clock generation circuit 9
The high-frequency clock signal from is modulated as a carrier signal. The modulated carrier signal (hereinafter referred to as the modulated carrier signal) is supplied to the coupling coil 7 via the drive circuit 6.

At this time, the IC card 3 is the reader / writer 2
Is attached to the reader / writer 2 and the coupling coil 7 and I
The coupling coil 10 of the C card 3 is magnetically coupled.

Therefore, the IC card 3 is supplied with the modulated carrier signal via the coupling coils 7 and 10. This modulated carrier signal is rectified by the rectifier circuit 11 and supplied to the power supply circuit 12 to generate a power supply voltage required for each part of the IC card 3. Further, the output signal of the rectifying circuit 11 is supplied to the receiving circuit 14 and the clock generating circuit 15, where the data is demodulated and the clock is generated. The demodulated data is processed by the data processing circuit 16 which operates by the clock from the clock generation circuit 15 and the reset signal from the reset generation circuit 17, and then written in the memory 18.

When data is sent from the IC card 3 to the reader / writer 2, an unmodulated carrier signal is output from the modulation circuit 5 in the reader / writer 2, and the IC is passed through the drive circuit 6 and the coupling coils 7 and 10. It is supplied to the card 3. In the IC card 3, similarly to the above, this carrier signal is rectified by the rectifier circuit 11 and supplied to the power supply circuit 12 to generate a predetermined power supply voltage. Further, the clock generation circuit 15 generates a clock from the output signal of the rectification circuit 11. As a result, the data processing circuit 16 operates.

On the other hand, the data read from the memory 18 is supplied to the transmission circuit 13 after being processed by the data processing circuit 16 such as a CPU. The transmission circuit 13 is composed of, for example, a load resistor and a switch, and this switch turns on and off according to "1" and "0" bits of data.

In the reader / writer 2, the transmission circuit 13
When the switch is turned on and off, the load seen from both terminals of the coupling coil 7 on the coupling coil 7 side varies, and the amplitude of the carrier current flowing through the coupling coil 7 varies accordingly. That is, this carrier current is amplitude-modulated by the data supplied to the transmission circuit 13. This amplitude-modulated carrier current is detected by the receiving circuit 8 and data is demodulated. This data is processed by the data processing circuit 4 and then sent from the external interface 1 to the host or the like.

[0010]

In the IC card system as described above, since the power supply voltage is generated from the carrier signal sent from the reader / writer 2 in the IC card 3, in order to obtain a stable power supply voltage. Has
It is preferable that the carrier signal has a constant amplitude.
Therefore, when data is sent from the reader / writer 2 to the IC card 3, if the modulation method of the modulation circuit 5 is a modulation method such as a frequency modulation method or a phase modulation method that keeps the amplitude of the carrier signal constant, in such data transmission, The amplitude of the carrier signal supplied to the IC card 3 can be made constant.

By the way, in order to demodulate a carrier signal frequency-modulated or phase-modulated by digital data in this way, a PLL (Phase Locked Loop) is generally used conventionally. In the case of a frequency-modulated carrier signal, demodulated digital data is obtained from the PLL low-pass filter, and in the case of a phase-modulated carrier signal, the oscillation frequency of the oscillation circuit is set to twice the carrier frequency and 2 Demodulated digital data is obtained from the phase comparison circuit of the divided signal and the carrier signal.

However, when such a PLL is incorporated into a non-contact type IC card to be integrated into an IC, the IC circuit becomes large and expensive due to its low-pass filter, which is not preferable.

An object of the present invention is to solve the above problems and provide a data transmission system capable of demodulating digital data from a modulated carrier signal by a simple and inexpensive means.

[0014]

In order to achieve the above object, the present invention widens the period of a carrier signal at the boundary between "1" and "0" bits of digital data as compared with the case of no modulation.

[0015]

When the cycle of the carrier signal is judged and the cycle is longer than other periods, "1" of digital data,
Judge as the boundary of "0" bits. As a means for determining such a cycle, the cycle is longer than the cycle when the carrier signal is not modulated,
A circuit having a simple structure such as a retrigger multivibrator having a time constant shorter than the expanded period can be used.

[0016]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is an explanatory diagram showing an embodiment of a data transmission system according to the present invention. When this embodiment is applied to the IC card system shown in FIG. 13, the digital data shown in FIG. 1A output from the data processing circuit 4 will be compared with the digital data shown in FIG. The modulated carrier signal shown in is output. This modulated carrier signal is
Assuming that the half cycle before modulation is T, it is 1/2 at the boundary between the "1" and "0" bits of the digital data (Fig. 1 (a)).
The period is expanded to twice the half period before modulation, that is, 2T. Here, 1 from the boundary of digital data
The 1/2 cycle of the cycle is expanded to 2T. Except for this part of the modulated carrier signal, 1/2 period is kept at the length T before modulation.

FIG. 2 shows a specific example of the modulation circuit 5 that performs such modulation. However, 19 is a frequency-dividing circuit, 20 is a selector, and parts corresponding to those in FIG.

In the figure, a clock having a constant 1/2 cycle T output from the clock generation circuit 9 is a selector 2
While being supplied to 0, the frequency is divided by the divide-by-2 circuit 19 to become a clock having a 1/2 cycle of 2T, which is supplied to the selector 20. On the other hand, from the data processing circuit 4, FIG.
2 of the clock output from the clock generation circuit 9 at each boundary of "1" and "0" bits of the digital data shown in
A select signal having a width of cycle 4T is output. Selector 2
Although 0 normally selects the clock from the clock generation circuit 9, when the select signal is supplied from the data processing circuit 4, the output clock of the signal period divide-by-2 circuit 19 is selected. As a result, the modulated carrier signal shown in FIG. 1A is obtained from the selector 20.

The modulated carrier signal is supplied to the non-contact type IC card 3 via the drive circuit 6 and the coupling coils 7 and 10 in FIG. Non-contact type IC card 3
Then, after being rectified by the rectifying circuit 11, it is supplied to the receiving circuit 14 and demodulated into digital data. This demodulating operation will be described with reference to FIG.

The modulated carrier signal shown in FIG. 1 (b) is rectified by the rectifier circuit 11 and supplied to the receiver circuit 14.
This modulated carrier signal is waveform shaped. This waveform-shaped modulated carrier signal is shown in FIG. 1C, but here, in order to show a simple waveform, the waveform in FIG. 1B is shown as being directly waveform-shaped.

Next, the time length of each 1/2 cycle of the modulated carrier signal shown in FIG. 1 (c) is detected, and the 1/2 cycle is 2
At the time of T, as shown in FIG. 1D, a pulse (hereinafter referred to as an edge pulse) is generated. Here, since the 1/2 carrier period of 2T continues twice in the modulated carrier signal, the edge pulse is generated twice in succession. And the edge pulse is 2
When it occurs consecutively, the data whose level is inverted is formed as shown in FIG. This data is demodulated from the modulated carrier signal (FIG. 1 (b)) to be digital data.

FIG. 3 shows a specific example of a demodulation circuit that performs the above demodulation operation. However, 21 is a waveform shaping circuit, 22 is a retrigger multivibrator, and 23 is a data forming circuit.

Referring to FIG. 1, the waveform shaping circuit 21 shown in FIG.
The modulated carrier signal shown in (c) is formed. The retrigger multivibrator 22 has a time constant TM of T <TM <2.
It is set to T and triggered on each edge of the modulated carrier signal shown in FIG. Since the retrigger multivibrator 22 has the time constant TM described above,
The edge pulse shown in (d) is output. The time interval between two edge pulses that are successively generated is 2T.

The data forming circuit 23 forms the data whose level is inverted when the edge pulse is supplied at intervals of 2T. Examples of the data forming circuit 23 include a delay circuit that delays an edge pulse by 2T, an AND gate that generates a trigger pulse when the input edge pulse and the edge pulse delayed by the delay circuit match, and this trigger. And a pulse-triggered T-type flip-flop circuit.

As described above, the PLL is used as the demodulation circuit.
It is possible to use a circuit having a simple circuit configuration suitable for IC without using. The same applies to the modulation circuit.

When digital data is transmitted as a carrier signal as shown in FIG. 1B, a predetermined bit of "0" or "1" is transmitted as an initial bit, and the data is transmitted. The forming circuit 23 sets the initial state according to the initial bit. As a result, the digital data is always demodulated correctly.

In the above embodiment, the time width for one cycle of the carrier signal is doubled at the boundary between "1" and "0" of the digital data, but as shown in FIG. The time width may be extended. However, FIG.
The signals of (a), (b), (c), (d) and (e) are shown in FIG.
These correspond to the signals (a), (b), (c), (d), and (e), respectively. In this case, as the modulation circuit, the basic configuration is the same as that of FIG. 2, but an inverting circuit is used instead of the divide-by-2 circuit 19, and the select signal output from the data processing circuit 4 is a clock generation circuit. 1 cycle 2 of the clock from 9
The pulse width is equal to T.

Demodulation of such a modulated carrier signal is performed in the same manner as in the embodiment shown in FIG. 1, but the edge pulse is shown in FIG.
As shown in (d), it occurs once. For this reason, when the demodulation circuit as shown in FIG. 3 is used, a T-type flip-flop circuit can be used as the data forming circuit 23, and as a result, as shown in FIG. Is obtained.

As described above, also in this embodiment, the same effect as that of the embodiment shown in FIG. 1 can be obtained.

FIG. 5 is an explanatory view showing still another embodiment capable of facilitating the data demodulation of the data transmission system according to the present invention. In this embodiment, digital data "1",
The modulated carrier signal is held at a constant level for a predetermined period at the boundary of the "0" bit, and this level is changed when the "0" bit shifts to the "1" bit and when the "1" bit shifts to the "0" bit. It is different. In FIG. 5, the modulated carrier signal is digital data “0”.
The bit and the "1" bit are phase-modulated so that the phases are different by 180 °, and the predetermined period in which the level is held constant is 2T ', where T'is the period of the modulated carrier signal. As the level shifts from “0” bit to “1” bit, “L” (low level),
On the contrary, it is set to "H" (high level) when shifting from "1" bit to "0" bit.

Also in such a modulated carrier signal, "L" is generated at the boundary between "0" and "1" bits of digital data.
Alternatively, in the period of "H", the period of the normal portion is T ', while it is expanded to 2T'.

On the side that receives the digital data, the digital data can be demodulated by detecting the level during the period of 2T 'in which the level is constant. In this embodiment, since the "0" and "1" bits can be discriminated by the level of such a time length period of 2T ', the phase modulation of the modulated carrier signal is not used. If the data is phase-modulated, the receiving section using the phase demodulation circuit can demodulate the digital data.

FIG. 6 is a block diagram showing a concrete example of a modulation circuit for generating such a modulation carrier.
Is a D-FF (D-type flip-flop circuit, 27 to 29 are inverters, 30 and 31 are AND gates, 32 is an OR circuit, 33 is an EX-OR exclusive OR circuit, 34 is an AND gate, and 35 is a D-FF). Therefore, the parts corresponding to those in FIG. 13 are designated by the same reference numerals.

FIG. 7 shows the signals of the respective parts of FIG. 6, and the signals corresponding to those of FIG. 6 are designated by the same reference numerals.

This concrete example is the modulation circuit 5 of FIG. 13, and in FIG. 6, the data processing circuit 4 (FIG. 1) is used.
The digital data DATA from 3) becomes the D input of the D-FF 24 and is latched at the rising edge of the clock φ of the period T'from the clock generation circuit 9 (FIG. 13). Therefore, as shown in FIG. 7, the D-FF 24 obtains the digital data DATA 'which is in phase with the clock φ.

Digital data DA from the D-FF 24
TA 'is latched in the D-FF 25 at the rising edge of the clock φ. As a result, this D-FF25
From the clock φ rather than the digital data DATA '
The digital data delayed by one cycle is output. This digital data is supplied to the EX-OR circuit 33 together with the digital data DATA '. This allows EX
From the -OR circuit 33, an "L" edge pulse EG having one cycle length of the clock φ is obtained for each edge of the digital data DATA '.

On the other hand, the digital data DATA 'output from the D-FF 24 is supplied to the AND gate 30, and also inverted by the inverter 28 and supplied to the AND gate 31. The clock φ is also supplied to the AND gate 31 and also inverted by the inverter 29 and supplied to the AND gate 30. Therefore, in the AND gate 30, the digital data 30 is sampled with the clock φ (−) inversion of the clock φ, and in the AND gate 31, the inverted data of the digital data 30 is sampled with the clock φ. The outputs of the AND gates 30 and 31 are added by the OR circuit 32.

If the "H" period of the digital data DATA 'is "0" bit and the "L" period is "1" bit, the AND gate 30 outputs the digital data DAT.
The "0" bit of A'is sampled by the inverted clock φ (-), and the AND gate 31 sets the digital data to "1".
This means that the bits are sampled with the clock φ. Therefore, the OR circuit 32 outputs the digital data DAT.
The phase is 180 ° between the "0" bit and the "1" bit of A '.
Different modulated signals are obtained. The point of time when this phase is inverted is the boundary between the "0" and "1" bits of the digital data DATA '. Therefore, the output signal of the OR circuit 32 is a so-called PSK (phase shift keying) signal.

The clock 2φ having a frequency twice that of the clock φ is also supplied from the clock generation circuit 9 (FIG. 13).
The rising edge of the clock 2φ is synchronized with the falling edge of the clock φ and is inverted by the inverter 27.
Inverted clock 2φ (−) output from the inverter 27
Are supplied to the AND gate 34 together with the edge pulse EG from the EX-OR circuit 33.
The inverted clock 2φ (−) in the pulse period of 1 is excluded.

The D-FF 35 is the PSK from the OR circuit 32.
Clock 2 from AND gate 34 with signal as D input
Sample and hold at the rising edge of φ (-) '. As a result, the modulated carrier signal M-PSK described in FIG. 5 is obtained from the Q terminal of the D-FF 35.

An inverted signal of the modulation carrier signal M-PSK signal is output from the Q (-) terminal of the D-FF 35, and this and the modulation carrier signal M-PSK are supplied to the driver 6. In the driver 6, these signals turn on and off different switches, whereby the current of the modulated carrier signal M-PSK flows in the coil 7.

Next, demodulation of the modulated carrier signal shown in FIG. 5 will be described. FIG. 8 is a diagram showing a part of a concrete example of the demodulation circuit, in which 36 and 37 are delay circuits and 38 and 39.
Is an AND gate.

In this figure, it is assumed here that two circuits consisting of a delay circuit and an AND gate are connected in series. The modulated carrier signal A shown in FIG. 5 is supplied to the AND gate 38, delayed by tD in the delay circuit 36, and supplied to the AND gate 38. In the case of the circuit configuration shown in the figure, the delay circuit tD is set to 0 <tD <T '/ 2. Therefore, the AND gate 38 obtains the signal B in which the rising edge is delayed from the modulated carrier signal A by tD and the falling edge is the same as the modulated carrier signal A. In this signal B, each “H” period is shorter than the modulated carrier signal by τD.

The output signal B of the AND gate 38 is supplied to the AND gate 39, and the delay circuit 37 outputs tD '.
Is supplied to the AND gate 39 delayed by only. The delay amount tD 'of the delay circuit 37 is set to T' / 2-tD <tD '<T' / 2 + tD. According to this, the "H" portion of the output signal B of the AND gate 38 having a time width of (T '/ 2-? D) or less is excluded.

Therefore, as shown in FIG. 9A,
Looking at the portion of the modulated carrier signal A which becomes "H" for the time τT '(the portion where the digital data changes from "1" bit to "0" bit), the output signal of the delay circuit 36 is shown in FIG. 9 (b). Therefore, the output signal B of the AND gate 38 becomes as shown in FIG. 9 (c).
Therefore, the output signal of the delay circuit 37 becomes as shown in FIG. 9D, and as a result, the AND gate 39 outputs the signal shown in FIG.
As shown in (e), a signal of 2T '"H" period is obtained. That is, the output signal of the AND gate 39 represents the timing when the digital data of the modulated carrier signal A shifts from "1" bit to "0" bit.

No signal can be obtained by the means shown in FIG. 8 during the 2T '"L" period when the digital data changes from the "0" bit to the "1" bit. In order to make this possible, it suffices to provide means having the same configuration as in FIG. 8 and invert the modulated carrier signal as the input thereof. The original digital data is obtained by resetting the flip-flop circuit by the output signal of such means and setting this flip-flop circuit at the output signal of FIG.

Now, assuming that a circuit consisting of a delay circuit and an AND gate as shown in FIG. 8 is connected in cascade in n stages and the total delay amount of these delay circuits is TD, "1" and "0" of the modulated carrier signal are obtained. If "T '/ 2 <TD <2T' is satisfied in order to remove the" bit portion (T '/ 2 period portion) and to always leave the 2T' period portion at the boundary between "1" and "0" bits. Good. Therefore, when trying to set the total delay amount TD to the period T'of the modulated carrier signal, the variation is allowed within the range of -50% to + 100%.

When the boundary between "1" and "0" bits is the time width of T ', T' / 2 <TD <T ', and TD = 2/3 × T'. Is allowed between -25% and + 50%, but the allowable range is narrower than when the time width is 2T '. Generally, "1",
The larger the time width of the signal at the boundary of "0" bits, the larger the allowable range of the variation of the total delay amount TD.
In this case, since the phases of the modulation parts at the "1" and "0" bits must be different by 180 °, "1",
The time width of the signal at the boundary of "0" bits must be an integral multiple of the period T'of the modulated carrier signal.

On the other hand, when the time width of the signal at the boundary between the "1" and "0" bits is set to be large, this signal has a constant level, so that the DC component exists for a long period in this portion of the modulated carrier signal. It will be. Therefore, when such a modulated carrier signal is transmitted between the reader / writer and the IC card, this direct current component is not transmitted because it is transmitted via the coil, and the central level of the modulated carrier signal fluctuates greatly in that portion, causing distortion. Occurs. For this reason, "1", "0"
The time width of the signal at the bit boundary cannot be made too long, and it is suitable to set it to 2T 'in view of the allowable range of the variation of the total delay amount TD.

FIG. 10 is a block diagram showing another concrete example of the demodulation means for the modulated carrier signal shown in FIG.
˜43 are delay circuits, 44 and 45 are AND gates, and 46 is SR-FF (set / reset type flip-flop circuit).

The specific example shown in FIG. 8 is provided for each "H" and "L" signal at the boundary between "1" and "0" bits, but the specific example shown in FIG. The circuit is shared so that these "H" and "L" signals can be detected. Although four delay circuits are used here, any number may be used as long as it is two or more.

The modulated carrier signal A shown in FIG. 5 is directly supplied to the AND gate 44, and also inverted to the AND gate 4.
5 and the delay circuits 40 to 43 sequentially delay the time tD. These delay circuits 40 to 43
Output signal is directly supplied to the AND gate 44, and
Each is inverted and supplied to the AND gate 45.

By appropriately setting the delay amount tD of the delay circuits 40 to 43, in the same manner as the specific example shown in FIG.
The AND gate 44 detects the "H" signal at the boundary between the "1" and "0" bits in the modulated carrier signal A, and the AND gate 45 similarly detects the "L" signal. The SR-FF 46 is set by the output signal of the AND gate 44 and reset by the output signal of the AND gate 45. As a result, digital data demodulated from the modulated carrier signal A is output from the Q terminal of the SR-FF46.

Note that the delay amounts of the delay circuits 40 to 43 may be different from each other, and each of them may be connected to the AND gate 4.
It may be set so that a signal at the boundary between "1" and "0" of the modulated carrier signal can be obtained from 4, 45. In any case, the allowable range of variations in the total delay amount of the delay circuits 40 to 43 is as described above.

FIG. 11 is a block diagram showing still another embodiment of the demodulation means for the modulated carrier signal shown in FIG.
47 and 48 are current sources, 49 is a capacitor, 50 is an amplifier, and 51 is an LPF.

In the figure, the current source 47 is turned on during the modulated carrier signal "H" period, and the current source 48 is turned on during the "L" period. During the “H” period of the modulation carrier A, the charging current flows from the current source 47 to the capacitor 49 to increase the charging voltage, and during the “H” period of the modulation carrier A, the discharging current flows from the capacitor 49 to the current source 48. The charging voltage becomes low.

Then, when the modulated carrier signal A shown in FIG. 12 (a) is input, as shown in FIG. 12 (b),
In the period of T'cycle of "1" and "0" bits, T '/ 2
Since the capacitor 49 is alternately charged and discharged for each period, the charging voltage of the capacitor 49 changes in the cycle of this T '/ 2 period, but the "H" level at the boundary from "1" bit to "0" bit is changed. In the 2T 'period, the charging voltage of the capacitor 49 rises significantly, and in the "L"2T' period at the boundary where the "0" bit shifts to the "1" bit, the capacitor 4 is charged.
The charging voltage of 9 drops sharply. Therefore, the capacitor 4
After amplifying the charging voltage of 9 with the amplifier 50, the LPF 51
12 to remove the high frequency component,
As shown in (c), the original digital data having "L" at "1" bit and "H" at "0" bit is obtained.

As described above, even for the modulated carrier signal shown in FIG. 5, a circuit having a simple and suitable circuit configuration can be used without using a PLL.

In the embodiment shown in FIG. 5, the modulated carrier signal is PSK-modulated with different phases by "1" and "0" bits, but in this embodiment, these "1" s are used. , "0" and "1" bits can be discriminated by the level of the signal at the boundary of "0" bits.
There is no need to use K modulation. However, in this case, since the phase of the modulated carrier signal is constant, "1", "0"
The time width of the signal at the bit boundary is NT '+ T' / 2 (where N = 1, 2, 3 ...). Also in this case, the digital data can be demodulated by the means shown in FIGS. 8, 10 and 11, and as described above, the allowable range of variation in the total delay amount of the delay circuits in FIGS. Considering the distortion of the modulated carrier signal to be transmitted, it is appropriate to set the time width of the signal at the boundary between "1" and "0" bits to 3T '/ 2 (N = 1).

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments. For example, although the above embodiment is applied to the IC card system, it goes without saying that the present invention is also applicable to systems other than the IC card system. Further, the extension time width of 1/2 cycle of the carrier signal is twice as wide as before the modulation, but the invention is not limited to this.

In the above embodiment, the card-type non-contact type information medium has been described as an example, but the present invention is also applicable to a pendant-type or coin-type information medium.

[0062]

As described above, according to the present invention,
The demodulation circuit can have a simple circuit configuration suitable for being integrated into an IC.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of a data transmission system according to the present invention.

FIG. 2 is a block diagram showing a specific example of a modulation circuit for the embodiment shown in FIG.

FIG. 3 is a block diagram showing a specific example of a demodulation circuit for the embodiment shown in FIG.

FIG. 4 is an explanatory diagram showing another embodiment of the data transmission system according to the present invention.

FIG. 5 is an explanatory diagram showing another embodiment of the data transmission system according to the present invention.

FIG. 6 is a block diagram showing a specific example of a modulation circuit for the embodiment shown in FIG.

FIG. 7 is a waveform diagram showing signals of respective parts in FIG.

8 is a block diagram showing a specific example of a demodulation circuit for the embodiment shown in FIG.

9 is a timing chart showing the operation of the specific example shown in FIG.

10 is a block diagram showing another specific example of the demodulation circuit for the embodiment shown in FIG.

11 is a block diagram showing still another specific example of the demodulation circuit for the embodiment shown in FIG.

FIG. 12 is a waveform diagram showing signals of respective parts of FIG.

FIG. 13 is a block diagram showing an example of an IC card system using a non-contact type IC card.

[Explanation of symbols]

 2 reader / writer 3 non-contact type IC card 5 modulation circuit 7, 10 coupling coil 14 receiving circuit T half cycle time width of carrier signal before demodulation T ′ one cycle time width of carrier signal before demodulation

Front page continuation (72) Inventor Takashi Takeuchi 1-26-5 Toranomon, Minato-ku, Tokyo NTT Data Communications Corp. (72) Inventor Toshion Ieki 1-26 Toranomon, Minato-ku, Tokyo No. 5 NTT DATA Communications Corporation

Claims (1)

[Claims]
1. A carrier signal is modulated and transmitted by digital data consisting of "1" and "0" bits, wherein the carrier signal is "1",
A data transmission method characterized in that modulation is performed at a boundary of "0" bits, and a cycle at the boundary is made longer than a cycle at other portions.
JP32150391A 1991-07-23 1991-11-11 Data transmission system Withdrawn JPH05236031A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP3-205702 1991-07-23
JP20570291 1991-07-23

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/325,643 US5418353A (en) 1991-07-23 1994-10-19 Non-contact, electromagnetically coupled transmission and receiving system for IC cards

Publications (1)

Publication Number Publication Date
JPH05236031A true JPH05236031A (en) 1993-09-10

Family

ID=16511294

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US9407311B2 (en) 2011-10-21 2016-08-02 Keyssa, Inc. Contactless signal splicing using an extremely high frequency (EHF) communication link
US9647715B2 (en) 2011-10-21 2017-05-09 Keyssa, Inc. Contactless signal splicing using an extremely high frequency (EHF) communication link
US9197011B2 (en) 2011-12-14 2015-11-24 Keyssa, Inc. Connectors providing haptic feedback
US9203597B2 (en) 2012-03-02 2015-12-01 Keyssa, Inc. Systems and methods for duplex communication
US10069183B2 (en) 2012-08-10 2018-09-04 Keyssa, Inc. Dielectric coupling systems for EHF communications
US9515365B2 (en) 2012-08-10 2016-12-06 Keyssa, Inc. Dielectric coupling systems for EHF communications
US9515707B2 (en) 2012-09-14 2016-12-06 Keyssa, Inc. Wireless connections with virtual hysteresis
US10027382B2 (en) 2012-09-14 2018-07-17 Keyssa, Inc. Wireless connections with virtual hysteresis
US9374154B2 (en) 2012-09-14 2016-06-21 Keyssa, Inc. Wireless connections with virtual hysteresis
US10033439B2 (en) 2012-12-17 2018-07-24 Keyssa, Inc. Modular electronics
US9531425B2 (en) 2012-12-17 2016-12-27 Keyssa, Inc. Modular electronics
US10523278B2 (en) 2012-12-17 2019-12-31 Keyssa, Inc. Modular electronics
US9960792B2 (en) 2013-03-15 2018-05-01 Keyssa, Inc. Extremely high frequency communication chip
US9553616B2 (en) 2013-03-15 2017-01-24 Keyssa, Inc. Extremely high frequency communication chip
US9426660B2 (en) 2013-03-15 2016-08-23 Keyssa, Inc. EHF secure communication device
US9894524B2 (en) 2013-03-15 2018-02-13 Keyssa, Inc. EHF secure communication device
US10602363B2 (en) 2013-03-15 2020-03-24 Keyssa, Inc. EHF secure communication device

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