JP2001103110A - Psk demodulator, psk demodulation method and recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PSK demodulator and a PSK demodulation method to accurately demodulate a high-speed PSK modulation signal without the need for using an analog filter. SOLUTION: A sampling unit 5 applies binary processing to a QPSK modulation signal that is amplified and frequency-converted and the resulting signal is fed to a delay device 7 and a detector 8. The delay device 7 delays the modulation signal received by itself by 1 symbol and gives the delayed signal to the detector 8. The detector a generates a detection signal denoting a time difference between a leasing of a signal fed from the sampling unit 5 and a leading of a signal fed from the delay device 7. A shift register 9 latches a logical value denoted by the detection signal in prescribed timing, a 4-value converter 11 converts the logic value latched by the shift register 9 into 2-bit data according to a prescribed rule and restores the data to the original data subjected to QPSK modulation. A local oscillator 4 and/or a sampling signal generator may be controlled by a PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PSK (Phase
More particularly, the present invention relates to a PSK demodulator and a PSK demodulator for performing digital signal processing.
The present invention relates to a K demodulation method.

[0002]

2. Description of the Related Art As a technique for transmitting a digital signal, a technique of QPSK (Quadrature Phase Shift Keying) modulation is widely used. According to the QPSK modulation, the phase of a section of two periods of a carrier wave is changed according to the logical value of a section (dibit) obtained by dividing a digital signal to be transmitted every two bits, and the phase shift of a section immediately before the section is performed. This is a modulation method in which the reference is changed in four ways.

[0003] As a combination of the amount of phase change, for example, (-3 · π / 4) radian, (-π / 4)
A combination of four values that are substantially equal to radian, (π / 4) radian and (3 · π / 4) radian are used.

The QP obtained by QPSK modulation
As a PSK demodulator for demodulating an SK modulated signal, for example, a demodulator shown in FIG. 6 has been conventionally known. As shown in the figure, the demodulator of FIG. 6 includes a delay circuit 101, multipliers 102 and 107, low-pass filters 103 and 1,
08, sampling circuits 104 and 109, a phase shifter 105, and a synchronizing signal regenerator 106.

In the demodulator shown in FIG. 6, a QPSK modulated signal as a received signal is first supplied to a delay circuit 101 and a multiplier 1
02 and 107. The delay circuit 101 generates a signal obtained by delaying the received signal by one symbol time (that is, a time corresponding to one dibit), and
And to the phase shifter 105.

[0006] The multiplier 102 is provided with the received signal and the delay circuit 10.
A signal indicating the result of multiplying the signal supplied from 1 is supplied to the low-pass filter 103. Low-pass filter 1
03 is QP of the signals supplied from the multiplier 102.
The component including the SK-modulated original data is supplied to the sampling circuit 104. The sampling circuit 104 samples the signal supplied thereto and outputs it as an output signal of an I baseband component.

On the other hand, the phase shifter 105 generates a signal obtained by shifting the phase of the signal supplied from the delay circuit 101 by (π / 2) radians and supplies the signal to the multiplier 107. The multiplier 107 supplies a signal indicating a result of multiplying the received signal by the signal supplied from the phase shifter 105 to the low-pass filter 108.
The low-pass filter 108 outputs the signal Q
The component including the original data subjected to the PSK modulation is supplied to the sampling circuit 109, which samples the output and outputs it as an output signal of the Q baseband component. Note that the synchronization signal reproducer 106 generates a sampling signal for determining the timing at which the sampling circuits 104 and 109 perform sampling, and supplies the sampling signal to the sampling circuits 104 and 109.

[0008]

However, when demodulating signals at a plurality of bit rates in the demodulator shown in FIG. 6, the cutoff frequencies of the low-pass filters 103 and 108 and other circuit constants are set to values adapted to the bit rates. It is necessary to Therefore, the low-pass filters 103 and 108 are selected according to the bit rate of the signal to be received.
A process for switching a part or all of is required, and this process is complicated.

Since the low-pass filter is composed of an analog filter including a coil and a capacitor, the low-pass filter shown in FIG.
It is extremely difficult to form the demodulation device as a semiconductor integrated circuit.

As a technique for solving this problem, for example, there is a demodulator disclosed in Japanese Patent Application Laid-Open No. 7-50699. As shown in FIG. 7, the demodulator disclosed in Japanese Patent Laid-Open No. 7-50699 has shift registers 201 and 20.
2, 204 and 207, and EOR elements 203 and 206
And D flip-flops 205 and 208.

In the demodulator shown in FIG. 7, a received signal is supplied to an EOR element 203, EO while a clock signal is supplied to shift registers 201, 202, 204 and 207.
It is supplied to the R element 206 and the shift register 201.

The shift register 201 generates a signal in which the phase of the received signal is advanced by (π / 2) radians and supplies the signal to the shift register 202 and the EOR element 206. The shift register 202 generates a signal in which the phase of the signal supplied from the shift register 201 is delayed by (π / 2) radians and supplies the signal to the EOR element 203.

The EOR element 203 is connected to the shift register 20
2 and a signal indicating the exclusive OR of the received signal and the received signal are supplied to the shift register 204 and the D flip-flop 205. The EOR element 206 supplies a signal indicating the exclusive OR of the signal supplied from the shift register 201 and the received signal to the shift register 207 and the D flip-flop 208.

The shift register 204 includes the EOR element 20
A signal obtained by delaying the phase of the signal supplied from (3) by (π / 2) radians as a clock signal
5 The D flip-flop 205 latches the signal supplied from the EOR element 203 every time the clock signal supplied from the shift register 204 rises,
The latched signal is output as an I output signal.

The shift register 207 includes the EOR element 20
6 is a signal obtained by delaying the phase of the signal supplied from (6) by (π / 2) radians as a clock signal.
8 The D flip-flop 208 latches the signal supplied from the EOR element 206 every time the clock signal supplied from the shift register 207 rises,
The latched signal is output as a Q output signal.

The D flip-flop 205 latches and outputs a low level signal while the duty ratio of the signal supplied from the EOR element 203 is 50% or less.
%, The high level signal is latched and output. The D flip-flop 208 latches and outputs a low-level signal when the duty ratio of the signal supplied from the EOR element 206 is 50% or less, and latches and outputs a high-level signal when the duty ratio exceeds 50%. I do.

In the demodulator shown in FIG. 7, the D flip-flops 205 and 208 are connected to the EOR element 203.
And 206 function as a low-pass filter that passes components including the original data that has been QPSK-modulated among the signals output. Therefore, the demodulation device in FIG. 7 does not require a low-pass filter composed of an analog filter, and does not require switching of the low-pass filter.

However, each shift register of the demodulator of FIG. 7 causes a signal delay, and the amount of delay is not affected by the bit rate of the received signal. Therefore, as the bit rate of the received signal increases, the ratio of the delay amount to the bit rate increases, and demodulation is not performed normally.

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and has a PSK demodulator and a PSK demodulator for accurately demodulating a high-speed PSK modulated signal without using an analog filter.
It is an object to provide a K demodulation method.

[0020]

To achieve the above object, a PSK demodulator according to a first aspect of the present invention comprises:
Π / 4 shift QPSK (Quadrature Phase S
hift keying) delay means for generating a delay signal representing a signal obtained by delaying the modulated signal by a time substantially occupied by a section corresponding to one symbol, and π of the demodulation target after the delayed signal makes a predetermined transition. A detection means for generating a detection signal that maintains a predetermined logic value until the シ フ ト shift QPSK modulation signal makes the predetermined transition; and a detection means for demodulating the demodulation target from the time when the delay signal makes the predetermined transition. Storage means for storing each logical value of the detection signal at a timing when each time of a quarter cycle, a half cycle, and a three-quarter cycle of the carrier of the π / 4 shift QPSK modulation signal has substantially elapsed. And quaternary conversion means for generating 2-bit demodulated data representing a result of converting each set of logical values stored in the storage means into quaternary data according to a predetermined rule and sequentially outputting the data. I do.

Such a PSK demodulator does not require a low-pass filter composed of an analog filter,
It demodulates a K-modulated signal and demodulates a QPSK-modulated signal having various carrier frequencies without switching a low-pass filter. The demodulation result is quaternized and output as 2-bit demodulated data. Further, according to such a PSK demodulator, since the signal is not delayed by the shift register, even if the bit rate of the received signal is increased,
The ratio of the delay amount to the bit rate does not increase, so that the high-speed QPSK modulated signal is accurately demodulated.

[0022] The PSK demodulation device is configured to demodulate the π to be demodulated.
/ 4 shift QPSK modulation signal is binarized and sampled,
A binarizing unit that outputs a binarized π / 4-shifted QPSK modulation signal, wherein the delay unit and the detection unit include:
The binarized π / 4 shift Q output by the binarization means
The PSK modulation signal is converted into a π / 4 shift QPS to be demodulated.
The signal may be handled as a K modulation signal. With such a configuration, even if the QPSK modulation signal includes noise and the like, the noise and the like are removed, and the demodulation of the QPSK modulation signal is reliably performed.

The binarizing means may binarize and sample the π / 4 shift QPSK modulated signal in synchronization with a sampling signal supplied thereto. In this case, the PSK demodulation device includes a sampling signal phase adjusting unit that generates the sampling signal such that a phase difference between the demodulated data and the demodulated data becomes a substantially constant value and supplies the sampling signal to the binarizing unit. Then, as a result of keeping the phase difference between the demodulated data and the sampling signal constant, it is possible to prevent a situation in which the demodulated data includes jitter caused by a variation in the phase difference between the demodulated data and the sampling signal.

The PSK demodulation device mixes the π / 4 shift QPSK modulation signal to be demodulated supplied to itself and the local oscillation signal supplied to itself, and demodulates the frequency obtained from the signal obtained by the mixing. Frequency conversion means for extracting a target π / 4 shift QPSK modulation signal, and the local oscillation signal having a substantially constant phase difference from the sampling signal, and supplying the local oscillation signal to the frequency conversion means And a local oscillation signal phase adjusting means.
The value conversion means synchronizes with the sampling signal supplied thereto and converts the frequency-converted demodulation target π / 4 shift QP
The SK modulation signal may be binarized and sampled. With this configuration, the phase difference between the sampling signal and the local oscillation signal is kept constant,
This prevents a situation in which the demodulated data includes jitter due to a variation in the phase difference between the sampling signal and the local oscillation signal.

Further, the PS according to the second aspect of the present invention
The K demodulator is used to construct a digital signal to be transmitted.
A multi-level PSK (Phase Shift Keying) modulation signal to be demodulated, which sequentially represents bit (where n is a natural number) data values by 2 ⁿ types of carrier phase shifts in one symbol section, receives the n-bit data. A multi-level PSK demodulator for restoring data, a delay means for generating a delay signal representing a multi-level PSK modulation signal to be demodulated delayed by a time substantially occupied by a section corresponding to one symbol, Detecting means for generating a detection signal that maintains a predetermined logical value from the time when the delayed signal makes a predetermined transition to the time when the multilevel PSK modulated signal to be demodulated makes the predetermined transition; and Specifies each logical value of the detection signal at a timing when a plurality of predetermined times have substantially elapsed from the time when the predetermined transition has been performed, and based on the specified logical values, the n bits And restoration means for restoring the data.

Such a PSK demodulator does not require a low-pass filter composed of an analog filter, and has a multi-valued PSK demodulator.
The SK modulation signal is demodulated, and the multi-level PSK modulation signal having various carrier frequencies is demodulated without switching the low-pass filter. The demodulation result is output as n-bit data. Further, according to such a PSK demodulator, since the signal is not delayed by the shift register,
Even if the bit rate of the received signal increases, the ratio of the delay amount to the bit rate does not increase, so that the high-speed multi-level PSK modulation signal is accurately demodulated.

The restoration means includes, for example, a register for storing each logical value of the detection signal at a timing when a plurality of predetermined times have substantially elapsed from the time when the delay signal has made the predetermined transition; And a decoder for generating the n-bit data representing the result of converting each set of logical values stored in the register according to a predetermined rule, thereby restoring the n-bit data.

The multi-level PSK modulated signal to be demodulated is obtained by converting the value of 2-bit data constituting the digital signal to be transmitted to (-3 · π /
4) A quaternary PSK modulation signal that is sequentially represented by four kinds of phase shifts of radian, (−π / 4) radian, (π / 4) radian, and (3 · π / 4) radian may be used.
In this case, the restoring means may perform a quarter period, a half period, and a three-quarter period of the carrier of the multi-level PSK modulation signal to be demodulated from the time when the delay signal makes the predetermined transition. If it is assumed that each logical value of the detection signal is specified at a timing when each time of the cycle has substantially elapsed, and the 2-bit data is restored based on each specified logical value, it is constituted by an analog filter. A high-speed quaternary PSK modulated signal having various carrier frequencies can be accurately demodulated without requiring a low-pass filter or switching of the low-pass filter.

The PSK demodulating apparatus includes a binarizing means for binarizing and sampling the multi-level PSK modulation signal to be demodulated and outputting a binarized multi-level PSK modulation signal, The detecting means may handle the binarized multi-level PSK modulated signal output by the binarizing means as the multi-level PSK modulated signal to be demodulated.
With such a configuration, even if the multi-level PSK modulation signal includes noise and the like, the noise and the like are removed and the multi-level PSK modulation signal is removed.
The demodulation of the modulated signal is performed reliably.

The binarizing means may binarize and sample the multi-level PSK modulated signal in synchronization with a sampling signal supplied thereto. In this case, the PSK demodulation device includes a sampling signal phase adjustment unit that generates the sampling signal such that the phase difference from the n-bit data becomes substantially constant and supplies the sampling signal to the binarization unit. If provided, n representing the demodulation result
As a result of keeping the phase difference between the bit data and the sampling signal constant, it is possible to prevent a situation in which jitter due to the variation in the phase difference between the n-bit data and the sampling signal is included in the n-bit data. You.

The PSK demodulator mixes the multi-level PSK modulated signal to be demodulated supplied thereto and the local oscillation signal supplied to itself, and converts a signal obtained by the mixing into a frequency-converted demodulated signal. Frequency conversion means for extracting a multi-level PSK modulation signal; and a local oscillation signal phase for generating the local oscillation signal such that the phase difference between the sampling signal and the sampling signal becomes substantially constant and supplying the signal to the frequency conversion means. Adjusting means, wherein the binarizing means binarizes and samples the frequency-converted demodulated multi-level PSK modulated signal in synchronization with the sampling signal supplied thereto. . With this configuration, the phase difference between the sampling signal and the local oscillation signal is kept constant. As a result, the jitter caused by the variation in the phase difference between the sampling signal and the local oscillation signal is n bits representing the demodulation result. Is prevented from being included in the data.

The PS according to the third aspect of the present invention
The K demodulation method uses a π / 4 shift QPSK (Quad
(rature Phase Shift Keying) a delay step of generating a delay signal representing a signal obtained by delaying a modulated signal by a time substantially occupied by a section corresponding to one symbol; A detection step of generating a detection signal that maintains a predetermined logical value until the π / 4 shift QPSK modulation signal performs the predetermined transition, and from the time when the delayed signal performs the predetermined transition,
Each logical value of the detection signal at a timing substantially elapse of a quarter period, a half period, and a three-quarter period of the carrier of the π / 4 shift QPSK modulation signal to be demodulated is represented by A storage step of storing; and a quaternary conversion step of generating 2-bit demodulated data representing a result of converting each set of logical values stored in the storage step into quaternary data according to a predetermined rule and sequentially outputting the data. It is characterized by including.

In such a PSK demodulation method, the QP demodulation method does not require a low-pass filter composed of an analog filter.
The SK modulation signal is demodulated, and the QPSK modulation signals having different carrier frequencies are demodulated without switching the low-pass filter. The demodulation result is quaternized and output as 2-bit demodulated data. Also, such a P
According to the SK demodulation method, no signal delay is caused by the shift register. Therefore, even if the bit rate of the received signal increases, the ratio of the delay amount to the bit rate does not increase. Is accurately demodulated.

A computer-readable recording medium according to a fourth aspect of the present invention includes a computer
Π / 4 shift QPSK (Quadrature Phase S
hift keying) delay means for generating a delay signal representing a signal obtained by delaying the modulated signal by a time substantially occupied by a section corresponding to one symbol, and π of the demodulation target after the delayed signal makes a predetermined transition. A detection means for generating a detection signal that maintains a predetermined logic value until the シ フ ト shift QPSK modulation signal makes the predetermined transition; and a detection means for demodulating the demodulation target from the time when the delay signal makes the predetermined transition. Storage means for storing each logical value of the detection signal at a timing when each time of a quarter cycle, a half cycle, and a three-quarter cycle of the carrier of the π / 4 shift QPSK modulation signal has substantially elapsed. And quaternary conversion means for generating 2-bit demodulated data representing a result of converting each set of logical values stored in the storage means into quaternary data according to a predetermined rule and sequentially outputting the data. Blog And characterized by recording the beam.

A computer that executes a program recorded on such a recording medium demodulates a QPSK modulated signal without the need for a low-pass filter composed of an analog filter, and without switching between low-pass filters.
The demodulation of QPSK modulation signals having different carrier frequencies is performed. The demodulation result is quaternized and output as 2-bit demodulated data. Also, a computer that executes a program recorded on such a recording medium does not cause a signal delay due to the shift register, so that even if the bit rate of the received signal increases, the ratio of the delay amount to the bit rate increases. And thus accurately demodulate the high-speed QPSK modulated signal.

[0036]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a PSK (Phase Shift Keying) demodulator according to an embodiment of the present invention will be described using a π / 4 shift QPSK (Quadrature Phase Shift Keying) receiver as an example.

(First Embodiment) FIG. 1 shows an example of a configuration of a π / 4 shift QPSK receiver according to a first embodiment of the present invention. As shown, the π / 4 shift QPSK receiver includes an antenna 1 and an RF (Radio Freq).
uency) an amplifier 2, a mixer 3, a local oscillator 4, a sampler 5, a sampling signal generator 6, a delay unit 7, a detector 8, a shift register 9, a conversion clock generator 10, And a quaternary converter 11 and a clock regenerator 12.

The RF amplifier 2 uses the electromagnetic wave to
Is supplied from the antenna 1, the signal supplied to itself is amplified and supplied to the mixer 3.

The mixer 3 converts a signal representing a component of a signal representing the product of two signals supplied from the RF amplifier 2 and the local oscillator 4 whose frequency is substantially equal to the difference between the frequencies of the two signals. Generated and supplied to the sampler 5.

The local oscillator 4 includes an oscillator for generating a square wave, and outputs a signal representing a square wave having a frequency substantially equal to the sum of a predetermined intermediate frequency and the carrier frequency of the signal supplied by the RF amplifier 2. Generate and supply to the mixer 3.

The sampler 5 constitutes a binarizing means. In response to the sampling signal supplied from the sampling signal generator 6, the instantaneous value of the signal supplied from the mixer 3 is changed to a predetermined threshold value. Is determined, the signal supplied from the mixer 3 is binarized according to the determination result, and a digital signal (current data) obtained as a result of the binarization is output. Specifically, for example, each time the sampling signal rises, the sampler 5 determines whether or not the instantaneous value of the signal supplied from the mixer 3 exceeds a threshold value. Is output, and if not exceeded, a predetermined low-level voltage is generated to output the current data.

The sampling signal generator 6 has an oscillator for generating a rectangular wave, and generates a sampling signal. The frequency of the sampling signal may be, for example, at least twice the above-mentioned intermediate frequency.

The delay unit 7 constitutes a delay unit, acquires the current data output from the sampler 5,
It generates and outputs a digital signal (delayed data) obtained by delaying the acquired current data by substantially one symbol (that is, two bits).

The detector 8 constitutes a detecting means. The detector 8 obtains the current data output from the sampler 5 and the delay data output from the delay unit 7, and detects the detected data based on the current data and the delay data. Generate and output a signal.

Specifically, for example, when the acquired delay data rises, the detector 8 responds to the rise, and thereafter outputs a high-level voltage as a detection signal until the rise of the current data is detected. I do. When the acquired current data rises, it responds to the rise, and thereafter outputs a low-level voltage as a detection signal until the rise of the delayed data is detected.
As a result, the detection signal includes a digital signal having a high-level voltage during a period from the rise of the delayed data to the rise of the current data, and a low-level voltage during the other periods.

The shift register 9 constitutes storage means or restoration means, and acquires the detection signal output from the detector 8 and a later-described conversion clock signal supplied by the conversion clock generator 10. When the conversion clock signal enters a predetermined state (for example, when the voltage of the conversion clock signal rises from a low level to a high level), the logic value of the detection signal at that time is stored. Then, the shift register 9 keeps holding three new logical values stored therein, and outputs 3-bit data representing the logical value currently held by itself.

The shift register 9 obtains an output clock, which will be described later, generated by the clock regenerator 12, detects that the output clock has risen, and stores the 3-bit data stored in its own memory. If the data is binary "0"
The bits are reset so as to represent 00 ". When the shift register 9 detects that the power is supplied to the QPSK demodulator, the shift register 9 resets these bits.

The conversion clock generator 10 generates a conversion clock signal that transitions at the timing described later, and supplies it to the shift register 9 and the clock regenerator 12.

The quaternary converter 11 constitutes quaternary conversion means or restoration means. The quaternary converter 11 acquires the 3-bit data output by the shift register 9,
An output clock signal to be described later is obtained from the clock regenerator 12 to generate 2-bit data representing the value of the 3-bit data obtained from the shift register, and output as a demodulated signal in synchronization with the output clock signal. I do.

The 2-bit data output from the quaternary converter 11 is synchronized with the output clock signal generated by the clock regenerator 12. Specifically, the transition (rise and fall) of the logical value of each bit of the 2-bit data occurs substantially simultaneously with the rise of the output clock signal. In addition, as described later,
Since the 3-bit data output from the shift register 9 takes four types of values, the size of the information indicating which value of the 4-bit data takes two bits is sufficient.

The clock regenerator 12 obtains a conversion clock signal from the conversion clock generator 10, generates an output clock signal that transitions at a timing described later based on the obtained conversion clock signal, and performs quaternary conversion. To the vessel 11.

(Operation) Next, this π / 4 shift QPSK
The operation of the receiver will be described. When the π / 4 shift QPSK receiver is started, the RF amplifier 2 acquires the QPSK modulated wave induced by the antenna 1 from the antenna 1, amplifies the wave, and supplies it to the mixer 3. On the other hand, the shift register 9
Upon detecting the power-on, the 3-bit data stored in its own memory represents the binary number "000".

The QPSK modulated wave acquired by the RF amplifier 2 divides each section obtained by dividing a rectangular wave whose frequency is equal to the carrier frequency every two periods into two bits from the top of the digital signal to be transmitted. In accordance with the value of the dibit obtained in this way, the phase is sequentially shifted by one of the four values with reference to the phase of the immediately preceding two periods.

More specifically, the QPSK modulated wave includes, for example, (a1) When the value of the dibit is a binary number “00”,
The two periods of the rectangular wave are compared with the immediately preceding two periods by (π /
4) Advance in radians. (A2) If the value of the dibit is a binary number “01”, advance by (3 · π / 4) radians as compared with the immediately preceding two periods. (A3) The value of the dibit is a binary number “10”. , The delay is delayed by (π / 4) radians compared to the immediately preceding two periods. (A4) If the value of the dibit is a binary number “11”, the delay is (3 · π / 4) radians compared to the immediately preceding two periods. It has been delayed.

The local oscillator 4 includes the RF amplifier 2 and the mixer 3
, A signal representing a rectangular wave having a frequency substantially equal to the sum of the carrier frequency of the QPSK modulated wave supplied and the above-mentioned intermediate frequency is supplied to the mixer 3. Mixer 3 is RF
When signals are supplied from the amplifier 2 and the local oscillator 4, respectively, of the signal representing the product of these two signals, the frequency thereof is substantially equal to the difference between the frequencies of the two signals (that is, the component described above). A signal representing a component having an intermediate frequency as a carrier frequency is generated and supplied to the sampler 5.

Each time the sampling signal supplied from the sampling signal generator 6 rises, the sampler 5 determines whether or not the signal supplied from the mixer 3 exceeds a predetermined threshold value. The signal supplied from the device 3 is binarized. And the sampler 5
Supplies the current data obtained by the binarization to the delay unit 7 and the detector 8.

When the current data is supplied from the sampling unit 5, the delay unit 7 outputs a signal obtained by substantially delaying the current data by one symbol, that is, delay data.
The length of time for one symbol is substantially equal to twice the reciprocal of the above-mentioned intermediate frequency.

When the detector 8 acquires the current data from the sampling device 5 and acquires the delayed data from the delay device 7,
A detection signal is generated and output based on the current data and the delay data supplied to the self substantially simultaneously.

Specifically, the detection signal output from the detector 8 is, for example, as shown in FIG. 2, a high-level voltage during a period from the rise of the delay data to the rise of the current data, and the other period is a high-level voltage. The digital signal is a low level voltage. Therefore, the length of the period in which the voltage of the detection signal is at the high level indicates the time difference between the timing when the delayed data rises and the timing when the current data rises.

On the other hand, the conversion clock generator 10 obtains one symbol of delayed data from the detector 8, generates a conversion clock signal based on the delayed data, and supplies it to the shift register 9. Specifically, as shown in FIG. 2, the conversion clock signal has a phase of the delayed data substantially (π / 2) radians, π radians, and (3 · π).
/ 2) composed of pulses rising at a timing of radian, and the length of each pulse is equal to 4 of the delay data.
It is shorter than one-half cycle.

When the shift register 9 obtains the detection signal output from the detector 8 and obtains the conversion clock signal from the conversion clock generator 10, each time the conversion clock signal rises, the shift register 9 outputs the detection signal. The logical value is stored, and 3-bit data representing the latest three logical values stored by itself is output.

The 3-bit data takes four values. Specifically, for example, as shown in FIG. 2, (b1) when the current data is advanced by (π / 4) radians compared to the delay data, the binary number becomes “111”, and (b2) the current data is the delay data. (3π /
4) When advancing in radians, the binary number becomes “110”. (B3) When the current data is delayed by (π / 4) radians compared to the delayed data, it becomes a binary number “000”. (3π /
4) When it is delayed by radians, the binary number is "100".

On the other hand, the clock regenerator 12 generates an output clock signal synchronized with the timing at which the detector 8 outputs the detection signal, and supplies the output clock signal to the shift register 9 and the quaternary converter 11. . Specifically, the output clock signal is, for example, one time from the rising of the sixth pulse after the delay data for one symbol starts being output from the delay unit 7 to the rising of the next pulse. It is a digital signal that rises and falls.

When the three-bit data output from the shift register 9 is obtained, the four-value converter 11 generates two-bit data indicating which of the four values the three-bit data takes. I do. More specifically, (c1) when the value of the 3-bit data output from the shift register 9 is a binary number “111”, the quaternary converter 11 outputs the binary number “00”. When the value of the 3-bit data output by the shift register 9 is a binary number “110”, the result is a binary number “01”. (C3) When the value of the 3-bit data output by the shift register 9 is a binary number “000” (C4) When the value of the 3-bit data output from the shift register 9 is the binary number "100", the binary number is "11".

Each time the output clock output by the clock regenerator 12 rises, the quaternary converter 11
It outputs 2-bit data generated by itself. Thus, the 2-bit data is output in synchronization with the output clock. The 2-bit data represents the demodulated data. The shift register 9 also acquires an output clock, and resets each bit stored therein when the output clock rises.

The configuration of the π / 4 shift QPSK receiver is not limited to the above. For example, some or all of the functions of the sampling signal generator 6, the delay unit 7, the detector 8, the shift register 9, the conversion clock generator 10, the quaternary converter 11, and the clock regenerator 12 are implemented by a DSP (Division).
gital Signal Processor) and CPU (Central Processi)
ng Unit). Further, the sampler 5 may be constituted by an A / D (Analog-to-Digital) converter. Further, the mixer 3 and the local oscillator 4
A part or all of the functions of A / D converter, DSP and D
It may be performed by an / A (Digital-to-Analog) converter.

Further, the π / 4 shift QPSK receiver does not need to obtain the QPSK modulated wave from the antenna 1, but may obtain the QPSK modulated wave from a wired line, for example. Further, the target digital signal subjected to the QPSK modulation may be a signal to which modulation by an arbitrary method is added in advance. A mixer 3 and a local oscillator 4
And the RF amplifier 2 are both unnecessary and can be omitted.

As long as the desired demodulation accuracy is obtained,
The timing at which the conversion clock signal generated by the conversion clock generator 10 rises does not need to exactly match the above timing. In addition, the pulse constituting the conversion clock signal has a phase of substantially (π / 2) radian, π radian, and (3 · π /) for at least one of the delay data of two periods of the carrier wave.
2) It only has to rise at a timing of radian. Therefore, the pulse constituting the conversion clock signal only needs to rise at least three times among the delay data of two periods of the carrier wave.

[0069] Also, the [pi / 4 shift QPSK receiver, N bits constituting the digital signal to be transmitted (where, N is the natural number) data values of the 2 ^N Street carriers in one symbol period of the phase N-bit data representing a result of demodulating a multi-level PSK (Phase Shift Keying) modulated wave sequentially represented by a shift may be generated and output. However, in this case, the conversion clock generator 10
Generates a conversion clock signal at a sufficiently narrow interval such that the data stored and output by the shift register 9 includes information sufficient to restore the N-bit data representing the demodulation result. The shift register 9 outputs data representing a predetermined number of values from the newly stored logical value among the logical values stored therein. However, the predetermined number is sufficient to restore N-bit data representing the demodulation result. Then, four-value converter 11, the shift register 9 acquires the output data, the acquired data to generate data of N bits representing whether taking any value 2 ^N as described above.

(Second Embodiment) The π / 4 shift QPSK receiver of the first embodiment described above has a local oscillator 4
Is generated and the signal generated by the sampling signal generator 6 are not synchronized, the phase difference between these two signals may be different each time the operation is performed (that is, the local The value of the phase difference between the signal generated by the oscillator 4 and the sampling signal varies.) For this reason, the data generated by performing the QPSK demodulation by the π / 4 shift QPSK receiver of the first embodiment may include jitter. In order to prevent the jitter, for example, the carrier component of the QPSK modulated wave may be synchronized with a signal that determines the timing of sampling the QPSK modulated wave. In the following, a configuration for synchronizing a signal generated by the local oscillator 4 with a signal generated by the sampling signal generator 6 will be described as a second embodiment.

FIG. 3 shows an example of the configuration of a π / 4 shift QPSK receiver according to the second embodiment of the present invention.
As shown, this π / 4 shift QPSK receiver has:
In addition to the configuration shown in FIG. 1, frequency dividers 21a and 21b, a phase comparator 22, and a low-pass filter 23 are further provided.

However, the local oscillator 4 in the configuration of FIG.
Is a VCO (Voltage Controlled Osc) that generates a square wave
illator) and the like, and changes the frequency of the rectangular wave generated by itself by an amount specified by the control signal supplied to itself. In a state where the control signal has not been supplied to itself, the local oscillator 4 generates, for example, a rectangular wave having a predetermined free running frequency. The mixer 3 constitutes a frequency converter, and includes the local oscillator 4, frequency dividers 21a and 21b, and a phase comparator 22.
And the low-pass filter 23 constitute a local oscillation signal phase adjusting unit.

Each of the frequency dividers 21a and 21b is composed of, for example, a flip-flop circuit, a counter circuit and the like. The frequency divider 21a obtains a signal generated by the mixer 3 and supplied to the sampler 5, and divides the obtained signal by a predetermined frequency division ratio p (where p is a natural number) (that is, mixing is performed). A signal having a frequency substantially equal to 1 / p of the frequency of the signal supplied to the frequency divider 21a from the frequency divider 3). Then, the signal obtained by the frequency division is
The signal is supplied to the phase comparator 22 with the phase difference between the signal obtained by itself and the signal obtained by frequency division kept constant.
The frequency divider 21b acquires a sampling signal generated by the sampling signal generator 6, divides the acquired signal by a dividing ratio q (where q is a natural number) described later, and obtains a signal obtained by dividing. Is supplied to the phase comparator 22 with the phase difference between the signal obtained by itself and the signal obtained by frequency division kept constant.

The phase comparator 22 is composed of a multiplying circuit and the like, and generates a control signal representing a phase difference between the carrier component of the signal supplied from the frequency divider 21a and the signal supplied from the frequency divider 21b. The generated control signal is transmitted to the local oscillator 4
Is supplied to the low-pass filter 23 as a signal for designating a change in the frequency of the signal generated by. The low-pass filter 23 substantially removes a harmonic component included in the control signal supplied from the phase comparator 22, and supplies the control signal from which the harmonic component has been removed to the local oscillator 4.

The control signal output from the phase comparator 22 is based on the carrier component of the signal supplied from the frequency divider 21a and the frequency divider 2
When the phase difference from the signal supplied from 1b is substantially 0, the change in the frequency of the signal generated by the local oscillator 4 is specified as substantially 0 (that is, the local oscillator 4 is actually To keep the frequency of the signal being generated.)

On the other hand, when the phase of the carrier component of the signal supplied from frequency divider 21a is ahead of the phase of the signal supplied from frequency divider 21b, the change indicated by the control signal output from phase comparator 22 Minutes are negative. That is, it is specified that the frequency of the signal generated by the local oscillator 4 be reduced. Further, when the phase of the carrier component of the signal supplied from the frequency divider 21a is delayed from the phase of the signal supplied from the frequency divider 21b, the change indicated by the control signal output from the phase comparator 22 is positive. Value. That is,
This specifies that the frequency of the signal generated by the local oscillator 4 be increased. However, regardless of whether the value of the change is positive or negative, the absolute value of the change specified by the control signal is
The larger the phase difference between the carrier component of the signal supplied from the frequency divider 21a and the signal supplied from the frequency divider 21b, the larger the value.

In the configuration of FIG. 3, when the frequency of the carrier component of the signal generated by the mixer 3 is higher than p, which is q of the frequency of the sampling signal, the phase comparator 22 determines the amount of change in the negative value. Since the designated control signal is supplied to the local oscillator 4, the frequency of the signal generated by the local oscillator 4 decreases. Conversely, when the frequency of the carrier component of the signal generated by the mixer 3 is lower than p, which is q of the frequency of the sampling signal, the phase comparator 22 outputs a control signal designating a positive value change to the local oscillator. 4, the frequency of the signal generated by the local oscillator 4 increases.

The frequency of the carrier component of the signal generated by the mixer 3 is calculated from the frequency of the signal generated by the local oscillator 4 by R
It is substantially equal to a value obtained by subtracting the carrier frequency of the QPSK modulated wave to be demodulated supplied by the F amplifier 2. Therefore, the frequency of the carrier component of the signal generated by the mixer 3 converges to a value of p for q of the frequency of the sampling signal. Then, the carrier component of the signal generated by the mixer 3 keeps a constant phase difference with the sampling signal. That is, the carrier component of the signal generated by the mixer 3 is synchronized with the sampling signal.

The value obtained by subtracting the carrier frequency of the QPSK modulated wave to be demodulated from the value of p for q of the frequency of the sampling signal is the above-mentioned intermediate frequency (that is, the reciprocal of the time width during which the delay unit 7 delays the current data). ), The quaternary converter 11 sequentially outputs 2-bit data representing QPSK demodulated data of the QPSK modulated wave to be demodulated. Then, the data output by the quaternary converter 11 does not substantially include jitter caused by variation in the value of the phase difference between the signal generated by the local oscillator 4 and the sampling signal.

Note that the π / 4 shift Q of the second embodiment is
The PSK receiver is not limited to those described above. For example, the functions of the frequency dividers 21a and 21b, the functions of the phase comparator 22, and the low-pass filter 23 may be performed by a DSP or a CPU. Further, part or all of the functions of the local oscillator 4 may be performed by a DSP and a D / A converter.

The frequency division ratio of the frequency divider 21a and the frequency divider 2
The frequency division ratio of 1b is also arbitrary. Therefore, at least one of the frequency dividers 21a and 21b may be one that can change the frequency division ratio (therefore, the ratio between the value of p and the value of q can be changed).

(Third Embodiment) The reason why data obtained by demodulation of a QPSK modulated wave includes jitter is that a signal for determining the timing of sampling the QPSK modulated wave and a signal generated as a result of quaternary conversion. Variation in phase difference from 2-bit data is also conceivable. Therefore, QP
By synchronizing the signal for determining the timing of sampling the SK modulated wave with the 2-bit data generated as a result of the quaternary conversion, it is possible to prevent a situation where the data representing the demodulated result of the QPSK modulated wave includes jitter. Is achieved. Hereinafter, as a third embodiment, a configuration for synchronizing a signal generated by the sampling signal generator 6 with 2-bit data generated by the quaternary converter 11 will be described.

FIG. 4 shows an example of the configuration of a π / 4 shift QPSK receiver according to the third embodiment of the present invention.
As shown, this π / 4 shift QPSK receiver has:
In addition to the configuration shown in FIG. 1, a frequency divider 31 and a phase comparator 32
And a low-pass filter 33.

However, the sampling signal generator 6 in the configuration of FIG. 4 is composed of a VCO or the like that generates a rectangular wave as a sampling signal, and changes the frequency of the sampling signal generated by itself to the control signal supplied to itself. Is changed by the amount specified by. In a state where the control signal has not been supplied to itself, the sampling signal generator 6 generates a sampling signal having a predetermined free running frequency, for example. The mixer 3 forms a frequency conversion unit, and the sampling signal generator 6, the frequency divider 31, the phase comparator 32, and the low-pass filter 33 form a sampling signal phase adjusting unit.

The frequency divider 31 is composed of, for example, a flip-flop circuit, a counter circuit and the like. Frequency divider 31
Obtains a sampling signal generated by the sampling signal generator 6 and divides the obtained signal by a dividing ratio p (where p
Is a natural number), and supplies the signal obtained by the frequency division to the phase comparator 32 while keeping the phase difference between the signal obtained by itself and the signal obtained by the frequency division constant.

The phase comparator 32 is composed of a multiplication circuit and the like, and generates a control signal representing a phase difference between the signal supplied from the frequency divider 31 and the 2-bit data output from the quaternary converter 11. Then, the generated control signal is supplied to the low-pass filter 33 as a signal for designating a change in the frequency of the sampling signal. The low-pass filter 33 substantially removes a harmonic component included in the control signal supplied from the phase comparator 32 and supplies the control signal from which the harmonic component has been removed to the sampling signal generator 6.

When the phase difference between the signal supplied from the frequency divider 31 and the 2-bit data output from the quaternary converter 11 is substantially 0, the control signal output from the phase comparator 32 The change in the frequency of the signal is designated as substantially zero. On the other hand, when the phase of the carrier component of the signal supplied from the frequency divider 31 is ahead of the phase of the 2-bit data output from the quaternary converter 11, the sampling indicated by the control signal output from the phase comparator 32 The change in the frequency of the signal has a negative value. The phase of the carrier component of the signal supplied from the frequency divider 31 is
The change in the frequency of the sampling signal indicated by the control signal output by the phase comparator 32 when the phase is delayed from the phase of the 2-bit data output by the controller becomes a positive value. When the value of the change in the sampling signal is either positive or negative,
The absolute value of the change specified by the control signal is set to be larger as the phase difference between the signal supplied from the frequency divider 31 and the 2-bit data output from the quaternary converter 11 is larger.

In the configuration of FIG. 4, when the frequency of the sampling signal is higher than m times the frequency of the 2-bit data output from the quaternary converter 11, the phase comparator 32 detects the change in the negative value. Since the designated control signal is supplied to the sampling signal generator 6, the frequency of the sampling signal decreases. Conversely, when the frequency of the sampling signal is lower than m times the frequency of the 2-bit data output from the quaternary converter 11, the phase comparator 32 generates a control signal designating a positive value change by generating a sampling signal. To supply to vessel 6
The frequency of the sampling signal increases.

Therefore, the frequency of the sampling signal is 4
M of the frequency of the 2-bit data output from the value converter 11
Converges to double the value. Then, the sampling signal maintains a constant phase difference with the frequency of the 2-bit data output from the quaternary converter 11. That is, the sampling signal is synchronized with the 2-bit data output from the quaternary converter 11. As a result, the data output by the quaternary converter 11 is
The jitter caused by the variation in the phase difference between the sampling signal and the data output from the quaternary converter 11 is substantially not included.

Note that the π / 4 shift Q of the third embodiment
The PSK receiver is not limited to those described above. For example, the function of the frequency divider 31, the function of the phase comparator 32, and the function of the low-pass filter 33 may be performed by a DSP or a CPU. Further, part or all of the function of the sampling signal generator 6 may be performed by a DSP and a D / A converter. Further, since the frequency division ratio of the frequency divider 31 is arbitrary, the frequency divider 31 may be one that can change the frequency division ratio.

Further, as shown in FIG. 5, this π / 4 shift QPSK receiver has, in addition to the configuration shown in FIG.
The aforementioned frequency dividers 21a and 21b, the phase comparator 22,
A low-pass filter 23 may be provided. In the π / 4 shift QPSK receiver having the configuration shown in FIG. 5, the signal generated by the local oscillator 4, the sampling signal, and the quaternary converter 11
Are synchronized with each other with the 2-bit data output by the. For this reason, the data output by the quaternary converter 11 having the configuration of FIG. 5 includes the jitter caused by the variation in the phase difference between the signal generated by the local oscillator 4 and the sampling signal, and the sampling signal and the quaternary converter. Jitter due to a variation in the phase difference value with the data output from the data 11 is also substantially not included.

The PSK demodulator according to the present invention has been described above. However, the PSK demodulator according to the present invention can be realized using an ordinary computer system without using a dedicated system. For example, in a personal computer having an A / D converter and a D / A converter, the program is installed from a medium (floppy (registered trademark) disk, CD-ROM, etc.) storing the program for executing the above-described operation. By doing so, the PS that executes the above process
A K demodulator can be configured.

[0093] For example, the program may be posted on a bulletin board (BBS) of a communication network and distributed via the network. Distribution via a network may be performed by transmitting a modulated wave obtained by modulating a carrier wave by the program. Then, by starting this program and executing it in the same manner as other application programs under the control of the OS, the above-described processing can be executed.

If the OS shares part of the processing,
Alternatively, when the OS constitutes a part of one component of the present invention, the recording medium may store a program excluding the part. Also in this case, in the present invention, it is assumed that the recording medium stores a program for executing each function or step executed by the computer.

[0095]

As described above, according to the present invention, a PSK demodulator and a PSK demodulator for accurately demodulating a high-speed PSK modulated signal without using an analog filter.
A K demodulation method is realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of a π / 4 shift QPSK receiver according to a first embodiment of the present invention.

FIG. 2 is a graph schematically showing waveforms of current data, delay data, a detection signal, and a conversion clock.

FIG. 3 is a block diagram showing a basic configuration of a π / 4 shift QPSK receiver according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a basic configuration of a π / 4 shift QPSK receiver according to a third embodiment of the present invention.

FIG. 5 is a block diagram showing a basic configuration of a modification of the π / 4 shift QPSK receiver in FIG. 4;

FIG. 6 is a block diagram showing a configuration of a conventional PSK demodulator.

FIG. 7 is a block diagram showing a configuration of a conventional PSK demodulator.

[Explanation of symbols]

 Reference Signs List 1 antenna 2 RF amplifier 3 mixer 4 local oscillator 5 sampler 6 sampling signal generator 7 delay unit 8 detector 9 shift register 10 conversion clock generator 11 quaternary converter 12 clock regenerator 21a, 21b, 31 frequency division Unit 22, 32 Phase comparator 23, 33 Low-pass filter

Claims (12)

[Claims] 1. A π / 4 shift QPSK (Quadra) to be demodulated.
a delay means for generating a delay signal representing a signal obtained by delaying the modulated signal by a time substantially occupied by a section corresponding to one symbol; and a demodulation target after the delayed signal makes a predetermined transition. Detecting means for generating a detection signal that maintains a predetermined logical value until the π / 4 shift QPSK modulation signal performs the predetermined transition, and demodulation from the time when the delayed signal has performed the predetermined transition. 4 of the carrier of the π / 4 shift QPSK modulated signal of interest
Storage means for storing each logical value of the detection signal at a timing when each time of one-half cycle, one-half cycle, and three-quarter cycle has substantially elapsed; and each logical value stored in the storage means A PSK demodulation device, comprising: four-value conversion means for generating 2-bit demodulated data representing the result of converting the set of data into four values according to a predetermined rule and sequentially outputting the data. 2. A binarizing means for binarizing and sampling the π / 4 shift QPSK modulation signal to be demodulated and outputting a binarized π / 4 shift QPSK modulation signal; The detecting means converts the binarized π / 4 shift QPSK modulated signal output from the binarizing means,
The PSK demodulation device according to claim 1, wherein the PSK demodulation device is treated as a π / 4 shift QPSK modulation signal to be demodulated. 3. The binarizing means binarizes and samples the π / 4 shift QPSK modulation signal in synchronization with a sampling signal supplied to the binarizing means. 3. The PSK demodulator according to claim 2, further comprising: a sampling signal phase adjusting unit that generates the sampling signal having a substantially constant value and supplies the sampling signal to the binarizing unit. 4. A π / 4-shifted QPSK modulated signal to be demodulated supplied to the self and a local oscillation signal supplied to the self are mixed, and a signal obtained by the mixing is converted to a π / shift to be demodulated by the frequency conversion. Frequency conversion means for extracting a 4-shift QPSK modulation signal; and a local oscillation signal phase for generating the local oscillation signal such that a phase difference between the sampling signal and the sampling signal becomes substantially constant and supplying the signal to the frequency conversion means. Adjusting means, wherein the binarizing means binarizes and samples the demodulated π / 4 shift QPSK modulated signal to be demodulated in synchronization with a sampling signal supplied thereto. The PSK demodulator according to claim 2 or 3, wherein: 5. A multi-valued PSK (a demodulation target) which sequentially represents n-bit (where n is a natural number) data values constituting a digital signal to be transmitted by 2 ⁿ kinds of phase shifts of a carrier in one symbol section. Phase Shift Keying) A multi-valued P that receives a modulated signal and restores the n-bit data
An SK demodulation device, comprising: delay means for generating a delay signal representing a signal obtained by delaying the multilevel PSK modulation signal to be demodulated by a time substantially occupied by a section corresponding to one symbol; After performing the transition, a detection unit that generates a detection signal that maintains a predetermined logic value until the multilevel PSK modulation signal to be demodulated performs the predetermined transition, and the delay signal performs the predetermined transition. Restoring means for identifying each logical value of the detection signal at a timing when a plurality of predetermined times have substantially elapsed from the time when the detection was performed, and restoring the n-bit data based on the identified logical values. A PSK demodulator characterized by the above-mentioned. 6. A register for storing each logical value of the detection signal at a timing when a plurality of predetermined times have substantially elapsed from the time when the delayed signal has made the predetermined transition, The PSK demodulator according to claim 5, further comprising: a decoder that generates the n-bit data representing a result of converting each set of logical values stored in the register according to a predetermined rule. 7. The multi-level PSK modulation signal to be demodulated is obtained by converting the value of 2-bit data constituting a digital signal to be transmitted to (-3 · π /
4) A quaternary PSK modulated signal sequentially represented by four kinds of phase shifts of radian, (-π / 4) radian, (π / 4) radian and (3π / 4) radian, wherein the restoration means Means that each time of a quarter period, a half period, and a three-quarter period of the carrier of the multilevel PSK modulation signal to be demodulated is substantially equal to the time from when the delay signal makes the predetermined transition. 7. The PSK demodulator according to claim 5, wherein each of the logical values of the detection signal at the timing at which the time has elapsed is specified, and the 2-bit data is restored based on the specified logical values. 8. . 8. Binarization means for binarizing and sampling the multi-level PSK modulation signal to be demodulated and outputting a binarized multi-level PSK modulation signal, wherein the delay means and the detection means comprise: The PSK demodulation device according to claim 5, 6 or 7, wherein the binarized multi-level PSK modulated signal output by the binarization means is treated as the multi-level PSK modulated signal to be demodulated. . 9. The binarizing means binarizes and samples the multi-level PSK modulation signal in synchronization with a sampling signal supplied to the binarizing means. The PSK demodulation device according to claim 8, further comprising: a sampling signal phase adjusting unit that generates the sampling signal having a substantially constant value and supplies the sampling signal to the binarizing unit. 10. A multi-valued P to be demodulated supplied to itself.
Frequency conversion means for mixing the SK modulation signal and the local oscillation signal supplied thereto and extracting a frequency-converted multi-level PSK modulation signal to be demodulated from a signal obtained by the mixing; Local oscillation signal phase adjusting means for generating the local oscillation signal such that the difference becomes a substantially constant value and supplying the generated local oscillation signal to the frequency conversion means, wherein the binarization means performs sampling supplied to itself. A multi-level PSK to be demodulated which has been frequency-converted in synchronization with a signal;
The PSK demodulator according to claim 8 or 9, wherein the modulation signal is subjected to binarization sampling. 11. A π / 4 shift QPSK (Quad) to be demodulated.
a delay step of generating a delayed signal representing a signal obtained by delaying a modulated signal by a time substantially occupied by a section corresponding to one symbol; A detection step of generating a detection signal that maintains a predetermined logical value until the π / 4 shift QPSK modulation signal performs the predetermined transition; and demodulating the demodulated signal from the time when the delayed signal has performed the predetermined transition. 4 of the carrier of the π / 4 shift QPSK modulated signal of interest
A storage step of storing each logical value of the detection signal at a timing when each time of a half cycle, a half cycle, and a three-fourth cycle has substantially elapsed; and each logic stored in the storage step A PSK demodulation method characterized by comprising: a quaternary conversion step of generating and sequentially outputting 2-bit demodulated data representing a result of converting a set of values into a quaternary value according to a predetermined rule. 12. A computer is connected to a π / 4 shift QPSK (Quadrature Phase S) to be demodulated.
hift keying) delay means for generating a delay signal representing a signal obtained by delaying the modulated signal by a time substantially occupied by a section corresponding to one symbol, and π of the demodulation target after the delayed signal makes a predetermined transition. A detection unit that generates a detection signal that maintains a predetermined logic value until the シ フ ト shift QPSK modulation signal makes the predetermined transition; and from the time when the delayed signal makes the predetermined transition, 4 of the carrier of the π / 4 shift QPSK modulation signal
Storage means for storing each logical value of the detection signal at a timing when each time of one-half cycle, one-half cycle, and three-quarter cycle has substantially elapsed; and each logical value stored in the storage means And a four-value conversion means for generating and sequentially outputting 2-bit demodulated data representing a result of converting the set of data into four values in accordance with a predetermined rule, and a computer-readable recording medium having recorded thereon a program for causing it to function.