JPH1168865A - Data carrier system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To constitute a system of high reliability in simple circuit configuration by dividing the frequency of a clock signal as specified, transmitting it through phase modulation as a frequency signal for subcarrier wave, dividing the carrier frequency of a received signal as specified, extracting a frequency component corresponding to data communication velocity and discriminating whether its phase is proper or not. SOLUTION: A frequency signal AF for carrier wave from an oscillation circuit 1 is inputted to a signal forming circuit 14 for data demodulation at a data demodulation circuit 13 and its frequency is divided into 1/16 stages of four kinds of frequency dividing signals F1, F2, F3 and F4 for data demodulation. When a signal selector circuit 15 for phase discrimination selects the frequency dividing signal F1 for data demodulation as an object signal FX for phase discrimination, the object signal FX for phase discrimination and a received signal RE are mixed by a multiplier circuit 16 composed of an EXOR circuit and inputted to a filter circuit 17, and the frequency component corresponding to data communication velocity is extracted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data carrier comprising, as data storage means, a data carrier provided with a nonvolatile semiconductor memory such as an EEP-ROM or F-RAM, and an access device for accessing the data carrier. Regarding the carrier system.

[0002]

2. Description of the Related Art A so-called battery-less data carrier, which is configured to supply power necessary for operation on the data carrier side from the access device side using electromagnetic induction coupling, has already been generalized. ing. As for modulation and demodulation methods in data communication in a data carrier system, various methods such as amplitude modulation (ASK), phase modulation (PSK), frequency modulation (FSK), and spread spectrum modulation have been put to practical use. However, in recent years, there has been an increasing tendency to employ a phase modulation method due to its excellent noise resistance and the like.

[0003]

When data communication is performed by the phase modulation method, a means for obtaining a detection reference signal for demodulating received data is particularly problematic on the receiving side. A method has been adopted in which a Costas loop using a PLL circuit or the like is provided to reproduce a detection reference signal having an appropriate frequency and phase based on a received data carrier. However, the provision of the Costas loop leads to an increase in the size of the data demodulation circuit or an increase in cost because the circuit configuration becomes complicated.

An object of the present invention is to provide an antenna for transmitting a predetermined carrier wave at an access device side, a modulating means for modulating the carrier wave according to serial transmission data at the time of data transmission, and a data carrier. And a demodulating means for demodulating received data in response to a transmission signal transmitted from the receiving side, wherein the data carrier side receives the antenna via the antenna coil receiving the carrier and the antenna coil. Rectifying means for rectifying a carrier wave to generate a DC power supply serving as power for driving the data carrier itself; and a clock for generating a clock signal having the same frequency as a carrier frequency based on the received carrier wave. A signal generation circuit, reception demodulation means for receiving the received carrier wave and demodulating serial transmission data from the access device, and data for the access device. In a two-way communication type data carrier system having transmission modulation means for returning data, the above-mentioned disadvantages of the prior art can be solved and highly reliable communication can be performed with a simple circuit configuration. It is to realize a data carrier system that can be used.

[0005]

In order to achieve the above object, according to the present invention, the transmission modulation means on the data carrier side performs sub-frequency division by dividing the clock signal by 1 / N (N is an integer). A frequency dividing circuit for forming a carrier frequency signal; a phase modulating circuit for phase modulating the sub-carrier frequency signal in accordance with the content of serial transmission data transmitted to the access device; Switching means for changing the load on the antenna coil, and the demodulation means on the access device side includes: a reception signal component extraction means for extracting the subcarrier frequency signal component from a signal in the antenna; Data demodulating means for receiving the output signal from the component extracting means and demodulating received data, wherein the data demodulating means divides the frequency signal of the power carrier by 1 / N. A data demodulation signal forming means for substantially forming a plurality of types of data demodulation frequency-divided signals having different phases from each other, and converting one of the plurality of types of data demodulation frequency-divided signals into a phase determination target signal A phase determining signal selecting means, a multiplying circuit for substantially mixing the phase determining target signal and the output signal from the received signal component extracting means, and a data communication speed corresponding to an output of the multiplying circuit. A filter circuit for extracting a frequency band component to be determined, the suitability of the phase of the phase determination target signal is determined by the output from the filter circuit, and when it is determined that the phase is inappropriate, the phase determination signal selection means, A phase for outputting a phase determination signal switching signal for reselecting the data demodulation frequency-divided signal of another phase as a new phase determination target signal Determining means, and using the frequency-divided signal for data demodulation having a predetermined phase relationship with respect to the target signal for phase determination as a phase detection reference signal, substantially performing phase detection on an output signal from the received signal component extracting means. Thus, it is characterized in that it is configured to include phase detection means for demodulating received data.

[0006]

1 to 8 show a first embodiment of the present invention.
1 and 2 are block diagrams showing configurations of an access device and a data carrier, respectively.

In the access device shown in FIG. 1, the oscillation circuit 1 outputs a carrier frequency signal FA as an original signal of a carrier transmitted to the data carrier. The carrier frequency signal FA is input to the antenna drive circuit 6 via the data transmission modulation circuit 2 and drives the antenna 7 forming a resonance circuit together with the capacitor C by series resonance. The transmission signal AT output from the transmission data processing circuit 4 is input to the modulation circuit 2, and at the time of serial data transmission from the access device side, the carrier transmitted from the antenna 7 is the data of the transmission signal AT. The amplitude is modulated at a predetermined ratio according to the data contents. The transmission and reception of serial data between the access device side and the data carrier side are performed in a start-stop synchronous manner in any direction, and a carrier wave transmitted from the antenna 7 is transmitted and received. In a state where the signal AT is data "1" (including an idling state in which data is not transmitted from the access device side), the signal AT is in a non-modulation state, and when the transmission signal AT is data "1". In the state of “0”, the modulation is controlled to the modulation state in which the amplitude is suppressed.

On the other hand, the antenna 7 comprises a receiver 8 comprising a resistor.
, Where the current flowing through the antenna 7 is converted to a voltage. That is, the receiver 8 is provided as an input terminal for receiving a reply from the data carrier side, and according to the contents of transmission data from the data carrier side,
It has a function of converting a current change occurring in the antenna 7 into a voltage change. Antenna signal RA from receiver 8
Is input to a reception signal component extraction circuit 10 composed of a band-pass filter circuit (hereinafter referred to as BPF) 11 and an amplification circuit 12, where the component of the subcarrier frequency signal in the antenna signal RA is converted to the reception signal RE to be demodulated. Is extracted as That is, in the BPF 11, the frequency component of the carrier itself is first eliminated, and the envelope component corresponding to the subcarrier frequency signal carried by the transmission modulation on the data carrier side is extracted. Amplification is performed. The received signal RE to be demodulated output from the amplifying circuit 12 is finally a signal which has been saturated-amplified to a logic level, and is input to the data demodulating circuit 13, where the received data is demodulated. Done. As described above, the demodulation circuit 9 on the access device side includes the reception signal component extraction circuit 10 and the data demodulation circuit 13. The data demodulation circuit 13 demodulates the carrier frequency signal AF and the demodulation signal. Demodulation of the received data is performed based on the target received signal RE. The demodulated reception data AR output from the data demodulation circuit 13 is input to the reception data processing circuit 5. The data transmission / reception control circuit 3
The function fulfills a function of controlling an operation sequence related to transmission / reception and forming an operation timing signal.

FIG. 2 is a circuit diagram showing a configuration on the data carrier side of this embodiment. In this circuit system, the VDD side is a reference potential (GND), and an antenna coil 20 for receiving a carrier wave transmitted from the access device side.
Has one end connected to a reference potential. The antenna coil 20 forms a parallel resonance circuit together with the resonance capacitor C1, and further includes a Zener diode D1.
A level shift circuit is constituted by the capacitor C2. The carrier wave received via the antenna coil 20 is rectified by a rectifier circuit 21 comprising a power supply capacitor C3 and a rectifier diode D2 after being subjected to a level shift by the level shift circuit. The DC power supply Vs is generated by a rectification method. The DC power supply Vs is further connected to a constant voltage circuit 23.
, Where it is regulated to a constant voltage power supply Vss of a predetermined voltage. On the other hand, the received carrier is also input to a clock signal generation circuit 22 composed of a linear amplifier circuit via a resistor R2, and the clock signal generation circuit 22 generates an AC signal component of the received carrier. , The clock signal C having the same frequency as the carrier frequency
Generate K. That is, each circuit section in the data carrier is configured to operate by receiving the system clock signal CK as necessary, using the constant voltage power supply Vss as driving power.

In order to increase the communicable distance of the data carrier, it is necessary to increase the carrier wave output from the antenna 7 on the access device side. As a result, the data carrier becomes very In the close state, the amplitude of the carrier wave received on the data carrier side and the constant voltage circuit 2
The voltage of the DC power supply Vs, which is the input of the DC power supply 3, also becomes very large, and there is a danger that the data carrier side circuit such as the constant voltage circuit 23 will be damaged. Zener
The diode D1 is provided as a voltage suppressing means for preventing an overvoltage, and has a series relationship with the antenna coil 20 and the Zener diode D1 for voltage suppression. Thus, the resistor R2 is inserted. The received carrier wave is extracted from the connection between the antenna coil 20 and the resistor R2 as a reception signal RX for demodulating the reception data, and is received by the reception demodulation circuit 2.
4 is input. Therefore, even if the voltage across the rectifier circuit 21 reaches the Zener voltage of the Zener diode D1, a change in the current flowing through the resistor R2 appears as a voltage change across the resistor R2. The voltage is not clamped by the negative node D1, and the result of the amplitude modulation on the access device side appears as a change in the voltage amplitude of the received signal RX. In addition, reception demodulation circuit 2
The demodulated reception data DR is input to the reception data processing circuit 25. As a result, the data transmission / reception control circuit 2
6 is an EEP-ROM based on commands and data from the access device side received via the reception data processing circuit 25.
Storage data for the non-volatile memory 27 such as
Data writing and reading are executed, and the processing result and the read data are controlled so as to be output as transmission data DT to the access device through the transmission data processing circuit 28.

On the other hand, the clock signal CK is also inputted to a frequency dividing circuit 31 constituting the transmission modulation circuit 30, where the frequency is divided into a subcarrier frequency signal FT. That is, the frequency dividing circuit 16 divides the frequency of the clock signal CK to a frequency of 1/16 to form and output a subcarrier frequency signal signal FT for transmission. Sometimes, the transmission data processing circuit 28
The phase modulation circuit 32 is configured to phase-modulate the subcarrier frequency signal FT in accordance with the content of the transmission data DT output from the sub-carrier. Under the control of the data transmission / reception control circuit 26, the preamble signal (preliminary signal) PS is output from the preamble signal forming circuit 29 prior to data transmission.
S is also input to the phase modulation circuit 32 similarly to the transmission data DT, and is configured to phase-modulate the subcarrier frequency signal FT. For phase modulation in these cases, π-BPSK modulation (two-phase modulation between phase 0 and π)
Is optimal, the phase modulation circuit 32 is basically
The transmission data DT or the preamble signal PS and the sub-carrier frequency signal FT can be constituted by an EX-OR circuit which receives the input. In the transmission modulation circuit 30, the transmission modulation signal TX output from the phase modulation circuit 32 is provided to the gate side of the transistor ST provided as transmission modulation switching means, and the transmission modulation signal TX Becomes "L" level, the transistor ST is controlled to the ON state, and the antenna coil 20
Is configured to change the load state (or AC impedance). Here, the antenna coil 20
Although the resistor R1 is used as an element for changing the load state, a capacitor may be used instead of the resistor R1. In the present embodiment, when the data carrier is not in the transmission state, the output signal of the phase modulation circuit 32 is maintained at the “H” level, and the transistor ST is controlled to the OFF state. I have.

Here, a communication operation when the data carrier transmits data and the access device receives the data will be described. FIG. 3 is a circuit diagram showing a configuration example of the reception signal component extraction circuit 10 on the access device side.
FIG. 7 is a waveform diagram of a main part relating to the communication operation from the data carrier side to the access device side.

First, once the transmission to the data carrier is completed, the access device waits for a reply from the data carrier, and then waits for a reply from the data carrier. , The output carrier from the antenna 7 is controlled to a non-modulated state. Here, the data carrier side is in a transmission state, and the transmission data TD from the data processing control circuit 28 (or the preamble signal PS from the preamble signal forming circuit 29) is, for example, as shown in FIG. Looking at the state before and after the change from data “0” to data “1”, the transmission modulation signal TX output from the phase modulation circuit 32 shows that the subcarrier frequency signal FT in the data “0” section. Are phase-modulated to the same phase as that of the data "1", and to a phase different from the subcarrier frequency signal FT by π in the section of data "1". As a result, the load state of the antenna coil 20 also undergoes a periodic change accompanied by a phase change in accordance with the change of the transmission modulation signal TX, and a transmission modulation state occurs due to a transmission operation from the data carrier side. The transmission waveform indicated by the antenna coil signal TA in FIG.
In this embodiment, since the subcarrier frequency signal FT output from the frequency divider 31 is frequency-divided into 1/16 the frequency of the clock signal CK having the same frequency as the carrier wave, Basically, in the state (when there is no phase change), the transistor ST repeats the ON state and the OFF state every eight periods of the carrier wave.
That is, in the section where the transistor ST is in the ON state,
Since the modulation resistor R1 is further connected in parallel to the parallel resonance circuit including the antenna coil 20 and the capacitor C1, the original parallel resonance state is broken and the load on the antenna coil 20 is large. As a result, the signal waveform in the antenna coil 20 has a reduced amplitude as compared with the non-modulated state. In the section where the transistor ST returns to the OFF state, the amplitude of the signal waveform in the antenna coil 20 also returns to the original state in order to return to the original parallel resonance state. As a result, in the above transmission modulation state, the signal waveform in the antenna coil 20 changes every eight periods of the carrier wave.
The state where the amplitude is modulated to be small and the original state are alternately repeated, and when the transmission data changes, a phase change is further added thereto.

Since the amplitude change occurring in the resonance circuit at the time of the above-mentioned modulation requires a certain time width in comparison with the carrier wave period, the sub-carrier frequency signal FT
If the frequency is too close to the original carrier frequency, a sufficient amplitude change cannot be obtained, resulting in insufficient transmission capability to the access device side. On the other hand, in order to reliably and easily perform reception demodulation on the access device side, it is necessary to secure a certain number or more of the above-described alternate repetition of the amplitude change per bit length which is a data unit at the time of transmission. As a result, the frequency signal F for the subcarrier is
If the frequency of T is too low than the original carrier frequency, the bit length becomes large, so that there is a disadvantage that the communication time becomes long. In consideration of these, the frequency of the subcarrier frequency signal FT is preferably in the range of 1/8 to 1/16 with respect to the carrier frequency (that is, the frequency of the clock signal CK). The bit length of the data at the time of transmission to the device side is 4 times the period of the subcarrier frequency signal FT.
A range of 2 to 16 times is appropriate.

On the other hand, as a result of the transmission modulation operation on the data carrier side, the antenna 7 on the access device side
A change also occurs in the waveform of the current flowing through. The antenna signal RA in FIG. 4 is a waveform diagram showing a signal received by the receiver 8 when the access device side is in a receiving state, and is affected by transmission modulation on the data carrier side. Also, a periodic amplitude change corresponding to the subcarrier frequency signal FT appears. In other words, the frequency component of the received signal at this stage is the frequency component of the carrier itself, and the envelope ra has a small amplitude change but a periodic change corresponding to the subcarrier frequency signal FT. I'm riding. As shown in FIG. 3, the antenna signal RA at the time of reception by the receiver 8 is a passive first BPF 11a configured to pass through the frequency band of the subcarrier frequency signal FT, and an active type 2nd BPF11b
, Where the antenna signal R
The frequency component of the carrier in A is removed, and the frequency band component of the subcarrier frequency signal FT, which is the AC component of the envelope ra, is extracted. The signal is output as the target reception signal RE. The extraction of the envelope component is not limited to the BPF, but may have a low-pass filter.

FIG. 5 is a circuit diagram showing a configuration of the data demodulation circuit 13 of the access device shown in FIG.
FIG. 7 to FIG. 7 are waveform charts showing signals of the main part. Here, the reception demodulation operation on the access device side will be described.

The carrier frequency signal FA from the oscillating circuit 1 is input to a data demodulation signal forming circuit 14 of a data demodulation circuit 13, where the four types of data demodulation signals F1, F2, F3 and F4 are output. The frequency is divided by 1/16 into the frequency signal.
In the embodiment shown in FIG. 5, the data demodulation signal forming circuit 14 includes eight toggle flip-flop circuits (hereinafter, referred to as FF circuits) 40 to 47, and outputs the data demodulated frequency-divided signal. F1, F2, F3, F4 are:
As shown in FIG. 6, each of the output signals AF
The second stage FF circuit 41 which divides the frequency of the output signal AF2 of the first stage FF circuit 40 and the third stage F
Since the F circuits 42 and 43 and the fourth-stage FF circuits 44 to 47 are connected as shown in the figure, the signals are shifted in phase by π / 4. The data demodulated frequency-divided signal F
1 to F4 are input to the phase determination signal selection circuit 15,
Here, one of the signals is selected as the phase determination target signal FX and is input to the multiplication circuit 16. In the initial state, any of the four frequency-divided signals F1 to F4 for data demodulation may be selected as the phase determination target signal FX in the initial state. Further, the multiplying circuit 16 has a function of substantially mixing the demodulation target reception signal RE and the phase determination target signal FX. However, since the reception signal RE is also saturated and amplified to be a digital signal, An EX-OR circuit can be used as it is as the multiplication circuit 16 in this case.

Here, the data carrier device side is configured to perform phase modulation by the preamble signal PS prior to actual data transmission as described above.
This is because when the access device performs reception demodulation, one of the four data demodulated frequency-divided signals F1 to F4 having a preferable phase relationship with the reception signal RE to be demodulated is phase-shifted. It relates to a procedure for selecting a reference signal for detection.

The received signal RE to be demodulated in FIG.
It shows a signal waveform when the phase modulation is performed by the preamble signal PS on the data carrier side and is received on the access device side. In the illustrated section, the preamble signal PS is a section in which the data “0” is included. The state before and after the transition to the section of data “1” from is shown.
In both the sections, the reception signal RE holds the data “0”.
(Or -π) with the change from “1” to data “1”
Only the phase is shifted. In this state, if it is assumed that the phase determination signal selection circuit 15 has selected the data demodulation frequency-divided signal F1 as the phase determination target signal FX, the phase determination target signal FX and the reception signal RE are ,
Since the signals are mixed by the multiplication circuit 16 composed of the EX-OR circuit, the output signal RM from the multiplication circuit 16 at this time is, as shown in FIG.
In the section where S is data "0", it is almost at "L" level, and in the section where preamble signal PS is data "1", it is almost at "H" level. Since the output from the multiplication circuit 16 is input to the filter circuit 17 configured to extract a frequency component substantially corresponding to the data communication speed, the output signal RF from the filter circuit 17 at this time is output. Changes from a substantially ground (hereinafter referred to as GND) level state to a substantially VDD level state, as shown in FIG. In the present embodiment, the filter circuit 17 has a configuration in which CR-type low-pass filters are connected in two stages. If a frequency component corresponding to the data communication rate (data change rate) of the preamble signal PS can be substantially extracted by cutting, a CR-type band-pass filter or a loop filter can be used. is there.

Here, the output of the filter circuit 17 is input to the Schmitt trigger type inverter 48 constituting the phase determination circuit 18. However, as described above, the output signal RF of the filter circuit 17 is substantially at the GND level. From to approximately the VDD level means that there is an input change exceeding the hysteresis width HB of the Schmitt trigger type inverter 48. As a result, the logic level of the output of the inverter 48 is inverted from the “1” level to the “0” level, so that the outputs of the two toggle FF circuits 49 and 50 constituting the phase determination circuit 18 are changed. One of the output signals becomes “H”, and one phase determination signal switching signal CS is output from the output side of the single shot circuit 51. That is, here, the phase determination circuit 18 determines that the data demodulated frequency-divided signal F1 is selected as the phase determination target signal FX as inappropriate phase (the reason will be described later).
As a result, as a result, the phase selection signal selection circuit 1
In response to the switching signal CS, the data demodulated frequency signal F1 is replaced with the data demodulated frequency signal F1.
2 is selected as the phase determination target signal FX.

Since the switching signal CS is also input to the reset terminals of the FF circuits 49 and 50, when the switching of the phase determination target signal FX is completed as described above, the FF circuit 49 is switched. , 50 have returned to the reset state. That is, when the logic level of the output of the Schmitt trigger type inverter 48 is again inverted next, the two toggle type FF circuits 4
One of the output sides 9 and 50 is at the “H” level, and the output side of the single shot circuit 51 has returned to a state where one phase determination signal switching signal CS can be output. Further, the phase determination signal selection circuit 15 counts, for example, the number of inputs of the switching signal CS, and according to the count value, the data demodulation frequency division signal F1.
F4 can be configured by a multiplexer type selector circuit that sequentially switches and selects any one of F4 to F4.

Next, FIG. 7 shows each signal when the data demodulated frequency-divided signal F2 is selected as the phase determination target signal DX. Here, following the state of FIG. The state before and after the preamble signal PS changes from the section of data “1” to the section of data “0” is shown. Therefore, the reception signal RE changes with the change of the data “1” to the data “0”. Thus, the phase is shifted by -π (or π). At this time, as shown in FIG. 7, in the section where the preamble signal PS is data "1", the output signal RM of the multiplication circuit 16 has a slightly longer period of "1" level (slightly larger duty), and Output signal RF from circuit 17
Is slightly closer to the VDD level. When the preamble signal PS is in a data “0” section, the multiplication circuit 1
The output signal RM of No. 6 has a slightly large period of “0” level (slightly small duty), and therefore the filter circuit 1
The output signal RF from 7 is slightly closer to the GND level. As a result, the output signal RF from the filter circuit 17 is also transmitted to the Schmitt trigger type inverter 48.
, The change slightly exceeds the input hysteresis width HB, and the logic level of the output of the inverter 48 is also inverted. Accordingly, the output signal of one of the two toggle FF circuits 49 and 50 constituting the phase determination circuit 18 becomes “H”, and the output of the single shot circuit 51 outputs one phase determination signal. Signal switching signal CS
Is output. That is, even in a state where the data demodulated frequency-divided signal F2 is selected as the phase determination target signal FX, the phase determination circuit 18 determines that the phase of the phase determination target signal is improper. In response to the switching signal CS, the signal selection circuit 15 selects the data demodulation frequency-divided signal F3 as the phase determination target signal FX.

FIG. 8 shows signals when the data demodulated frequency-divided signal F3 is selected as the phase determination target signal FX. Here, following the above-described state of FIG. The state before and after the PS changes from the data “0” section to the data “1” section is shown. Therefore, the received signal RE has a phase of π (or −π) according to the data change. Is shifting. At this time, as shown in the figure, the output signal RM of the multiplication circuit 16 is output in both the section in which the preamble signal PS is data “1” and the section in which the preamble signal PS is data “0”.
Is in a state where the period of the “1” level and the period of the “0” level are almost equal (duty is almost １ ／). As a result, the output signal RF of the filter circuit 16 becomes almost VDD /
The voltage level is about 2. Therefore, in this case, since the output signal RF of the filter circuit 17 does not exceed the input hysteresis width HB of the Schmitt trigger type inverter 48, both the output sides of the FF circuits 49 and 50 are set to the “H” level. From the output side of the single shot circuit 51.
Is not output. That is, this time, the phase determination circuit 18 determines that the phase of the phase determination target signal FX is appropriate, and further continues the preamble signal PS between the data “1” and the data “0” from this state. Even if it changes, the above state basically does not change, and among the plurality of types of frequency-divided signals for data demodulation F1 to F4,
The data demodulated frequency-divided signal F3 is maintained in the selected state. When the preamble signal PS ends and the actual data reception starts, the reception of the data demodulated signal F3 as the phase determination target signal FX is performed as described above. Data demodulation will be performed.

Here, in the present embodiment, the phase detection circuit 19 is composed of a D-FF circuit that performs phase detection by a so-called direct conversion method, and the data input side of the D-FF circuit is: The receiving signal RE to be demodulated is input, and the clock input side includes a plurality of types of frequency-divided signals for data demodulation F1 to F4.
The same signal (signal having the same phase) as the signal selected as the phase determination target signal FX is input as the phase detection reference signal DX. In such a direct conversion system, the reception signal RE which is a data input is synchronized with the falling (or rising) of the phase detection reference signal DX which is a clock input of the D-FF circuit.
By sampling the serial reception data A
It is configured to demodulate R directly. Therefore, in an actual receiving operation, the received signal has a waveform distortion or a rounded waveform,
Taking into account the fluctuation of the duty and the like, it is clear that the above sampling timing is more suitable as it is closer to the midpoint between the rise and fall of the reception signal RE. That is, the phase detection reference signal DX is π / 2 (or -π
/ 2) is the most suitable state. For this reason, in this embodiment,
While the preamble signal PS is being given, one of a plurality of types of frequency-divided signals F1 to F4 for data demodulation, the phase of which is shifted by π / 2 (or -π / 2) with respect to the reception signal RE. Is first searched for as a phase determination target signal FX, and the same signal (signal having the same phase) as the phase determination target signal FX is used as a phase detection reference signal DX so that actual reception demodulation is performed. It is configured.

As described above, in the data carrier of the present embodiment, when determining the phase relationship between the phase determination target signal FX and the demodulation target reception signal RE, the two signals are multiplied by the multiplication circuit 16. Mixing, and checking whether or not the result of cutting high-frequency components higher than the frequency of the data communication carrier by the filter circuit 17 is at a voltage level near VDD / 2, thereby obtaining π / 2
(Or -π / 2). That is, the filter circuit 1
7 is within the input hysteresis width HB of the Schmitt trigger type inverter 48 (in other words, VDD
/ 2), the phase of the phase determination target signal FX is π /
2 (or −π / 2), and if it is determined that it is sufficiently close to π / 2 (or −π / 2), the same signal (same as the phase determination target signal FX) (Phase signal) is used as the phase detection reference signal DX in the direct conversion method. The reason that the preamble signal PS has both a section of phase 0 (section of bit data “0”) and a section of phase π (section of bit data “1”) in π-BPSK modulation is as follows. The target signal FX for phase determination is the received signal R
In a state where there is no phase relationship close to π / 2 (or −π / 2) with respect to E, if there is a change between the section of phase 0 and the section of phase π in the phase modulation, Schmidt
Although the logic level of the output of the trigger type inverter 48 is inverted, the above-described inversion of the logic level does not occur when the phase determination target signal FX has a phase relationship close to π / 2 with respect to the received signal RE. This is because the phase can be determined very easily despite a very simple circuit configuration. On the data carrier side,
If the transmission data is configured to be once converted into a so-called biphase signal and then subjected to π-BPSK modulation,
It is apparent that the preamble signal PS may be constituted by only data "1" which is an idling signal in start-stop synchronous communication, for example. That is, in this case, the preamble signal PS automatically includes both the phase 0 section and the phase π section in the phase modulation regardless of the data content. This can be applied to a configuration such as the phase determination circuit 18. If the data demodulation circuit 13 on the access device side is constituted only by a logic circuit, a capacitor and a resistor as shown in FIG. 5, a so-called standard logic IC can be used, or a low power consumption C-MOS type IC can be used. Since it can be easily built in, an access device with a simpler configuration, lower cost, or lower current consumption can be realized.

Which of the data demodulated frequency-divided signals F1 to F4 is suitable as the phase determination target signal or the phase detection reference signal depends on the fact that the data carrier approaches the access device and the power supply on the data carrier side is turned on. The number of times the selection signal is switched (how many phase determination signal switching signals CS are generated) and the signal of the appropriate phase is changed because of the randomness caused by the timing and the direction of the back / front of the data carrier with respect to the access device. Is not known in advance, and therefore, as the above-mentioned preamble signal PS, the change between the phase 0 (data “0”) and the phase π (data “1”) in the phase modulation is performed at least four times. It is desirable to include. In actual reception demodulation, the reception signal RE and the phase detection reference signal D
In addition to the phase problem with X, in the case of π-BPSK modulation, the receiving side determines which state is assigned to data “1” and which state is assigned to “0” separately. There is also the problem of having to decide. That is, in the case of π modulation, the state in which the phase is advanced by π and the state in which the phase is delayed by π are the same in terms of waveform, and the relationship between the state of data “1” and the state of “0” is also relative. From the viewpoint of the receiving side, it is possible to distinguish between data “1” and “0”, but any state is data “1”,
This means that data "0" cannot be determined without depending on the promise of the transmitting side. However, this problem is caused, for example, when the data carrier side has a preamble signal P
After completion of S, the problem can be easily solved by a method of interposing a stop bit of 10 bits or more (idle state of data "1") at the forefront of actual data transmission (in this case, If the same demodulated data continues over 10 bits or more, the state may be assigned to data "1". Therefore, a detailed description is omitted. As for the phase detection circuit 19, a low-pass filter and an amplification circuit for saturation amplification are connected to the output side of the D-FF circuit, and the serial reception data A
You may comprise so that R may be taken out.

FIG. 9 is a circuit diagram showing a configuration of the data demodulation circuit 13 on the access device side according to the second embodiment, and FIG. 10 is a waveform diagram showing signals of main parts thereof.
However, in the present embodiment, the data demodulation signal formation circuit 14, the phase determination signal selection circuit 15, the multiplication circuit 16,
The filter circuit 17 and the phase determination circuit 18 have the same basic configuration and operation as those of the embodiment shown in FIG. The phase detection circuit 19 includes a multiplication circuit 53, a filter circuit 54, and an amplification circuit 55.
3. The filter circuit 54 is exactly the same as the multiplication circuit 16 and the filter circuit 17, respectively. In the case of such a demodulation method, as the phase of the phase detection reference signal DX with respect to the reception signal RE becomes closer to 0 or π (or -π), the reception signal RE is demodulated with higher efficiency, and the demodulation condition is changed. Obviously, it will be preferred. On the other hand, in the phase determination signal selection circuit 15, as in the case of FIG.
Since the phase determination signal FX having a phase difference close to 2 (or -π / 2) is configured to be selected, the data demodulated frequency-divided signals F1 to F4 are eventually selected. A signal having a phase different from the phase determination signal FX by π / 2 (or -π / 2) is referred to as a phase detection reference signal D.
This means that X should be supplied to the multiplication circuit 53 of the phase detection circuit 19.

FIG. 11 is a circuit diagram showing a configuration of the data demodulation circuit 13 on the access device side according to the third embodiment, and FIG. 12 is a waveform diagram showing signals of main parts thereof. However, the phase determination signal selection circuit 15, the multiplication circuit 16 and the filter circuit 17 are the same as those in the embodiment shown in FIG. In the access device side, since the restrictions on the cost and size of the circuit components are not as large as those on the data carrier side, analog discrete circuit components such as an OP amplifier can be employed. In the embodiment, the phase determination circuit 18 includes a high-speed comparator 61, an AND circuit 62, a single shot circuit 63, and a timer circuit 64. On the data carrier side, as described above, the preamble signal PS is output prior to actual data transmission.
The preamble signal PS in this case is constituted by an idling output state (a state in which a stop bit of data “1” continues during an idling period in start-stop synchronous data communication).

First, the data demodulation signal forming circuit 14 forms an eight-phase data demodulation divided signal composed of F1 to F8 by dividing the carrier frequency signal AF by 1/16. That is, the data demodulation signal forming circuit 1
4 is a signal having four basic phases F1 to F4,
These inverted signals F5 to F8 are also supplied to the phase determination signal selection circuit 18. Further, in the phase determination signal selection circuit 15, one of these signals is selected as the phase determination target signal FX, and the multiplication circuit 1
6 is mixed with the reception signal RE to be demodulated, and the output signal RM from the multiplication circuit 16 is filtered by the filter circuit 1
7 is input.

The output signal RF of the filter circuit 17 is given to the minus input side of a comparator 61 constituting the phase determination circuit 19, and the output of the timer circuit 64 is normally set to "H" level. ing. Therefore, when the output signal RF of the filter circuit 17 is lower than the comparison reference voltage level VRF, the output side of the comparator 61 and the output side of the AND circuit 62 become “H” level. Is output. As a result,
The phase determination signal selection circuit 15 selects the next-order data demodulation frequency-divided signal as a new phase determination target signal FX. The timer circuit 64 is provided with the switching signal CS
In response to the switching signal CS, the output signal of the AND circuit 62 is output from the switching signal CS over a predetermined period regardless of the output state of the comparator 61. Are held at the “L” level. Here, in a state where the new phase determination target signal FX is selected, when the reset signal from the timer circuit 64 is released, the output signal RF of the filter circuit 17 is still lower than the comparison reference voltage level VRF. In this case, the same operation as above is repeated again.

In this manner, the operation of selecting the phase determination target signal FX is repeated until the voltage level of the output signal RF of the filter circuit 17 becomes higher than the comparison reference voltage level VRF. When the state is reached, in order to actually demodulate the received data, the selection operation of the phase determination signal selection circuit 15 is locked, and the selection operation ends. Note that the output signal R of the filter circuit 17 is
It is clear that the voltage level of F increases as the phase of the phase determination target signal FX with respect to the received signal RE approaches π (or −π).

Here, in the present embodiment, the multiplying circuit 16 and the filter circuit 17 also constitute a basic part of the phase detecting circuit 19. That is, the output signal RF of the filter circuit 17 is output as the serial reception data AR via the amplifier circuit 60, but the amplifier circuit 60 simply saturates and amplifies the output signal RF of the filter circuit 17 to a logic level. Since only the output signal RF is output from the filter circuit 17, the output signal RF itself may be considered as demodulated data. Therefore, in this case, as in the case of FIG. 5, the phase determination target signal FX and the phase detection reference signal DX are, of course, the same signal (the same phase signal).
It turns out that. Also, in the case of such a demodulation method, as the phase of the phase detection reference signal DX with respect to the reception signal RE becomes closer to 0 or π (or −π), as in the case of FIG. Obviously, the demodulation is performed with high efficiency, and the demodulation conditions become favorable. In other words, as the phase of the phase determination target signal FX with respect to the reception signal RE becomes closer to 0 or π (or −π), that is, as the voltage level of the output signal RF of the filter circuit 17 becomes higher, the more suitable signal selection state. It can be said. FIG. 12 shows the most ideal state as
The state of each signal when the phase difference between the two signals is almost π is shown.

In this embodiment, the use of the comparator 61 allows the above phase relationship to be π (or the same for -π) during the preamble signal PS period consisting of the above-mentioned continuous stop bit signal by idling. , So that it reaches the selection state where the demodulated data becomes “1”, so that the selection of the phase of the signal and the difference between “0” and “1” of the demodulated data eventually result. Assignment will be performed simultaneously. That is, in this case, the pre-angle signal PS
In the section corresponding to, based on the promise to the transmitting side that the demodulated data should be "1", the state close to phase 0, which should be the same as it should be, is discarded. Only the state close to π (or -π) is selected, and as a result, the demodulated serial reception data AR
Is assigned to the state where is "1".

In the above embodiment, the multiplication circuits 16 and 53 are constituted by EX-OR circuits, but may be constituted by using transmission gates and the like. Further, the data demodulation signal forming circuit 14
With regard to the above, in order to substantially form a data demodulation frequency-divided signal having a plurality of types of phases, for example, the data demodulation signal forming circuit and the phase determination signal connection circuit are organically coupled, and a plurality of types of Instead of forming the frequency-divided signal for data demodulation, in response to the signal switching signal for phase determination,
There is also a configuration in which the connection state between the toggle-type FF circuits for frequency division is logically switched by a selector or the like, thereby forming a frequency-divided signal for data demodulation of substantially plural types of phases. It is possible. Further, based on the frequency signal of the power carrier, a frequency-divided signal of one kind of phase is formed in advance, and this is divided into a plurality of delay circuits having different time constants and a plurality of delay circuits having different delay time widths. By passing through a logic delay circuit, it is possible to form a frequency-divided signal for data demodulation of substantially plural kinds of phases, or to form a phase-decision signal instead of forming plural kinds of frequency-divided signals for data demodulation in advance. Signal switching signal
By switching the constants of the delay circuits and the connection states of the logic delay circuits in a logical manner using a selector or the like, it is possible to form a frequency-divided signal for data demodulation of substantially multiple types of phases. It is possible. That is, it is clear that any of the above is within the scope of the configuration that can be employed in practicing the present invention.

In the above description, with respect to the waveform diagrams of the signals shown in FIGS. 4, 6 to 8, 10 and 12, the serial transmission / reception data is set between "0" and "1". When changing, the received signal waveform is also shown to follow and change in a consistent manner, but this is based on modeling for explanation, and as in the above-described embodiment, Sending
When the receiving antenna forms a resonance circuit,
Actually, immediately after the data change, the waveform is disturbed by the influence of the resonance phenomenon. However, in serial communication, data acquisition into the reception data processing circuit
Since it is performed near the midpoint of the bit period width of the data, both ends of the bit period width at which the above-mentioned waveform disturbance occurs (change portion of data) have no meaning, and Is not a communication problem. However, since the above-mentioned disturbance of the waveform slightly affects the output signal from the multiplication circuit, in the above-described embodiment, the filter circuit 17 is connected to the low-pass filter 2.
By adopting a stage connection structure, the influence is more reliably suppressed. In other words, if the output signal from the filter circuit is disturbed, the input hysteresis width of the Schmitt trigger circuit is relatively narrow due to the disturbance, and the output of the Schmitt trigger circuit is not required However, since this disturbance occurs only at both ends of the bit period width and is composed of relatively high frequency components, for example, as described above, the filter circuit is connected to the low-pass filter 2. This can be easily solved by taking into consideration the configuration of the step connection.

[0036]

As described above, in the present invention,
The signal to be captured at the time of reception on the access device side may be a component of the same frequency as the carrier wave transmitted from the access device itself, and the frequency component of the subcarrier carried by the transmission modulation on the data carrier side is used as a reception signal. In particular, even when only one antenna is provided for both power transmission and reception and data transmission / reception, and the antenna constitutes a resonance circuit, the antenna is configured to extract. Thus, efficient reception can be performed without difficulty in the frequency band. From reception to demodulation, two frequency components, the carrier frequency and the subcarrier frequency, are involved. Except for noise having both of these two frequency components at the same time, the data is transmitted from the antenna to the data demodulation circuit. Since the communication is interrupted without being taken in, communication with excellent noise resistance becomes possible. Further, in the present invention, the demodulation of received data also has a completely accurate frequency without providing a Costas loop using a PLL circuit or the like which is likely to be unstable in operation with a complicated configuration as in the related art. In addition, it is possible to obtain a phase detection reference signal having a suitable phase. That is, on the data carrier side, the frequency signal of the received power carrier is divided by 1 / N to form a subcarrier frequency signal for data transmission modulation, whereas the access device side transmits the signal. Since the frequency signal of the power carrier is divided by 1 / N to form a phase detection reference signal, the frequency of the phase detection reference signal is completely accurate in performing reception demodulation. . Also, the phase of the phase detection reference signal can be selected in a stable state with a simple circuit configuration based on the present invention, so that the reliability of communication can be further improved at low cost. .

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a circuit configuration of an access device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration on a data carrier side according to the embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of a reception signal component extraction circuit on the access device side according to the embodiment of the present invention.

FIG. 4 is a waveform chart showing signals of main parts according to the embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a data demodulation circuit on the access device side according to the embodiment of the present invention.

FIG. 6 is a waveform diagram showing signals of main parts according to the embodiment of the present invention.

FIG. 7 is a waveform chart showing signals of main parts according to the embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a reception data demodulation circuit on the access device side according to the embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating a configuration of a data demodulation circuit on an access device side according to a second embodiment of the present invention.

FIG. 10 is a waveform chart showing signals of main parts according to the second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a data demodulation circuit on an access device side according to a third embodiment of the present invention.

FIG. 12 is a waveform chart showing signals of main parts according to the third embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 2 Modulation circuit 7 Antenna 9 Demodulation circuit 10 Received signal component extraction circuit 13 Data demodulation circuit 14 Data demodulation signal formation circuit 15 Phase determination signal selection circuit 16 Multiplication circuit 17 Filter circuit 18 Phase determination circuit 19 Phase detection circuit 20 Antenna coil 21 Rectifier circuit 22 Clock signal generation circuit 24 Reception demodulation circuit 29 Preamble signal formation circuit 30 Transmission modulation circuit 31 Divider circuit 32 Phase modulation circuit

Claims (9)

[Claims] 1. A data carrier system comprising: a data carrier provided with a nonvolatile semiconductor memory as data storage means; and an access device for accessing the data carrier. The apparatus receives an antenna for transmitting a predetermined carrier, modulating means for modulating the carrier according to serial transmission data at the time of data transmission, and a transmission signal transmitted from the data carrier. And a demodulating means for demodulating received data. The data carrier is provided by rectifying an antenna coil for receiving the carrier and a carrier received via the antenna coil. Rectifying means for generating a DC power supply serving as power for driving the data carrier itself, and generating a clock signal having the same frequency as the carrier frequency based on the received carrier wave. Clock signal generating circuit, receiving demodulation means for receiving the received carrier wave, and demodulating serial transmission data from the access device, and transmission modulation means for returning data to the access device. In the two-way communication type data carrier system having the following, the transmission modulation means on the data carrier side divides the frequency of the clock signal by 1 / N (N is an integer) to obtain a subcarrier signal. A frequency dividing circuit for forming a frequency signal; a phase modulating circuit for phase modulating the subcarrier frequency signal in accordance with the content of serial transmission data transmitted to the access device; Switching means for changing the load of the antenna coil, and the demodulation means on the access device side converts the subcarrier frequency signal component from the signal in the antenna. It comprises a received signal component extracting means for extracting, and data demodulating means for receiving the output signal from the received signal component extracting means and demodulating received data, wherein the data demodulating means comprises a frequency of the power carrier wave. Data demodulation signal forming means for substantially forming a plurality of types of divided data demodulation signals having different phases by dividing the signal by 1 / N; Phase determining signal selecting means for selecting one as a phase determining target signal; a multiplying circuit for substantially mixing the phase determining target signal with an output signal from the received signal component extracting means; A filter circuit for extracting a frequency band component corresponding to the data communication speed from the output of the, the appropriateness of the phase of the phase determination target signal is determined by the output from the filter circuit,
A phase determination signal switching signal for causing the phase determination signal selection means to reselect the data demodulation frequency-divided signal of another phase as a new phase determination target signal when it is determined that the phase is inappropriate; Output signal from the received signal component extraction means, using the frequency-divided signal for data demodulation having a predetermined phase relationship with respect to the target signal for phase determination as a phase detection reference signal. A data carrier system comprising a phase detection means for demodulating received data by phase detection. 2. The phase modulation by the phase modulation circuit on the data carrier side is π-BPSK modulation, and the data carrier side transmits a phase 0 section and a phase π before data transmission.
A preamble signal forming means for supplying a preamble signal including both of the sections to the phase modulation circuit,
The phase judging means on the access device side includes a Schmitt trigger circuit for receiving an output from the filter circuit, and when detecting an inversion of the logic level of the output from the Schmitt trigger circuit, forms a phase judgment signal switching signal. 2. The data carrier system according to claim 1, wherein the data carrier system is configured as follows. 3. The phase modulation by the phase modulation circuit on the data carrier side is π-BPSK modulation, and the phase detection means on the access device side comprises a D-type flip-flop (D-FF) circuit. The output signal from the component extraction means is input to the data input side of the D-FF circuit, and among a plurality of types of frequency-divided signals for data demodulation,
2. The data carrier system according to claim 1, wherein a signal having the same phase as the phase determination target signal is input as a phase detection reference signal to a clock input side of the D-FF circuit. 4. The phase modulation by the transmission modulation circuit on the data carrier side is π-BPSK modulation, and the phase detection means on the access device side determines a phase determination target among a plurality of types of frequency-divided signals for data demodulation. 2. The data carrier system according to claim 1, further comprising a multiplying circuit for mixing a signal having a phase different from that of the signal by π as a phase detection reference signal with an output signal from the received signal component extracting means. 5. The phase modulation by the phase modulation circuit on the data carrier side is π-BPSK modulation, and the data carrier side supplies a preamble signal consisting of idle transmission data to the phase modulation circuit prior to data transmission. In addition to having the signal forming means, the access device side phase determining means includes a comparator receiving an output from the filter circuit, and is configured to form a phase determining signal switching signal according to the output from the comparator. The data carrier system according to claim 1, characterized in that: 6. The data demodulation signal forming means divides the frequency signal of the power carrier wave to form a plurality of types of data demodulation frequency-division signals having phases shifted by π / 4 or π / 8. 2. The data carrier system according to claim 1, further comprising means. 7. The access device according to claim 1, wherein said modulating means comprises means for modulating the amplitude of said carrier wave in accordance with transmission data to a data carrier side. A data carrier system as described. 8. On the access device side, the received signal component extracting means includes a filter circuit for extracting an envelope component corresponding to the subcarrier frequency signal in the antenna signal. The data carrier system according to claim 1, wherein 9. On the access device side, the reception signal component extraction means includes an amplification circuit for saturating and amplifying the AC component of the envelope component extracted by the filter circuit to a logic level. 9. The data carrier system according to claim 8, wherein: