JP3961215B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor memory device that performs non-contact data transmission and reception with a nonvolatile memory.
[0002]
[Prior art]
In recent years, the market of the RFID field for transmitting and receiving data without contact has been rapidly expanding. Along with this, in the specification of LSI, standardization for market expansion is rapidly progressing, such as proximity type ISO14443 with a communication distance of about 10 cm and proximity type ISO15693 with a communication distance of about 70 cm. The future market demand is to develop a cheaper contactless data communication LSI with a longer communication distance. The power consumption of the LSI greatly affects the length of the communication distance, and the communication distance can be extended as the power consumption decreases.
[0003]
The configuration and operation of a conventional contactless data transmission / reception system equipped with a non-volatile memory will be described below. FIG. 6 shows a circuit configuration diagram of a conventional example. This system includes a reader / writer 12 to which an antenna 13 including a coil 10 and a capacitor 11 is connected, and an LSI 9 to which an antenna 1 including a coil 7 and a capacitor 8 is connected. The LSI 9 includes a rectifier circuit 2 that extracts a DC power source from a signal received by the antenna 1, a demodulation circuit 3 that extracts data and a clock from the signal received by the antenna 1, and a modulation circuit 4 for transmitting data via the antenna 1. And a control circuit 5 that controls the LSI in response to data (DATA) and a clock (CLK) generated by the demodulation circuit 3, and a nonvolatile memory 6 for storing the DATA generated by the demodulation circuit 3.
[0004]
FIG. 7 shows a timing chart in a basic non-contact data transmission / reception LSI. When a signal VI generated by superimposing a carrier wave and a signal is transmitted from the reader / writer 12 of FIG. 6 via the antenna 13, a magnetic flux 14 is generated around the antenna 13. The antenna 1 receives the magnetic flux 14 to transmit / receive data and supply power by electromagnetic induction. VA is a voltage generated in the antenna 1. Data transmission / reception is generally performed by amplitude modulation. As shown in FIG. 7, the potential of the signal VI is Vm when there is no modulation and Vn when there is modulation. Therefore, the potential of the generated VA is also different, and in a normal state, it is Vm1 when there is no modulation and Vn1 when there is modulation. The potential of VA generated in the antenna 1 also changes depending on the distance between the antenna 13 and the antenna 1, the size and shape of each antenna, or the magnitude of the voltage VI applied to the antenna 13. The longer the distance (communication distance) between the antenna 13 and the antenna 1, the smaller the potential of VA with respect to the same VI potential.
[0005]
The power supply VDD of the LSI is generated by rectifying VA by the rectifier circuit 2. Since VDD is generated along the envelope of VA, when VA is not modulated, the potential of V1 is generated as VDD, and when VA is modulated, the potential of V2 is generated as VDD. . The relationship between V1 and V2 is V1> V2. The VA is also input to the demodulation circuit 3, and data (DATA) and a clock (CLK) are generated. Data (DATA) is generated by detecting the rise / fall of VDD.
[0006]
[Problems to be solved by the invention]
FIG. 8 shows a timing chart when the nonvolatile memory 6 is operated at the time of data reception. A signal for starting the nonvolatile memory 6 is ACT, and when the nonvolatile memory 6 is operated, a large amount of power is instantaneously consumed. Here, the case where ACT occurs when the VA signal is modulated will be described. Since the VA signal is modulated as the potential of the LSI power supply VDD, first, a voltage V2 smaller than the voltage V1 when the VA is not modulated is generated. Here, when ACT occurs, the voltage drops from the voltage V2 to the voltage V3 due to power consumption when the nonvolatile memory 6 operates. Therefore, the lower limit voltage at which the LSI operates is the voltage V3, which limits the communication distance.
[0007]
In addition, when the ACT signal is generated when the VA signal is not modulated and the nonvolatile memory 6 is operated, the potential of VDD changes as follows. That is, the voltage V1 at the time of non-modulation first drops to the potential V4 due to the power consumption of the nonvolatile memory 6, then rises to the potential V5 that matches the waveform of VA, and then transitions to the potential V2. For this reason, the demodulation circuit 3 may not be able to correctly restore the data (DATA). That is, normally, the demodulating circuit 3 detects the change from the potential V1 to the potential V2 and generates data (DATA). In the above case, since the VDD transitions from the potential V1 → V4 → V5 → V2, It may cause malfunction due to the influence.
[0008]
The present invention solves the above-described problems, makes it possible to increase the communication distance, and to restore a signal more stably, and to provide a semiconductor memory device that transmits and receives data without contact The purpose is to provide.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor memory device of the present invention has a built-in nonvolatile memory for storing data, and transmits / receives data to / from a reader / writer in a contactless manner using an amplitude modulation communication signal. there line, a semiconductor memory device having a means for communicating signals to start a non-volatile memory in a period of unmodulated comprises means for detecting a rising edge of the communication data from the reader-writer transmitted by amplitude modulation The built-in nonvolatile memory is activated using the signal that detects the rising edge. According to this configuration, the nonvolatile memory is started when the power supply VDD is at a high potential, and the influence of the power consumption of the nonvolatile memory is avoided. As a result, it is possible to increase the communication distance and restore the signal more stably.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 shows a configuration of a contactless data transmission / reception circuit according to the first embodiment of the present invention. This circuit includes an antenna 101 including a coil 107 and a capacitor 108, and an LSI 110. The LSI 110 includes a rectifier circuit 102, a demodulation circuit 103, a modulation circuit 104, a control circuit 105, an edge detection circuit 109, and a nonvolatile memory 106.
[0014]
The rectifier circuit 102 extracts a DC power source from the signal received by the antenna 101. The demodulation circuit 103 extracts data and a clock from the signal received by the antenna 101. The modulation circuit 104 transmits data via the antenna 101. The control circuit 105 receives the data (DATA) and the clock (CLK) output from the demodulation circuit and controls the LSI 110. The edge detection circuit 109 detects a rising edge of data (DATA). The nonvolatile memory 106 is used for storing DATA generated in the demodulation circuit 103.
[0015]
FIG. 2 is a configuration example of the edge detection circuit 109. It is composed of D flip-flops (D-FF) 120 and 121, an inverter 122, and an AND 123. Data (DATA) is input to the D input of the D-FF 120, and a clock (CLK) is input to the CK input. The Q output of the D-FF 120 is input to the inverter 122 and the AND 123. The output of the inverter 122 is input to the D input of the D-FF 121. A clock (CLK) is input to the CK input of the D-FF 121. The Q output of the D-FF 121 is input to the AND 123. Further, the output PREACT of the control circuit 105 is input to the AND 123.
[0016]
FIG. 3 shows a timing chart in the circuit of FIG. The VA potential generated via the antenna 101 varies depending on the presence / absence of amplitude modulation of the signal. The VA potential is input to the demodulation circuit 103, and a clock (CLK) and data (DATA) are generated. The VA potential is input to the rectifier circuit 102 and generates the power supply voltage VDD of the LSI 110. Data (DATA) is generated by detecting the rising / falling edge of VDD.
[0017]
When data (DATA) and a clock are input to the edge detection circuit 109, the output Q1 of the D-FF 120 is obtained by delaying the data (DATA) by one clock. Further, Q1 is inverted by the inverter 122, and an output Q2 is generated by delaying the signal by one clock in the D-FF 121. The Q1, Q2, and PREACT are decoded by the AND 123 to generate an ACT signal for starting the nonvolatile memory 106. That is, by detecting the rising edge of the data (DATA), the ACT signal can be generated at a timing when the signal is not modulated, that is, when the power supply VDD of the LSI 110 is at the high potential V1. Since the power supply VDD of the LSI 110 does not modulate the signal, it first generates the V1 potential, and immediately after that, the ACT signal is generated, the nonvolatile memory 106 operates, the power is consumed, and the voltage drops to the potential V4.
[0018]
In other words, the nonvolatile memory 106 is always activated when the signal is not modulated, thereby causing a voltage drop from a state in which the LSI 110 voltage is high, so that the power supply VDD is prevented from being lower than the potential at the time of modulation, and the communication distance is increased. It becomes possible to do.
[0019]
In addition, since the activation signal ACT of the nonvolatile memory 106 is not generated at the timing when the signal shifts from non-modulation to modulation or from modulation to non-modulation, it is not affected by the power consumption of the nonvolatile memory 106 and is stable. Thus, the rising / falling of the power supply VDD of the LSI 110 can be generated. Therefore, it is possible to reliably generate data (DATA) in the demodulation circuit 103.
[0020]
(Embodiment 2)
FIG. 4 shows a configuration of a contactless data transmission / reception circuit according to the second embodiment of the present invention. An LSI 151 composed of a coil 157 and a capacitor 158 and an LSI 161 are connected. The LSI 161 includes a rectifier circuit 152, a demodulator circuit 153, a modulator circuit 154, a control circuit 155, a counter circuit 159, a frequency divider circuit 160, and a nonvolatile memory 156.
[0021]
The rectifier circuit 152 extracts a DC power source from the signal received by the antenna 151. The demodulation circuit 153 extracts data and a clock from the signal received by the antenna 151. The modulation circuit 154 transmits data via the antenna 151. The control circuit 155 generates a signal RESET that resets the counter circuit 160. The frequency divider 160 divides the clock (CLK) generated by the demodulator 153 to generate the clock CLKn. The counter circuit 159 receives the clock CLKn generated by the frequency dividing circuit 160 and controls a signal ACT for starting the nonvolatile memory 156.
[0022]
FIG. 5 shows a timing chart of the non-contact data transmission / reception circuit in the second embodiment. Usually, the communication signal with the reader / writer is transmitted with the modulation signal transmitted from the start flag at the head. The carrier wave is used to generate a clock (CLK) through the demodulation circuit 153. This clock (CLK) is divided by the frequency dividing circuit 160 to generate the clock (CLKn). The period of the divided clock (CLKn) is set to a value Tb that is smaller than the minimum non-modulation period Ta of the communication signal.
[0023]
The control circuit 155 receives the start flag, generates a reset signal RESET for the counter circuit 159, and sets the counter circuit 159 to 0 with this reset signal. Thereafter, the counter circuit 159 is counted up by the divided clock (CLKn). The activation signal ACT of the nonvolatile memory 156 is generated according to the value of the counter circuit 159. Here, the communication signal is set so that a non-modulation period exists at a predetermined time interval from the start flag. Therefore, by generating the start signal ACT based on the value of the counter circuit 159 as described above, it is possible to generate the start signal ACT during the predicted non-modulation period.
[0024]
As described above, the cycle Tb in which the counter 159 is incremented is smaller than the minimum non-modulation period Ta. Therefore, the nonvolatile memory 156 can always be completed in the non-modulation period, that is, the power supply VDD of the LSI 161 is high. It becomes possible to extend the communication distance.
[0025]
【The invention's effect】
According to the present invention, the influence of the power consumption of the nonvolatile memory is avoided by making the timing of the signal for starting the nonvolatile memory appropriate. As a result, it is possible to increase the communication distance and restore the signal more stably.
[Brief description of the drawings]
1 is a block diagram showing a contactless data transmission / reception circuit according to a first embodiment of the present invention. FIG. 2 is a diagram showing a configuration of an edge detection circuit in the circuit of FIG. 1. FIG. 3 is a timing chart of the circuit of FIG. 4 is a block diagram showing a contactless data transmission / reception circuit according to the second embodiment. FIG. 5 is a timing chart of the circuit shown in FIG. 4. FIG. 6 is a block diagram showing a conventional contactless data transmission / reception system. System timing chart [FIG. 8] Timing chart showing the operation of the system of FIG.
1,13 Antenna 2 Rectifier circuit 3 Demodulator circuit 4 Modulator circuit 5 Control circuit 6 Non-volatile memory 7, 10 Coil 8, 11 Capacitor 9 LSI
12 Reader / Larter 101 Antenna 102 Rectifier Circuit 103 Demodulator Circuit 104 Modulator Circuit 105 Control Circuit 106 Nonvolatile Memory 107 Coil 108 Capacitor 109 Edge Detection Circuit 110 LSI
120, 121 D flip-flop circuit (D-FF)
122 Inverter circuit 123 AND circuit 151 Antenna 152 Rectifier circuit 153 Demodulator circuit 154 Modulator circuit 155 Control circuit 156 Non-volatile memory 157 Coil 158 Capacitor 159 Counter circuit 160 Divider circuit 161 LSI

Claims (1)

A built-in nonvolatile memory for storing data, have rows contactless data transmission and reception by the communication signals of an amplitude shift keying scheme with the reader writer, the non-volatile memory wherein the communication signal is a period of unmodulated In the semiconductor memory device having the means for starting the memory , the semiconductor memory device has means for detecting the rising edge of the communication data sent from the reader / writer by amplitude modulation, and the signal is detected by using the signal that detects the rising edge. A semiconductor memory device, wherein a nonvolatile memory is activated .

Images