JP2000307465A - Bpsk demodulating circuit and noncontact ic card system with the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the BPSK demodulating circuit which has small malfunction due to noise, etc. SOLUTION: In the BPSK demodulating circuit 56 which demodulates a BPSK-modulated binarized response signal (g) into NRZ data (e), a clock generation part 56a generates an internal clock CK1 of frequency much higher than the frequency of the binarized response signal (g). A phase switching detection part 56b synchronizes the binarized response signal (g) with an internal clock to output a synchronizing response signal and operates in synchronism with the internal clock CK1 to detect a phase shift point of the synchronizing response signal and outputs a detection pulse PhO. A flag generation part 56c performs counting operation in synchronism with the clock CK2 synchronized with the internal clock, clears the counter output once the detection pulse PhO is inputted, and sets a flag (n) when the count value reaches a predetermined value. An output inversion part 56g presets an output (e) when the flag (h) is set and then inverts the output (e) each time the detection pulse PhO is inputted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a BPSK demodulation circuit for demodulating a BPSK-modulated binary response signal into NRZ data, an interrogator (reader / writer) and a transponder including the BPSK demodulation circuit in a receiving circuit. The present invention relates to a non-contact type IC card system having an (IC card) and having a BPSK demodulation circuit for exchanging signals between an interrogator and a transponder by an electromagnetic coupling method.

[0002]

2. Description of the Related Art A general structure of a non-contact type IC card system 10 using an electromagnetic coupling method and an operation outline thereof will be described with reference to FIGS. The numerical values of the frequency and the like shown below are examples, and other numerical values may be adopted. (Transmission Operation of Interrogator) First, the configuration of the interrogator 12 and its transmission operation will be described. The oscillating unit 14 outputs a carrier a (fc
= 13.56MHz) is output continuously. In the first data processing unit 16, the NRZ (Non Return to Z
ero) A question command b which is data (106 Kbps) is output. In addition, as will be described later, a response command of the transponder 20 that is demodulated and output by the first demodulation unit 18 is captured and analyzed. The first modulation unit 22 converts the carrier a into an ASK (Amplitude Shif) based on a query command b which is NRZ data.
t Keying) Output the modulated signal c.

The antenna coil driving section 24 amplifies the signal c output from the first modulation section 22 and outputs the amplified signal c to the first antenna coil 26. Therefore, the first antenna coil 2
6 outputs a high-frequency signal having the frequency component of the carrier wave a that has been amplitude-modulated by the query command b. This high-frequency signal is obtained by amplifying the signal c. In this example, as shown in FIG.
Assuming that the amplitude of the command “1” is A and the amplitude of the “0” is B, the modulation degree is (A−B) /
It is calculated by (A + B) × 100. Actually, the modulation factor is adjusted to 10% by varying B with respect to A.

Next, a description will be given of an example of a configuration of a receiving circuit on the interrogator 12 side and a receiving operation. The receiving circuit includes a first antenna coil 26, a first demodulation unit 18, a detection transformer 28 in which a primary winding 28 a is interposed in series between the first antenna coil 26 and the antenna coil driving unit 24. Having. An example of a typical configuration of the detection transformer 28 and the first demodulation unit 18 will be described in more detail with reference to FIG. The first demodulation unit 18 includes a plurality of capacitors for adjusting a voltage induced in the secondary winding 28b of the detection transformer 28 and a sensitivity adjustment unit 18a including a terminating resistor 30 for terminating both ends of the secondary winding 28b; And a demodulation signal processing unit 18b.

The first demodulator 18 detects a carrier a continuously output from the first antenna coil 26 and a response command component that ASK-modulates the carrier a, as described later. The signal is picked up separately from the transmission line X by using the signal 28 and output from the secondary winding 28b. Subsequently, the demodulation signal processing unit 18b separates the signal from the transmission line X as described later and extracts a response modulation signal component from the picked-up signal by envelope detection.
Further, this response modulation signal component is
BPSK (Binary Phase Shift Keying: 2)
A phase-modulated (modulated) response signal is obtained as a binarized response signal. And BPS is applied to this response modulation signal.
By performing K demodulation, a response command d of the transponder 20 is extracted. As a result, the first data processing unit 16 responds to the
Can be confirmed.

(Receiving / Transmitting Operation of Transponder) On the other hand, when the transponder 20 enters the reach of the high-frequency signal output from the interrogator 12, a magnetic field is induced in the built-in second antenna coil 32 by the high-frequency signal. Is done. The second antenna coil 32 is configured as a part of a resonance circuit set so as to obtain an appropriate Q that can efficiently convert the induced magnetic field into a voltage. Note that a load switching unit 34 capable of connecting and disconnecting a load to the resonance circuit is connected to the resonance circuit so that Q of the resonance circuit can be selectively switched.

[0007] The voltage generated in the second antenna coil 32 is taken into the second demodulation section 36, demodulated by envelope detection, and the interrogation command sent from the interrogator 12 is taken out. Although the fundamental frequency component of the generated voltage is constituted by a carrier wave, the transponder 20 rectifies the generated voltage and charges the capacitor to use it as an internal power supply. This fundamental frequency component is binarized and used as an internal clock. The second data processing unit 38 operates based on a power supply and an internal clock obtained from a carrier wave,
It performs internal processing according to the contents of the question command sent from the server, prepares a response command as a response signal, returns the response command to the interrogator 12, and responds.

This response operation will be described with reference to FIG. In the second data processing unit 38, a response command (NRZ data, 106 Kbps) which is a response signal as shown in FIG.
Assume that e is prepared. Then, the internal clock (fc = 13.56
MHz) as an example to generate a subcarrier (fsc = 847 KHz) f as shown in FIG.
BPSK modulates this subcarrier f. The fundamental frequency of the binarized response modulation signal (hereinafter simply referred to as a binarized response signal) g generated by this modulation is fsc = 847 KHz.
However, when the response command changes from "1" to "0" or when the response command changes from "0" to "1", the phase is inverted in synchronization.

In the second data processing section 38, the load switching section 34 is operated when the binary response signal g is "high: 1" and "low: 0" to switch the load on the resonance circuit.
As a result, the Q of the resonance circuit including the second antenna coil 32 of the transponder 20 switches, so that the second antenna coil 3 has a magnetic coupling relationship with the second antenna coil 32.
2, the amplitude of the carrier a continuously output from the first antenna coil 26 that induces a magnetic field also changes depending on whether the load on the resonance circuit is light or heavy. Therefore,
As a result, the carrier a continuously output from the first antenna coil 26 is ASK-modulated in synchronization with the timing of the subcarrier f as shown in FIG.
0 means that the carrier wave a output from the interrogator 12 is modulated and the answer command e is returned. Then, the interrogator 12 demodulates the carrier wave a modulated by the response operation of the transponder 20, and receives the response command e output from the transponder 20.

(Reception Operation of Interrogator) Next, the demodulation operation of the first demodulator 18 in the interrogator 12 will be described with reference to FIGS. First, by the response operation of the transponder 20, as described above, the carrier a
(Fc = 13.56 MHz) is modulated, and a signal as shown in FIG. 4C appears in the first antenna coil 26. Since the modulation is performed at the timing of the binarized response signal g, the amplitude of the carrier wave a changes at the cycle of the binarized response signal g (fsc = 847 KHz).

The detection transformer 28 of the interrogator 12 separates the binary response signal g component including the carrier a component from the transmission line X, and outputs it to the demodulation signal processing unit 18b. The demodulation signal processing unit 18b performs envelope detection on the input signal and extracts a binarized response signal g component as shown in FIG. Furthermore, the binarized response signal g is binarized (digitally) using a comparator or the like, thereby obtaining a binarized response signal g as shown in FIG. Finally, by subjecting the binarized response signal g to BPSK demodulation, a response command (NRZ data, 106 Kbps) e shown in FIG. 4F whose polarity is inverted at the phase displacement point of the binarized response signal g is obtained. .

Next, it is included in the demodulation signal processing unit 18b,
The BPSK demodulation circuit 40 that generates a response command e by BPSK demodulating the binary response signal g will be described in more detail with reference to FIG. First, the frame synchronization part of the response command e sent from the transponder 20 side, that is, the structure of the synchronization data always added to the first part of the response command e, as shown in FIG. The dummy data of "1" is continuously added for a certain period. The start bit of the valid data constituting the response command e is always "0". Therefore, in the BPSK demodulation circuit 40,
A phase change when the NRZ data is switched from "1" to "0" for each communication is captured, and the data is demodulated based on this change.

The demodulation operation will be described together with the configuration of the BPSK demodulation circuit 40. The binary response signal g input to the BPSK demodulation circuit 40 is input to the clock terminal of the counter 40a, and switches at the switching point where the phase of the modulation frequency component of the BPSK-modulated binary response signal g is inverted. It is input to the phase switching detection unit 40b for detection. In addition,
When the count value of the counter 40a reaches a predetermined value, the binary response signal g input to the clock terminal of the counter 40a is transmitted to the clock terminal of the binary response signal g so that the counter 40a stops the counting operation. An OR operation is performed with the output bit signal h at a predetermined position of the counter 40a so that the input is blocked, and the output of the OR gate 40c is input to the clock terminal of the counter 40a. The predetermined value is set so that the output bit signal h is output only when the counter 40a detects continuous "1" dummy data always added to the first part of the response command e. . For this reason, the output bit signal h can also be said to be a flag indicating that continuous dummy data "1" has been detected. Hereinafter, the output bit signal h is also referred to as a flag.

The outline of the operation of the phase switching detecting section 40b is as follows.
The same switching detection clock as the PSK modulation carrier frequency is used.
It is generated using an internal clock of the interrogator 12 (such as a clock from the oscillator 14). Then, the switching detection clock is appropriately delayed, and the binarized response signal g is latched. Thereby, the NRZ data is temporarily demodulated. The NRZ data generated at this time is NRZ data.
“1” and “0” may be inverted every demodulation. Also,
It is easily affected by noise when there is no signal. Therefore, the NRZ data (for the sake of explanation, the original NRZ data) is further shifted (delayed) by one clock of the BPSK modulation carrier frequency by a flip-flop or the like to generate NRZ data (for the explanation, delayed NRZ data). Then, by taking the exclusive OR of the original NRZ data and the delayed NRZ data, it occurs only at the switching of the phase of the binary response signal g, and B
A detection pulse PhO having a length of one clock of the PSK modulation carrier frequency is generated. And this detection pulse Ph
O, the formal NRZ data is converted to the phase change detection unit 40b.
Is generated by a flip-flop arranged at the subsequent stage.

The detection pulse PhO output from the phase switching detector 40b is input to the clock terminal of a flip-flop (D-FF) 40d at the subsequent stage of the phase switching detector 40b. The flag h of the counter 40a is the D-FF 40
d is input to the preset terminal. Furthermore, this DF
In F40d, a signal from the inverted output terminal is input to the data input terminal. With this configuration, the D-FF 40d inverts the signal output from the non-inverting output terminal of the D-FF 40d every time the detection pulse PhO is input. Therefore, in response to the rise of the flag h, the output is preset to "1", and thereafter, it functions as an output inverting unit that inverts the output every time the detection pulse PhO is input.

According to the configuration of the BPSK demodulation circuit 40, the counter 40a is first reset when the power is turned on, and when the response command e sent from the transponder 20 is received thereafter, first, the response command e Since the dummy data of “1” is continuously added to
The counter 40a starts the counting operation by the binary response signal g whose phase is not switched. Further, the phase switching detection section 40b starts detecting a phase change of the binary response signal g. At the beginning of the binary response signal g, dummy data of "1" is continuously added and there is no change in the phase of the binary response signal g. Counting is performed until the flag h is output and the counting operation is stopped. Thereby, the counter 4
At 0a, it is determined that the continuous input period of "1" is sufficiently long and is the dummy data of "1" always added at the beginning of the binary response signal g. The D-FF 40d performs a preset operation in response to the flag h, sets the signal from the non-inverting output terminal to "1", and matches the polarity of the dummy data.

When valid data constituting the response command e starts to be input following the dummy data of "1", the start bit of the valid data is always "0". Is output. Then, in the D-FF 40d, the signal from the non-inverting output terminal, which has been set to "1" by the preset operation, is inverted at the timing of input of the detection pulse PhO, and is set to "0".
Thereafter, the D-FF 40d inverts the polarity of the signal from the non-inversion output terminal every time the detection pulse PhO is input. Thereby, the NRZ data is demodulated.

[0018]

However, the above-mentioned conventional BPSK demodulation circuit has the following problems. The counter 40a performs a counter operation using the binary response signal g as a clock signal. In the non-signal period other than the period in which the response command e is sent from the transponder 20, the signal is generated by various factors such as power supply, switching, and various frequency clocks used inside the interrogator 12. The noise that occurs is noticeable. For this reason, the counter 40a performs the counting operation due to the noise, and a state occurs in which the flag h is output before the continuous “1” data is transmitted. If the phase switch detection unit 40b also malfunctions due to noise during the no-signal period and outputs the detection pulse PhO, there arises a problem that "1" and "0" of the signal output from the BPSK demodulation circuit are inverted. .

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a BPSK demodulation circuit which is less likely to malfunction due to noise or the like.

[0020]

To solve the above-mentioned problems, the present invention has the following arrangement. That is, the BPSK demodulation circuit according to claim 1 of the present invention is a BPSK demodulation circuit for demodulating a BPSK-modulated binary response signal into NRZ data.
In the demodulation circuit, a clock generation unit for generating an internal clock having a frequency sufficiently higher than the frequency of the binary response signal, synchronizing the input binary response signal with the internal clock, and synchronizing the synchronous response signal A phase switching detection unit that outputs a detection pulse that operates in synchronization with the internal clock, detects a phase displacement point of the synchronization response signal, and outputs a detection pulse;
A count operation is performed in synchronization with the internal clock or a clock obtained by dividing the internal clock. When the detection pulse is input, the counter output is cleared, and when the count value reaches a predetermined value, a flag is set. , And an output inverting unit that presets an output in response to the rising of the flag, and then inverts the output every time the detection pulse is input.

According to this, since the counting operation is performed using the internal clock, it is hardly affected by noise. The phase switching detection unit generates the detection pulse by using the binarized response signal once synchronized with the internal clock, so that the phase switching detection unit is also hardly affected by noise. Therefore, a stable demodulation operation can be performed. According to a second aspect of the present invention, there is provided a non-contact IC card system having a BPSK demodulation circuit, comprising: an interrogator including the BPSK demodulation circuit according to the first aspect in a receiving circuit; and a transponder. Signals are transmitted and received between the transmitter and the transponder by an electromagnetic coupling method.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of a BPSK demodulation circuit according to the present invention will be described below in detail with reference to the accompanying drawings. As an example, a transponder included in a receiving circuit for an interrogator in a non-contact IC card system in which a signal is exchanged between an interrogator (reader / writer) and a transponder (IC card) by an electromagnetic coupling method. Although a description will be given using a BPSK demodulation circuit that demodulates a BPSK-modulated binary response signal into NRZ data, the present invention can also be applied to a BPSK demodulation circuit other than a non-contact IC card system.

(Overall IC Card System) First, the overall configuration of a non-contact IC card system 50 having a BPSK demodulation circuit according to the present invention is similar to that of the conventional non-contact IC card system 10 shown in FIG. The interrogator (reader / writer) 52 and the transponder (I
C card) 20.

The interrogator 52 includes the oscillation unit 14 and the first
It includes a data processing unit 16, a first modulation unit 22, a first antenna coil 26, an antenna coil driving unit 24, and a first demodulation unit 54. The configuration of the transponder 20 is the same as the configuration described in the conventional example, and the second antenna coil 32
, A load switching unit 34, and a second demodulation unit 36
And a second data processing unit 38.

Here, the characteristic part of the present invention resides in the receiving circuit of the interrogator 52 in the IC card system 50, and more specifically, the demodulation signal processor 18b included in the first demodulator 54.
Is that the BPSK demodulation circuit 56 constituting a part of the configuration shown in FIG. The configuration of the BPSK demodulation circuit 56 will be described. The clock generation unit 56a has a BP
The first internal clock CK1 having a frequency sufficiently higher than the frequency of the binary response signal g input to the SK demodulation circuit 56 is generated. Further, a second internal clock CK2 having the same frequency as the BPSK modulation carrier frequency fsc is generated. The clock generator 56a generates these clocks CK1 and CK2 using the output clock a of the oscillator 14.

In the phase switching detecting section 56b, the input 2
By synchronizing the value response signal g with the first internal clock CK1,
The synchronization response signal j is output (see FIG. 9). In particular,
As an example, a binary response signal g is shifted (delayed) by one clock of the first internal clock CK1 by a flip-flop (not shown) or the like to obtain a synchronization response signal j. The phase switching detector 56b operates in synchronization with the first internal clock CK1, detects a phase displacement point of the synchronization response signal j, and outputs a detection pulse PhO. More specifically, the detection pulse PhO is obtained by synchronizing the synchronization response signal j and one clock of a clock having the same frequency as the BPSK modulation carrier frequency (accordingly, the second internal clock CK2 may be used) with a flip-flop or the like. It is generated by taking an exclusive OR with a signal shifted (delayed) by a minute. Therefore, the detection pulse PhO is
The carrier frequency has a length of one clock.

In the flag generator 56c, the output clock of the oscillator 14 or a clock obtained by dividing this clock (for example, the first internal clock CK1 or the second internal clock CK2)
Etc.) and the detection pulse
It has a function of clearing the counter output when PhO is input and setting a flag h when the count value reaches a predetermined value. Specifically, when the dummy data of “1” as the frame synchronization signal is detected, the flag h is set, and the count value is set so that the count time is slightly shorter than the period of the continuous dummy data of “1”. Is set. The circuit configuration of the flag generator 56c is, for example, as shown in FIG.
Is input to the clear terminal and the detection pulse PhO is input to the counter 56d. When the count value reaches a predetermined value, the output bit at a predetermined position that changes from "0" to "1" is "1". Is held at the clock terminal, the signal of the output bit of the predetermined order is input to the clock terminal, and the flip-flop (D-F) whose input terminal is pulled up to "1"
F) 56e. Note that the counter 5
A reset signal is input to 6d and the clear terminal of the D-FF 56c, and the output can be cleared from the outside.
The reset signal and the detection pulse PhO are ORed by the OR gate 56f and input to the clear terminal of the counter 56d.

The D-FF 56g has the same configuration as the D-FF 40d described in the conventional example, and functions as an output inverting unit. When the flag h is set, the output is preset, and then the detection pulse PhO is input. It has the function of inverting the output every time it is performed.

FIG. 8 shows the operation of the BPSK demodulation circuit 56.
This will be described with reference to FIG. First, the reset signal sets the flag h from the flag generator 56c to "0". In the circuit of FIG. 8, the counter 56d and the D-FF 56e
Output is cleared. The clock generator 56a starts outputting the first internal clock CK1 and the second internal clock CK2. As shown in the timing chart of FIG.
Thereafter, even if noise occurs until the response command e is output on the transponder 20 side, the flag generator 56c performs a counting operation based on the second internal clock CK2 as compared with the conventional circuit. Start of operation is prevented. Thereafter, when the reception of the response command e is started, first, the dummy data of “1” is continuously added at the beginning of the response command e.
6b, the phase change of the response command e is not detected. Therefore, the detection pulse PhO is not output. Therefore, the counter 56d is not cleared, and starts counting at the timing of the second internal clock CK2.

When the count value reaches a predetermined value, the flag h from the flag generator 56c changes from "0" to "1", and the flag h of the D-FF 56g acting as an output inverting unit accordingly. The output is preset,
The demodulated output of the BPSK demodulation circuit 56 is "1". Thereafter, when the dummy data period of the continuous “1” of the response command e ends and the period of the valid data starts, the start bit of each valid data is always “0”.
Is input, the phase of the response command e changes.
Therefore, the phase change detecting section 56b detects the phase change of the response command e and outputs the detection pulse PhO, and the output of the D-FF 56g receiving the detection pulse PhO is inverted from "1" to "0". . Further, the flag generator 56
The counter 56d inside c is cleared. Thereafter, each time the phase switching detecting section 56b detects a phase change of the response command e and outputs the detection pulse PhO, the output of the D-FF 56g is inverted, and the response command e demodulated by BPSK is changed to the BPSK.
It is output from the SK demodulation circuit 56.

As described above, various preferred embodiments of the present invention have been described. However, the present invention is not limited to the above-described embodiments, and many modifications can be made without departing from the spirit of the invention. Of course.

[0032]

According to the present invention, the BPSK demodulation circuit and the BPSK
If a non-contact type IC card system having a K demodulation circuit is used, the count operation is performed using an internal clock.
Less susceptible to noise. Further, since the phase switching detection unit generates the detection pulse using the binary response signal once synchronized with the internal clock, it is also hardly affected by noise. Therefore, there is an effect that a stable demodulation operation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a general configuration of a contactless IC card system having a BPSK demodulation circuit.

FIG. 2 is a waveform of a question command output by a first data processing unit in FIG. 1;

FIG. 3 is an output waveform of a first modulation unit in FIG. 1;

4A is a waveform of a response command, FIG. 4B is a waveform of a response modulation signal, FIG. 4C is a waveform of a carrier output by an interrogator modulated by the response modulation signal, and FIG. (C) is an output waveform obtained by envelope detection, (e) is a binarized waveform of (d), and (f) is a response command obtained by subjecting (e) to BPSK demodulation by the first demodulator. It is a waveform.

FIG. 5 is a circuit diagram showing a configuration of a conventional detection transformer and a first demodulation unit.

FIG. 6 is a circuit diagram showing a configuration of an example of a conventional BPSK demodulation circuit.

FIG. 7 is an explanatory diagram for explaining a frame configuration of a response command and a bit configuration of valid data following the frame synchronization portion.

FIG. 8 is a circuit diagram showing a configuration of an embodiment of a BPSK demodulation circuit according to the present invention.

FIG. 9 is a timing chart for explaining the demodulation operation of FIG.

[Explanation of symbols]

 56 BPSK demodulation circuit 56a Clock generation unit 56b Phase switching detection unit 56c Flag generation unit 56g D-FF CK1 as the output inversion unit First internal clock CK2 Second internal clock g Binarization response signal h Flag j Synchronization response signal PhO detection pulse

Claims (2)

[Claims] An BPSK-modulated binary response signal is represented by N
In a BPSK demodulation circuit for demodulating into RZ data, a clock generator for generating an internal clock having a frequency sufficiently higher than the frequency of the binary response signal, and synchronizing the input binary response signal with the internal clock A phase switching detector that outputs a synchronization response signal, operates in synchronization with the internal clock, detects a phase displacement point of the synchronization response signal and outputs a detection pulse, and separates the internal clock or the internal clock. A flag generation unit that performs a count operation in synchronization with the clock that has circulated, clears a counter output when the detection pulse is input, and sets a flag when the count value reaches a predetermined value; Presets the output in response to
And an output inverting unit for inverting the output every time the detection pulse is input. 2. An interrogator including the BPSK demodulation circuit according to claim 1 in a receiving circuit, and a transponder, wherein signals are transmitted and received between the interrogator and the transponder by an electromagnetic coupling method. A non-contact type IC card system having a BPSK demodulation circuit.