JP4157237B2 - Voltage nonlinear resistor and manufacturing method thereof - Google Patents

Description

【００６８】
【表２】

【００６９】
第１の実施の形態に該当する試料、つまりＡｌＰＯ₄（オルトリン酸アルミニウム）の含有量が１，２５ｗｔ％、ＭｎＦｅ₂Ｏ₄（フェライト）の含有量が０．１,１５ｗｔ％、Ｆｅ₂Ｏ₃（酸化鉄）の含有量が０．１,１５ｗｔ％の第１の高抵抗層３を有する試料（表１及び表２中の試料番号２２，２７，３０，３１，４２、４３，４６，４７）は、１７０ｋＡ以上という高いインパルス電流印加により破壊が生じた。
【００７０】
これに対して、上記以外の試料は、１００〜１３０ｋＡという比較的低いインパルス電流印加により破壊が生じた。また、第１の実施の形態に該当する含有量のＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を副成分として形成した第１の高抵抗層３の表面に、ＳｉＯ₂（シリカ）もしくはＡｌ₂Ｏ₃（アルミナ）もしくはＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）もしくはＡｌ₂Ｏ₃（アルミナ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分として第２の高抵抗層４を形成した試料（表１及び表２中の２３〜２６，４８〜５１）は、１９０〜２００ｋＡという極めて高いインパルス電流印加により破壊が生じた。
【００７１】
以上の結果から明らかなように第１の実施の形態は、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）を１．０〜２５ｗｔ％、ＭｎＦｅ₂Ｏ₄（フェライト）を０．１〜１５ｗｔ％，Ｆｅ₂Ｏ₃（酸化鉄）を０．１〜１５ｗｔ％含む第１の高抵抗層３を備えることによって、この第１の高抵抗層３が焼結体１の側面に強く接着することができ、耐電圧性能が向上する。
【００７２】
そのため、電圧非直線抵抗体は飛躍的にインパルス電流に対する保護能力が向上することがわかる。また、ＳｉＯ₂（シリカ）もしくはＡｌ₂Ｏ₃（アルミもしくはＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）もしくはＡｌ₂Ｏ₃（アルミナ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分としている第２の高抵抗層４を形成することにより、さらに、飛躍的にインパルス電流に対する保護能力が向上することが分る。
【００７３】
以上、第１の高抵抗層３の成分として、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト），Ｆｅ₂Ｏ₃（酸化鉄）のみを成分とする例を記述したが、その他ＴｉＯ₂（酸化チタン）の他、高抵抗層の接着強度を向上させる成分を加えた場合においても、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト），Ｆｅ₂Ｏ₃（酸化鉄）の含有量が上記の範囲において、最良のインパルス耐量を実現できることが確認できている。
【００７４】
次に第２の実施の形態について述べる。
【００７５】
第２の実施の形態では、前述した第１の実施の形態で形成される第１及び第２の高抵抗層３及び４の厚さを１０μｍ〜1ｍｍとするものである。
【００７６】
ここで、第１及び第２の高抵抗層３及び４の厚みが異なる数種類の電圧非直線抵抗体を作製し、第２の実施の形態に該当する試料と、それ以外の試料とを比較して、第２の実施の形態の作用効果について説明する。
【００７７】
まずＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト），Ｆｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％含有した第１の高抵抗層３を形成し、その上にＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とした非晶質の第２の高抵抗層４を形成する。その際、高抵抗層３及び４の厚みをそれぞれ、０．１,１,１０,１００,５００μｍ及び１,２ｍｍに調整した試料を作製し、合計７種類の試料を作製した。
【００７８】
以上のようにして作製した各試料について、各試料に８／２０μｓ波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加し、試料が破壊する電流値を測定し、各試料の過電圧保護能力の評価を行った。その結果を図２に示す。第２の実施の形態に該当する試料、つまり第１及び第２の高抵抗層３及び４の厚みが１,１０,１００,５００μｍ及び１ｍｍの試料は、１９０ｋＡ以上のインパルス電流印加により破壊が生じた。
【００７９】
これに対して、第２の実施の形態に該当しない試料、つまり高抵抗層の厚みが０．１μｍおよび２ｍｍの試料は、１００〜１３０ｋＡという低いインパルス電流印加により破壊が生じた。これは、第１及び第２の高抵抗層３及び４の厚みが小さ過ぎると優れたインパルス電流に対する保護能力を得ることができないこと、反対に第１及び第２の高抵抗層３及び４の厚みが厚つ過ぎると、今度は厚みが増加するに連れて第１及び第２の高抵抗層３及び４の接着強度が低下し、優れたインパルス電流に対する保護能力を得ることができないことを示している。
【００８０】
以上の結果より、第２の実施の形態では、第１及び第２の高抵抗層３及び４の厚さを１０μｍ〜1ｍｍとすることにより、適切な接着強度と良好な耐電圧性能の両方を確保することができ、インパルス電流に対する保護能力を大きく向上させることができる。
【００８１】
次に第３の実施の形態について説明する。
【００８２】
第３の実施の形態では、第１の実施の形態で第１の高抵抗層３を形成する工程のうち、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加して混合スラリーを作る混合工程において、平均粒径が０．０１〜１０μｍであるＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を用いるものである。
【００８３】
ここで、第３の実施の形態の作用効果を説明するために、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）の平均粒径が異なる数種類の電圧非直線抵抗体を作製する。
【００８４】
まず、上記第２の実施の形態と同様にＡｌ₆ＳｉＯ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト），Ｆｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％含有した第１の高抵抗層３を形成する。この第１の高抵抗層３を形成するにあたって、平均粒径が０．００１,０．０１,０．１,１,１０及び２０μｍのＭｎＦｅ₂Ｏ₄（フェライト）、Ｆｅ₂Ｏ₃（酸化鉄）を使用した１２種類の試料を作製した。
【００８５】
これら各試料に対して、第１の高抵抗層３の上にＳｉＯ2（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とした非晶質の第２の高抵抗層４を形成し、評価試料とした。
【００８６】
以上のようにして作製した各試料に、８／２０μｓ波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加して行き、試料が破壊したときの電流値を測定することで、各試料の過電圧保護能力の評価を行った。
【００８７】
その結果を図３に示す。第３の実施の形態に該当する試料、つまりＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）の平均粒径が０．０１〜１０μｍの試料は、１９０ｋＡ以上のインパルス電流を印加することにより破壊が生じたが、平均粒径が上記の範囲外の試料は、１００〜１３０ｋＡのインパルス電流を印加することにより破壊が生じた。
【００８８】
一般的に使用する粉末の平均粒径は細かいほど分散性が悪くなるので、第１の高抵抗層３の均一性が悪くなり、平均粒径が０．０１μｍのＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を用いた試料はインパルス電流に対する保護能力が優れたものとはならない。
【００８９】
一方、使用する粉末の平均粒径が粗いと、やはり高抵抗層成分中に偏積しやすくなるため、平均粒径が２０μｍのＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を用いた試料も、インパルス電流に対する保護能力が優れたものとはならない。
【００９０】
以上の結果より、第３の実施の形態では、平均粒径が０．０１〜１０μｍの範囲のＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加することで、第１の高抵抗層３が適切な均一性を保持でき、優れた耐電圧性能を発揮し、インパルス電流に対する保護能力が優れたものとなる。
【００９１】
次に第４の実施の形態について説明する。
【００９２】
第４の実施の形態では、第１の実施の形態で第１の高抵抗層３を形成する場合、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）とＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分としたスラリーに、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加して混合スラリーを作る混合工程が終了した後、１００時間以内に塗布工程及び焼付け工程を終了させるものである。
【００９３】
ここで、第４の実施の形態の作用効果を説明するために次のような試料を作製した。
【００９４】
Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）とＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分としたスラリーに、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％添加し、スプレー塗布により焼結体１の側面に塗布，焼き付けを行うに当たって、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加後、１，１２，２４,５０,１００,１２０及び１８０時間後に塗布，焼付けを行った７種類の試料を作製した。
【００９５】
これらの各試料に対して、第１の高抵抗層３の上にＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とした非晶質の第２の高抵抗層４を形成し、評価試料とした。
【００９６】
以上のようにして作製した各試料に、８／２０μs波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加して行き、試料が破壊したときの電流値を測定することで、各試料の過電圧保護能力の評価を行った。
【００９７】
その結果を図４に示す。第４の実施の形態に該当する試料、つまりスラリーにＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加後、１００時間以内に塗布，焼付けを行った試料は、１８０ｋＡ以上のインパルス電流印加により破壊が生じた。
【００９８】
これに対して、スラリーにＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加後、１２０及び１８０時間経過後に塗布，焼付けを行った試料は、１００〜１３０ｋＡのインパルス電流印加により破壊が生じた。このように破壊電流値が小さいのは次のような理由が考えられる。
【００９９】
Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）中にＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加すると、添加したＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）が徐々に溶解していき、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）の正常な硬化反応を妨げる。
【０１００】
そのため、第１の高抵抗層３の接着強度を次第に低下し、添加から１２０及び１８０時間経過した後に塗布，焼付けを行っても、第１の高抵抗層３は焼結体１の側面に接着し難く、耐電圧性能が低下してインパルス電流に対する保護能力が優れたものとはならなかった。
【０１０１】
以上の結果より、第４の実施の形態では、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加後１００時間以内に塗布，焼付けを行うことで、第１の高抵抗層３の接着強度が低下しないうちに焼結体１の側面に形成することが可能である。これにより、第４の実施の形態に係る電圧非直線抵抗体はインパルス電流に対する保護能力が優れたものとなる。
【０１０２】
次に第５の実施の形態について説明する。
【０１０３】
第５の実施の形態では、第１の実施の形態で第１の高抵抗層３を形成する場合、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）とＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分としたスラリーに、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加して混合した混合スラリーを塗布した後、焼付けを行う際にその焼き付け最高温度を２００℃〜８００℃とするものである。
【０１０４】
ここで、第５の実施の形態の作用効果を説明するために次のような試料を作製した。
【０１０５】
Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）とＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分としたスラリーに、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％添加し、スプレー塗布により焼結体１の側面に塗布，焼き付けを行うに当たって、焼付け時の最高温度を１５０,２００,４００,６００,８００及び１０００℃で焼付けを行った５種類の試料を作製した。
【０１０６】
これらの各試料に対して、第１の高抵抗層３の上にＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とした非晶質の第２の高抵抗層４を形成し、評価試料とした。
【０１０７】
以上のようにして作製した各試料に、８／２０μs波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加し、試料が破壊する電流値を測定し、各試料の過電圧保護能力の評価を行った。
【０１０８】
その結果を図５に示す。第５の実施の形態に該当する試料、つまり第１の高抵抗層３の焼き付け最高温度を２００〜８００℃の範囲で焼付けを行った試料は、１９０ｋＡ以上のインパルス電流印加により破壊が生じた。
【０１０９】
これに対して、１５０℃及び１０００℃で焼付けを行った試料は、１００〜１１０ｋＡのインパルス電流印加により破壊が生じた。このように破壊電流値が小さいのは次のような理由が考えられる。
【０１１０】
２００℃未満の焼付け温度では、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）の硬化反応が起こらないため、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト）、Ｆｅ₂Ｏ₃（酸化鉄）を含んだ第１の高抵抗層３が形成されなかったため、焼結体１の側面への接着度合いが悪く、耐電圧が低下してインパルス電流に対する保護能力が優れたものとはならなかった。
【０１１１】
また、８００℃より高い焼付け温度では、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）の正常な硬化反応を起こすことができなかっため、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト）、Ｆｅ₂Ｏ₃（酸化鉄）を含んだ第１の高抵抗層３が形成されない。このため、焼結体１の側面への接着度合いが悪く、耐電圧が低下してインパルス電流に対する保護能力が優れたものとはならなかった。
【０１１２】
以上の結果より、第５の実施の形態では、第１の高抵抗層３を焼付ける最高温度を２００〜８００℃で行うことで、接着強度が最も高い状態で第１の高抵抗層３を焼結体１側面に形成することが可能である。これにより、第５の実施の形態に係る電圧非直線抵抗体はインパルス電流に対する保護能力を優れたものとなる。
【０１１３】
次に第６の実施の形態について説明する。
【０１１４】
第６の実施の形態では、第１の実施の形態で第１の高抵抗層３を形成する場合、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）とＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分としたスラリーに、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）を添加して混合した混合スラリーを塗布した後、焼付けを行う際に少なくとも１００℃〜最高温度までの昇温速度を１０℃／ｈｒｓ〜３００℃／ｈｒｓで行うものである。
【０１１５】
ここで、第５の実施の形態の作用効果を説明するために次のような試料を作製した。
【０１１６】
Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）とＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分としたスラリーに、ＭｎＦｅ₂Ｏ₄（フェライト）及びＦｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％添加し、スプレー塗布により焼結体１の側面に塗布，焼き付けを行うに当たって、焼付け時の昇温速度を５,１０,１００,２００,３００及び４００℃／ｈｒｓで焼付けを行った６種類の試料を作製した。
【０１１７】
これらの各試料に対して、第１の高抵抗層３の上にＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とした非晶質の第２の高抵抗層４を形成し、評価試料とした。
【０１１８】
このようにして作製した各試料に対して、それぞれ８／２０μs波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加し、試料が破壊する電流値を測定し、各試料の過電圧保護能力の評価を行った。
【０１１９】
その結果を図６に示す。第6の実施の形態に該当する試料、つまり第１の高抵抗層の焼き付け昇温速度を１０〜３００℃／ｈｒｓの範囲で焼付けを行った試料は、１９０ｋＡ以上のインパルス電流印加により破壊が生じた。
【０１２０】
これに対して、5℃／ｈｒｓ及び４００℃／ｈｒｓで焼付けを行った試料は、１００〜１３０ｋＡのインパルス電流印加により破壊が生じた。このように破壊電流値が小さいのは次のような理由が考えられる。
【０１２１】
１０〜３００℃／ｈｒｓの昇温速度で第１の高抵抗層３を焼付けることによって最適なＡｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）の硬化反応速度を与えることができ、焼結体１の側面への接着度がきわめて高く、耐電圧が向上してインパルス電流に対する保護能力が優れたものとなる。
【０１２２】
これに対して、昇温速度が３００℃／ｈｒｓより速くなるとＡｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）の硬化反応が急激に進行してしまい、焼結体１の側面への接着度が低下する。
【０１２３】
また、１０℃／ｈｈｒｓ未満の焼付け昇温速度では、Ａｌ（Ｈ₂ＰＯ₄）₃（第１リン酸アルミニウム）の硬化反応がゆっくりと進行し、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト）、Ｆｅ₂Ｏ₃（酸化鉄）を含んだ第１の高抵抗層３が完全に形成されなかったため、焼結体１の側面への接着度合いが悪くなるため、耐電圧が低下してインパルス放電耐量特性は低下する。
【０１２４】
以上の結果より、第６の実施の形態では、第１の高抵抗層３を焼付ける昇温速度を１０〜３００℃／ｈｒｓで行うことで、接着強度が最も高い状態で第１の高抵抗層３を焼結体１側面に形成することが可能である。これにより、第６の実施の形態に係る電圧非直線抵抗体はインパルス電流に対する保護能力が優れたものとなる。
【０１２５】
次に第７の実施の形態について説明する。
【０１２６】
第７の実施の形態では、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト）、Ｆｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％含んでいる第１の高抵抗層３の上に、ＳｉＯ₂(シリカ），ＳｉＯＣＨ₃（アルコキシラン），イソプロパノール、ｎ−ブタノール、シリコン系界面活性剤及び酢酸を成分とした水溶液を塗布し焼付けを行うことによって、ＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４を形成する際に、第２の高抵抗層４の焼き付け最高温度を５０〜８００℃の範囲で行うものである。
【０１２７】
ここで、第７の実施の形態の作用効果を説明するために次のような試料を作製した。
【０１２８】
第１の高抵抗層３の上に、ＳｉＯ₂(シリカ）とＳｉＯＣＨ₃（アルコキシラン），イソプロパノール、ｎ−ブタノール、シリコン系界面活性剤及び酢酸を成分とする溶液を塗布して焼付けを行なうに当たって、焼付け時の最高温度を３０，５０，１００，３００，６００，８００，１０００℃で焼付けを行った７種類の試料を作製した。
【０１２９】
このようにして作製した各試料に対して、それぞれ８／２０μs波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加し、試料が破壊する電流値を測定し、各試料の過電圧保護能力の評価を行った。
【０１３０】
その結果を図７に示す。第７の実施の形態に該当する試料、第２の高抵抗層４の焼き付け最高温度を５０〜８００℃の範囲で焼付けを行った試料は、１９０ｋＡ以上のインパルス電流印加により破壊が生じた。
【０１３１】
これに対して、３０℃及び１０００℃で焼付けを行った試料は、１００〜１１０ｋＡのインパルス電流印加により破壊が生じた。このように破壊電流値が小さいのは次のような理由が考えられる。
【０１３２】
５０℃未満の焼付け温度では、イソプロパノール，ｎ−ブタノールの蒸発が起こらないため、ＳｉＯ2（シリカ）とＣＨ3ＳｉＯ1.5（オルガノシリケート）を主成分とする第２の高抵抗層４が形成されなかったため、良好な耐電圧性能が得られず、インパルス電流に対する保護能力が優れたものが得られならなかった。
【０１３３】
また、８００℃を超える焼付け温度では、急激にイソプロパノール，ｎ−ブタノールの蒸発が生じるため、ＳｉＯ₂（シリカ）とＣＨＳｉＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４が正常な状態で形成されなかったため、良好な耐電圧性能が得られず、インパルス電流に対する保護能力が優れたものが得られなかった。
【０１３４】
以上の結果より、第７の実施の形態では、第２の高抵抗層４を焼付ける最高温度を５０〜８００℃で行うことで、良好な耐電圧性能を有する第２の高抵抗層４を第１の高抵抗層３を施した焼結体１の側面に形成することが可能である。これにより、第7の実施の形態に係る電圧非直線抵抗体はインパルス電流に対する保護能力が優れたものとなる。
【０１３５】
以上、第２の高抵抗層４の焼き付け温度を限定した実施例として、ＳｉＯ₂（シリカ）とＣＨＳｉＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４を形成する場合を代表例として記述したが、ＳｉＯ₂（シリカ）またはＡｌ₂Ｏ₃（アルミナ）またはＡｌ₂Ｏ₃（アルミナ）とＣＨＳｉＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４を形成する場合においても、上記の焼き付け温度範囲において、最良のインパルス耐量を実現できる事が確認できている。
【０１３６】
次に本発明の第８の実施の形態について説明する。
【０１３７】
第８の実施の形態では、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）、ＭｎＦｅ₂Ｏ₄（フェライト）、Ｆｅ₂Ｏ₃（酸化鉄）をそれぞれ５ｗｔ％含んでいる第１の高抵抗層３の上に、ＳｉＯ2(シリカ），ＳｉＯＣＨ₃（アルコキシラン），イソプロパノール、ｎ−ブタノール、シリコン系界面活性剤及び酢酸を成分とした水溶液を塗布し焼付けを行うことによって、ＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４を形成する際に、第２の高抵抗層４の焼き付け時の少なくとも３０℃〜最高温度の昇温速度を１０〜３００℃／ｈｒｓの範囲で行うものである。
【０１３８】
ここで、第８の実施の形態の作用効果を説明するため、次のような試料を作製した。
【０１３９】
第１の高抵抗層３の上に、ＳｉＯ₂(シリカ）とＳｉＯＣＨ₃（アルコキシラン），イソプロパノール、ｎ−ブタノール、シリコン系界面活性剤及び酢酸を成分とする溶液を塗布して焼付けを行なうにあたって、焼付け時の最高温度を焼付け時の最高温度を４００℃とし、 焼付け時の昇温速度を５,１０,１００,２００,３００及び４００℃／ｈｒｓで焼付けを行った６種類の試料を作製した。
【０１４０】
このようにして作製した各試料に対して、それぞれ８／２０μs波形のインパルス電流を６０ｋＡから１０ｋＡ刻みで印加しながら、試料が破壊する電流値を測定して各試料の過電圧保護能力の評価を行った。
【０１４１】
その結果を図８に示す。第８の実施の形態に該当する試料、第２の高抵抗層４の焼き付け最高温度を１０〜３００℃／ｈｒｓの範囲で焼付けを行った試料は、１９０ｋＡ以上のインパルス電流印加により破壊が生じた。
【０１４２】
これに対して、５℃／ｈｒｓ及び４００℃／ｈｒｓで焼付けを行った試料は、１００〜１３０ｋＡインパルス電流印加により破壊が生じた。このように破壊電流値が小さいのは次のような理由が考えられる。
【０１４３】
１０℃／ｈｒｓ未満の昇温速度では、反応がゆっくりと進行し、ＳｉＯ₂（シリカ）とＣＨ₃ＳＩＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４が完全に形成されなかったため、良好な耐電圧性能が得られず、インパルス電流に対する保護能力が低下した。
【０１４４】
また、３００℃／ｈｒｓを超える焼付け温度では、急激にイソプロパノール，ｎ−ブタノールの蒸発が生じるため、ＳｉＯ₂（シリカ）とＣＨ₃ＳＩＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４が正常な状態で形成されなかったため、良好な耐電圧性能が得られず、インパルス電流に対する保護能力が低下した。
【０１４５】
以上の結果より、第８の実施の形態では、第２の高抵抗層４を焼付ける最高温度を１０〜３００℃／ｈｒｓで行うことで、良好な耐電圧性能を有する第２の高抵抗層４を第１の高抵抗層３を施した焼結体１の側面に形成することが可能である。これにより、第８の実施の形態に係る電圧非直線抵抗体はインパルス電流に対する保護能力が優れたものとなる。
【０１４６】
以上、第２の高抵抗層４の焼き付け温度を限定した実施例として、ＳｉＯ₂（シリカ）とＣＨ₃ＳＩＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４を形成する場合を代表例として述べたが、ＳｉＯ₂（シリカ）またはＡＬＡｌ₂Ｏ₃（アルミナ）またはＡｌ₂Ｏ₃（アルミナ）とＣＨ₃ＳＩＯ_1.5（オルガノシリケート）を主成分とする第２の高抵抗層４を形成する場合においても、上記の焼き付け温度範囲において、最良のインパルス耐量を実現できることが確認できている。
【０１４７】
以上述べた本発明による電圧非直線抵抗体及びその製造方法の第１の実施の形態乃至第８の実施の形態で述べたように、焼結体１の側面に形成される第１の高抵抗層３が、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分として、ＡｌＰＯ₄（オルトリン酸アルミニウム）を１．０〜２５ｗｔ％、ＭｎＦｅ₂Ｏ₄（フェライト）を０．１〜１５ｗｔ％、Ｆｅ₂Ｏ₃（酸化鉄）を０．１〜１５ｗｔ％含む成分で構成することによって、接着強度が高く、且つ優れた耐電圧性能を発揮し、雷インパルス過電圧等のサージに対する保護能力を向上させることができた。さらに、第１の高抵抗層３の上に、第２の高抵抗層４としてＳｉＯ₂（シリカ）もしくはＡｌ₂Ｏ₃（アルミナ）もしくはＳｉＯ₂（シリカ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）もしくはＡｌ₂Ｏ₃（アルミナ）とＣＨ₃ＳｉＯ_1.5（オルガノシリケート）を主成分とした非晶質の第２の高抵抗層４を形成することによって、さらに優れた耐電圧性能を発揮し、雷インパルス過電圧等のサージに対する保護能力を向上させることができる。
【０１４８】
次に上述した第１の実施の形態乃至第８の実施の形態とは異なる成分で構成される本発明による電圧非直線抵抗体及びその製造方法の実施の形態について説明する。
【０１４９】
第９の実施の形態では、酸化亜鉛を主成分とする焼結体の側面に、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分とし、リン酸アルミニウム塩にリン酸マンガン塩を含む高抵抗剤を塗布し、焼き付け処理を行って高抵抗層を形成する電圧非直線抵抗体について説明する。
【０１５０】
図９は、本実施の形態によるセラミック素子の断面図である。図９に示すように焼結体１１を円板状とし、この焼結体１１の両端面（図９の上下面）には電極１２が設けられる。
【０１５１】
また、焼結体１１の側面（図９の円周方向）には、第１の高抵抗層１３が形成される。
【０１５２】
さらに、第１の高抵抗層１３上に第２の側面高抵抗膜１４が形成される。
【０１５３】
ここで、セラミック素子の焼結体１１を得るためための製造工程を説明する。
【０１５４】
まず、酸化亜鉛（ＺｎＯ）に酸化ビスマス、酸化マンガン、二酸化珪素、酸化クロムをそれぞれ０．５モル％、酸化コバルト、酸化アンチモン、酸化ニッケルをそれぞれ１モル％添加して、酸化亜鉛を調整する。
【０１５５】
次いで、この原料を水や有機バインダー類と共に混合装置に入れて混合し、この混合物をスプレードライヤーで、噴霧造粒する。
【０１５６】
次に、この造粒粉を金型に入れて加圧し、例えば、直径８０mm、厚さ３０mmの円板に成形する。また、例えば寸法が１００mm×１００mm×３０mmのテストピースを成形しておく。
【０１５７】
このようにして得られた成形体を約１２００℃の温度で焼成し、焼結体１１とテストピースＰ１を得る。
【０１５８】
このテストピースＰ１にＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分とし、リン酸アルミニウムとリン酸マンガンを適当量に調整した高抵抗剤を垂らし、ぬれ角を調べた後、別のテストピースＰ１と焼結体１１に塗布し、これを２００〜６００℃の温度範囲で焼き付けを行い、第１の高抵抗層１３を形成する。
【０１５９】
このとき、テストピースと焼結体に形成される第１の高抵抗層１３の膜厚が一定になるように適量の高抵抗剤を塗布する。
【０１６０】
次いで、接着強度を調べるために、第１の高抵抗層１３を形成したテストピースＰ１の接着面と直角な面を研磨して、７０mm×７０mm×２０mmにテストピースＰ２を作成する。
【０１６１】
一方、第１の高抵抗層１３を形成した焼結体１１の両端面を研磨し、アルミニウムの電極を溶射し、電極１２を設けて電圧非直線抵抗体を得る。
【０１６２】
ここで、電圧非直線抵抗体の高抵抗層の膜厚さとテストピースＰ２の膜厚は研磨時に測定した。
【０１６３】
比較例として本発明品と同様の焼結体１１、テストピースＰ１を用い、Ａｌ₂Ｏ₃を主成分とし、リン酸アルミニウムを適当量含有させたものを作製して、そのぬれ角を調べ、本実施の形態と同様の温度で焼き付け、これを比較例１として製作した。
【０１６４】
表３に本発明品及び比較例１のぬれ角、剥離面積、衝撃接着強度、引っ張り付着強さ、放電耐量特性、課電寿命特性、耐湿特性を示す。
【０１６５】
【表３】

【０１６６】
供試試料は各々８ｐ用意した。
【０１６７】
ここで、剥離面積とは非直線抵抗体の外観、即ち電圧非直線抵抗体の高抵抗層１３が焼結体１１から剥離した面積の総和を示す。
【０１６８】
衝撃接着強度はデュポン式による耐衝撃性試験（ＪＩＳ K5400 8.3 参照）に基づいて行い、試験片はテストピースＰ２を用い、質量５００±１∋の重りを一定の高さから落下させて高低抗層面が割れ、剥離が生じない高さ位置の平均をプロットする。
【０１６９】
高抵抗層の引っ張り付着強さはＪＩＳ K5400 8.7 に基づき行った。ここでは試験片としてテストピースＰ２を用いた。引っ張り強さは平均値をプロットする。
【０１７０】
放電耐量特性は４／１０μｓのインパルスを５分間隔で２回通電し、破壊及び沿面閃絡が起きるまで４０ｋＡから２０ｋＡずつ電流値を上昇させていった。
【０１７１】
課電寿命特性は周囲温度１２０℃、課電率９５％（ＡＣピーク値）の条件で行い、初期漏れ電流値Ｉ０とＴ時間後の漏れ電流値Ｉｔの比Ｉｔ／Ｉ０が１．１を越える時間を測定した。
【０１７２】
耐湿試験は、周囲温度を２０℃にし、試験槽内を一定湿度に保つためにデシケータ内に塩化カリウム水溶液を浸す。この場合、相対湿度は約８５％になるように調湿し、電圧非直線抵抗体をデシケータ内に放置しておく。そして、６０時間後、電圧非直線抵抗のＤＣ１μＡの電圧値Ｖ₆₀を測定し、初期電圧値Ｖ₀からの変化率を求めた。ここで変化率（％）は（Ｖ₆₀−Ｖ₀）×１００／Ｖ₀として計算した。
【０１７３】
表３から分かることは、本実施の形態に示したようにＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分とし、リン酸アルミニウムとリン酸マンガンを適当量に調整した高抵抗剤は比較例に比べ、ぬれ角度が小さいことである。
【０１７４】
さらに、リン酸アルミニウムとリン酸マンガンを適当量に調整することによってぬれ角度を最適化することができる。ぬれ角度が６０°以下であれば、剥離面積は１００ｍｍ以下となり、衝撃接着強度も５０ｍｍ以上、引っ張り付着強さは０．８ＭＰａ以上と向上するが、さらに高抵抗膜の厚さが５０〜２００μｍであるものは、衝撃接着強度、引っ張り付着強さも強く、放電耐量特性も良好であることが分かる。
【０１７５】
また、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分とし、リン酸アルミニウムとリン酸マンガンを適当量に調整した高抵抗剤は比較例に比べ、課電寿命、耐湿特性のいずれも優れている。
【０１７６】
第１０の実施の形態では、第９の実施の形態で示したぬれ角度３０°の高抵抗剤に、Ｆｅ₂Ｏ₃を適量含有させたものと、ＭｎＦｅ₂Ｏ₄を適量含有させたものをそれぞれ焼き付けて高低抗層を形成させた。また、その上にさらにＳｉＯ₂、Ａｌ₂Ｏ₃を主成分とした非晶質の高抵抗剤を塗布した後焼き付けて非晶質の高抵抗膜４を形成したものも製作した。
【０１７７】
比較例として第９の実施の形態で示したぬれ角度３０°の高抵抗剤からなる高低抗層にＳｉＯ₂、Ａｌ₂Ｏ₃を主成分とした非晶質の高抵抗剤を塗布し、焼き付けた非直線抵抗体（比較例２）とＡｌ₂Ｏ₃を主成分とし、リン酸アルミニウムを適当量含有させたものから構成される高抵抗層にＳｉＯ₂、Ａｌ₂Ｏ₃を主成分とした非晶質の高抵抗剤を塗布したものを１００〜３５０℃焼き付けた非直線抵抗体（比較例３）を作製した。
【０１７８】
ここで、高抵抗層の厚さはどれも一定になるように塗布量を調整している。
【０１７９】
表５に本発明品及び比較例２、比較例３のＦｅ₂Ｏ₃添加量、ＭｎＦｅ₂Ｏ₄添加量、非晶質の高抵抗膜の有無、放電耐量特性、課電寿命特性、耐湿特性を示す。
【０１８０】
【表４】

【０１８１】
表５から分かることは、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分とし、リン酸アルミニウムとリン酸マンガンを適当量に調整した高抵抗剤にＦｅ₂ Ｏ₃ が適量含有させたものと、ＭｎＦｅ₂Ｏ₄を適量含有させたものは耐湿特性が大きく向上するがＦｅ₂Ｏ₃が０．２〜５ｗｔ％又はＭｎＦｅ₂Ｏ₄を１〜１０ｗｔ％から外れると放電耐量特性が低下したり、耐湿特性が低下したりする。また、Ｆｅ₂Ｏ₃とＭｎＦｅ₂Ｏ₄が上記範囲内であれば両者を同時に用いても影響は無い。
【０１８２】
また、これらの高低抗層上にさらにＳｉＯ₂、Ａｌ₂Ｏ₃を主成分とした非晶質の高低抗層を形成したものはさらに耐湿特性が向上する。
【０１８３】
次に本発明の第１１の実施の形態を説明する。
【０１８４】
側面高抵抗剤中のリン酸アルミニウム塩及びとリン酸マンガン塩の添加量を調整して、高抵抗層中のＡｌＰＯ₄，Ｍｎ₄（Ｐ₂Ｏ₇）₃の重量％及び焼き付け温度について検討した。さらに、非晶質の高抵抗膜を形成させた時の焼き付け温度についても検討した。その結果を表４に示す。
【０１８５】
【表５】

【０１８６】
表４から分かることは、Ｍｎ ₄ （Ｐ ₂ Ｏ ₇ ） ₃ の添加量が０．５〜３ｗｔ％の範囲内にある場合、放電耐量特性や課電寿命特性、耐湿試験は比較例に比べ良好な特性を示すが、さらに高抵抗層の焼き付け温度を１５０〜６００℃、非晶質の高低抗膜を１５０〜３５０℃で行えばさらに良好な特性を得ることができる。
【０１８７】
また、ＡｌＰＯ₄が５〜２０ｗｔ％から外れると放電耐量は定価することが分かる。これはＡｌＰＯ₄が上記範囲から外れると付着強さが定価するためと考えられる。
【０１８８】
第１１の実施の形態に示すように、焼き付け温度が高いと、課電寿命特性が低下する傾向にある。これら高い温度で焼き付けを行うと焼結体の結晶相が相転移を起こすためである。そのため、焼き付け温度はなるべく低い温度で焼き付けることが望ましい。
【０１８９】
この他、本発明は次のようにしてもよい。
【０１９０】
本発明品においては高抵抗層の主成分がＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を用いているが、これは焼結体との熱膨脹係数を合わせるためである。即ち、素体に大きなサージエネルギーが注入されると急激温度上昇に伴うため、素体と高抵抗層との熱膨脹差が大きいと、高抵抗層が素体から剥がれ、放電耐量特性が低下してしまう。
【０１９１】
高抵抗層の主成分にＡｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を用いると２０〜２００℃の範囲において、素体と高抵抗層の熱膨脹係数の差が±２．０×１０^-6／℃になり、他の金属酸化物を用いるより、安定した高抵抗層が得られる。
【０１９２】
なお、本発明は上記し且つ図面に示す実施の形態に限定されたるものではなく、その要旨を変更しない範囲内で適宜変更して実施できるものである。
【０１９３】
例えば、本実施の形態では、酸化亜鉛を主成分とする焼結体の側面に、Ａｌ₆Ｓｉ₂Ｏ₁₃（ムライト）を主成分とし、ＡｌＰＯ₄を５．０〜２０ｗｔ％、Ｍｎ₄（Ｐ₂Ｏ₇）₃を０．５〜３ｗｔ％を含む側面抵抗層について述べたが、Ｍｎ₄（Ｐ₂Ｏ₇）₃に代わりにＭｎ ₂ ＰＯ ₇ ，Ｍｇ ₃ （ＰＯ _４ ） _２ ，Ｃａ（ＰＯ₃）₂を加えても同様の効果を示すことが確認されている。
【０１９４】
以上説明した本発明の第９の実施の形態乃至第１１の実施の形態によれば、より良好で安定した放電耐量特性と耐特性劣化の双方に優れたセラミック素子を用いた電圧非直線抵抗体を得ることができる。
【０１９５】
【発明の効果】
以上述べたように本発明によれば、接着強度が高く優れた耐電圧性能を発揮し得る高抵抗層を形成することにより、雷インパルスや過電圧等のサージに対する保護能力を向上させることができる電圧非直線抵抗体及びその製造方法を提供できる。
【図面の簡単な説明】
【図１】本発明の第１乃至第８の実施の形態における電圧非直線抵抗体を示す断面図。
【図２】本発明の第２の実施の形態の電圧非直線抵抗体において、第１及び第２の高抵抗層の厚みと過電圧保護能力の関係を示したグラフ。
【図３】本発明の第３の実施の形態の電圧非直線抵抗体において、第１の高抵抗層を形成する工程のうち、混合スラリーを作る混合工程でフェライト及び酸化鉄の平均粒径と過電圧保護能力の関係を示したグラフ。
【図４】本発明の第４の実施の形態の電圧非直線抵抗体において、第１の高抵抗層を形成する工程のうち、フェライト及び酸化鉄の添加後から、塗布及び焼付け終了までの時間と過電圧保護能力の関係を示したグラフ。
【図５】本発明の第５の実施の形態の電圧非直線抵抗体において、第１の高抵抗層形成時の焼き付け温度と過電圧保護能力の関係を示したグラフ。
【図６】本発明の第６の実施の形態の電圧非直線抵抗体において、第１の高抵抗層形成時の焼き付け昇温速度と過電圧保護能力の関係を示したグラフ。
【図７】本発明の第７の実施の形態の電圧非直線抵抗体において、第２の高抵抗層形成時の焼き付け温度と過電圧保護能力の関係を示したグラフ。
【図８】本発明の第８の実施の形態の電圧非直線抵抗体において、第２の高抵抗層形成時の焼き付け昇温速度と過電圧保護能力の関係を示したグラフ。
【図９】本発明の第９乃至第１１の実施の形態における電圧非直線抵抗体を示す断面図。
【符号の説明】
１，１１…焼結体
２，１２…電極
３，１３…第１の高抵抗層
４，１４…第２の高抵抗層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a voltage non-linear resistor used in an overvoltage protection device for protecting a power system, for example, and a manufacturing method thereof, and more particularly to a voltage non-linear resistor having a high resistance layer and a manufacturing method thereof.
[0002]
[Prior art]
In general, in a power system, an overvoltage protection device such as a lightning arrester or a surge absorber is used to remove the overvoltage superimposed on a normal voltage and protect the power system.
[0003]
In this overvoltage protection device, a voltage nonlinear resistor is mainly used. The voltage non-linear resistor is a resistor having a characteristic that exhibits a substantially insulating characteristic at a normal voltage and has a relatively low resistance when an overvoltage is applied.
[0004]
Such a voltage non-linear resistor is mainly composed of ZnO (zinc oxide), and is mixed, granulated and molded by adding at least one metal oxide as an additive in order to obtain non-linear resistance characteristics. Thereafter, a sintered body obtained by sintering is provided.
[0005]
In addition, in order to prevent flash-over from the side surface during surge absorption, a high resistance component paste coating or glass coating is applied to the side surface of the sintered body and then baked by heat treatment to provide high resistance. Forming a layer.
[0006]
[Problems to be solved by the invention]
In recent years, with the growth of power demand and the development of a highly information-oriented society, stable and inexpensive power supply is strongly demanded. In response to this, there is an increasing demand for high reliability and miniaturization in overvoltage protection devices.
[0007]
Recently, in order to meet such requirements, the voltage value per unit thickness of the voltage non-linear resistor is increased to keep the height dimension low, and further, the energy absorption capacity is improved to reduce the diameter. Miniaturization of linear resistors is being promoted.
[0008]
However, in the conventional voltage nonlinear resistor, when the high resistance layer is bonded to the side surface of the sintered body with an adhesive, the high resistance layer is easily peeled off from the sintered body due to a decrease in adhesive strength. Even if the resistance layer partially peels from the sintered body, there is a problem that the withstand voltage performance is lowered.
[0009]
Therefore, it has been difficult to meet the protection capability against surges such as lightning impulse and overvoltage required when the voltage nonlinear resistor is downsized by increasing the voltage per unit thickness or reducing the diameter.
[0010]
The present invention has been made to solve the above-mentioned problems, and protects against surges such as lightning impulse and overvoltage by forming a high resistance layer that has high adhesive strength and can exhibit excellent withstand voltage performance. An object of the present invention is to provide a voltage nonlinear resistor capable of improving the capability and a method for manufacturing the same.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, in the present invention, a voltage nonlinear resistor is obtained by the following means and manufacturing method.
[0012]
The invention corresponding to claim 1 is a voltage non-linear resistor comprising a sintered body containing zinc oxide as a main component and having a high resistance layer on a side surface of the sintered body, wherein the high resistance layer is made of Al.₆Si₂O₁₃(Mullite) as the main component, at least AlPO_Four(Aluminum orthophosphate) 1.0-25 wt%, MnFe₂O_Four(Ferrite) 0.1 to 15 wt%, Fe₂O_ThreeIt is formed of a component containing 0.1 to 15 wt% of (iron oxide).
[0013]
In the voltage non-linear resistor of the invention corresponding to claim 1, the high resistance layer can be strongly bonded to the side surface of the sintered body, and the withstand voltage performance is improved. And can exhibit excellent protection ability.
[0014]
The invention corresponding to claim 2 is the voltage non-linear resistor of the invention corresponding to claim 1, wherein the high-resistance layer is used as a first high-resistance layer, and SiO 2 is further formed thereon.₂(Silica) or Al₂O_Three(Alumina) or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5An amorphous second high resistance layer mainly composed of (organosilicate) is formed.
[0015]
In the voltage nonlinear resistor of the invention corresponding to claim 2, the non-voltage second resistor of the invention corresponding to claim 1 is formed by forming an amorphous second high resistance layer on the first high resistance layer. Compared to the linear resistor, the withstand voltage performance in the high resistance layer can be further enhanced.
[0016]
According to a third aspect of the present invention, in the voltage nonlinear resistor of the first or second aspect of the present invention, the high resistance layer has a thickness of 10 μm to 1 mm.
[0017]
In the voltage non-linear resistor of the invention corresponding to claim 3, by limiting the thickness of the high resistance layer to 10 μm to 1 mm, it is possible to ensure both appropriate adhesive strength and good withstand voltage performance. .
[0018]
According to a fourth aspect of the present invention, there is provided a method for manufacturing a voltage nonlinear resistor according to any one of the first to third aspects of the present invention, wherein Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is added, mixed to form a mixed slurry, an application step of applying the mixed slurry to the side surface of the sintered body, and a baking step of baking the mixed slurry. A high resistance layer is formed.
[0019]
In the method of manufacturing a voltage non-linear resistor according to the invention corresponding to claim 4, Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is added and mixed to make a mixed slurry, and this is applied to the side of the sintered body and baked to produce Al.₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite) and Fe₂O_ThreeA voltage nonlinear resistor in which a first high resistance layer containing (iron oxide) is formed and strongly bonded to the side surface of the sintered body can be manufactured.
[0020]
According to a fifth aspect of the present invention, in the method for manufacturing a voltage non-linear resistor according to the fourth aspect of the present invention, when the first high resistance layer is formed, an average particle size is 0.01 in the mixing step. MnFe that is 10 μm₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is used.
[0021]
In the method of manufacturing a voltage nonlinear resistor according to the invention corresponding to claim 5, MnFe₂O_Four(Ferrite) and Fe₂O_ThreeBy limiting the average particle diameter of (iron oxide) to 0.01 to 10 μm, the high resistance layer can maintain appropriate uniformity and can have an excellent withstand voltage performance.
[0022]
According to a sixth aspect of the present invention, in the method for manufacturing a voltage non-linear resistor according to the fourth or fifth aspect of the present invention, in the case where the first high resistance layer is formed, 100 hours after the completion of the mixing step. The coating process and the baking process are finished within the range.
[0023]
In the method for manufacturing a voltage non-linear resistor according to the invention according to claim 6, the adhesive strength of the first high resistance layer is increased by terminating the coating step and the baking step within 100 hours from the end of the mixing step. A voltage non-linear resistor can be manufactured before it decreases.
[0024]
The invention corresponding to claim 7 is the method for producing a voltage non-linear resistor according to any one of claims 4 to 6, wherein when the first high resistance layer is formed, the baking step Thus, baking is performed at a maximum baking temperature of 200 ° C. to 800 ° C.
[0025]
In the method for manufacturing a voltage non-linear resistor according to the invention according to claim 7, the high resistance layer has excellent adhesive strength by baking at a maximum baking temperature in the baking step of 200 to 800 ° C. And can have excellent withstand voltage performance.
[0026]
According to an eighth aspect of the present invention, in the method for manufacturing a voltage non-linear resistor corresponding to any one of the fourth to seventh aspects, in the case where the first high resistance layer is formed, Baking is performed at a temperature rising rate of 10 ° C./hrs to 300 ° C./hrs at least from 100 ° C. to the maximum temperature.
[0027]
In the method for manufacturing a voltage non-linear resistor according to the eighth aspect of the invention, the first step is performed by baking at a baking temperature increase rate in the baking step in the range of 10 ° C./hrs to 300 ° C./hrs. The high resistance layer can have an excellent adhesive strength and can have an excellent withstand voltage performance.
[0028]
The invention corresponding to claim 9 is the method for producing a voltage non-linear resistor according to any one of claims 2 to 8, wherein₂(Silica) or Al₂O_Three(Alumina), SiOCH_ThreeAn aqueous solution containing (alkoxysilane), isopropanol, n-butanol, silicon surfactant and acetic acid as components is applied to the side surface of the sintered body on which the first high resistance layer is formed and baked to form a second A high resistance layer is formed.
[0029]
In the method of manufacturing a voltage non-linear resistor according to the invention corresponding to claim 9, SiO 2₂(Silica) or Al₂O_Three(Alumina) or SiO₂And CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5By forming an amorphous second high resistance layer containing (organosilicate) as a main component, a non-linear resistor with further improved withstand voltage characteristics can be manufactured.
[0030]
The invention corresponding to claim 10 is the method of manufacturing a voltage non-linear resistor according to claim 9, wherein the baking maximum temperature is 50 ° C. to 50 ° C. in the baking step when the second high resistance layer is formed. Bake in the range of 800 ° C.
[0031]
In the method for manufacturing a voltage non-linear resistor according to the invention corresponding to claim 10, by baking at a maximum baking temperature in the baking step of the second high resistance layer in the range of 50 to 800 ° C., excellent Withstand voltage performance can be realized.
[0032]
According to an eleventh aspect of the present invention, in the method for manufacturing a voltage non-linear resistor according to the ninth or tenth aspect of the present invention, in the case of forming the second high-resistance layer, at least during baking, Baking is performed at a rate of temperature increase from 30 ° C. to the highest baking temperature in the range of 10 ° C./hrs to 300 ° C./hrs.
[0033]
In the voltage nonlinear resistor manufacturing method of the invention corresponding to claim 11, the baking temperature rising rate in the baking step of the second high resistance layer 4 is in the range of 10 ° C./hrs to 300 ° C./hrs. By performing the baking, an excellent withstand voltage performance can be realized.
[0034]
  Reference Example 1On the side of the sintered body mainly composed of zinc oxide, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four5.0 to 20 wt% and Mn₂PO₇Or Mn_Four(P₂O₇)_ThreeAnd having a high resistance layer containing 0.5 to 3 wt%.
[0035]
  Reference example 2On the side of the sintered body mainly composed of zinc oxide, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four5.0 to 20 wt% and Mg_Three(PO_Four)₂And having a high resistance layer containing 0.5 to 3 wt%.
[0036]
  Reference example 3On the side of the sintered body mainly composed of zinc oxide, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four5.0-20 w% and Ca (PO_Three)₂And having a high resistance layer containing 0.5 to 3 wt%.
[0037]
  Reference Example 4 is one of Reference Example 1 to Reference Example 3 aboveIn the voltage non-linear resistor, the high resistance layer has TiO₂Or Fe₂O_ThreeContains 0.2 to 5 wt%.
[0038]
    Reference Example 5 is one of Reference Example 1 to Reference Example 3 aboveIn the voltage non-linear resistor, the high resistance layer has MnFe₂O_FourIs contained in an amount of 1 to 10 wt%.
[0039]
  Reference Example 6 is one of Reference Examples 1 to 5 above.In the voltage nonlinear resistor, SiO is further formed on the high resistance layer.₂, Al₂O_ThreeIt has an amorphous high-resistance film containing as a main component.
[0040]
  Therefore,According to Reference Example 1 to Reference Example 6 above,A voltage non-linear resistor that has greatly improved adhesion strength between the side of the sintered body and the high-resistance layer, provides stable quality to the external environment, and has both excellent discharge resistance characteristics and deterioration resistance characteristics. Obtainable.
[0041]
  Where aboveFeatures of Reference Example 1 to Reference Example 6It is as follows when the function and effect are described.
[0042]
  In order to form a high resistance layer,Like any of Reference Example 1 to Reference Example 3On the side of the sintered body mainly composed of zinc oxide, Al₆Si₂O₁₃(Mullite) as the main component, a high resistance agent containing at least one of aluminum phosphate, manganese phosphate, magnesium phosphate, and calcium phosphate is applied and baked in a temperature range of 150 to 600 ° C. A high resistance layer is formed.
[0043]
At this time, by applying the high resistance agent to the side surface of the sintered body, it is possible to approach the distance working between the side surface portion of the sintered body by the action of wetting, but other phosphates are added to the aluminum phosphate. Addition increases the action of wetting, so that the adhesive strength can be increased. In order to improve wettability, the adhesive strength can be increased by appropriately adjusting the mixing ratio of other phosphates to aluminum phosphate.
[0044]
Moreover, characteristic deterioration with respect to a high humidity atmosphere is mentioned as a 2nd effect | action. In the case of a high resistance layer formed by baking a high resistance agent using only aluminum phosphate, a part of the unreacted aluminum phosphate is ionized and left in a high humidity atmosphere with a relative humidity of 85%, for example. In other words, since the surface of the high resistance layer has a relatively porous structure, moisture is absorbed through the pores and aggregation is likely to occur at the neck portion on the particle surface.
[0045]
As a result, it is considered that a uniform electric field layer is formed between the counter electrodes, whereby the electrical conductivity is increased and the characteristics are deteriorated.
[0046]
On the other hand, the addition of other phosphates to aluminum phosphate has the effect of suppressing ionization of a part of the unreacted aluminum phosphate, and the characteristics do not deteriorate even in a high humidity atmosphere.
[0047]
  And alsoIn Reference Example 4TiO, which is a metal oxide₂Or Fe₂O_ThreeThe same effect can be expected by adding. This is because the metal oxide acts as a kind of catalyst and accelerates the curing reaction of the high resistance agent.
[0048]
  further,In Reference Example 5, MnFe₂O_FourIt is considered that the same action is exerted by entering the relatively porous structure portion of the high resistance layer by adding.
[0049]
  In Reference Example 6, Reference Examples 1 to 5On top of the high resistance layer, SiO₂, Al₂O_ThreeSince the amorphous high resistance film has a water generating action at the same time as entering the relatively porous structure portion of the high resistance layer by forming an amorphous high resistance film mainly composed of It is thought that the same effect is exerted by covering the side surface of the sintered body.
[0050]
On the other hand, in order to increase the adhesive force, it is necessary to match the thermal expansion coefficients of the sintered body and the high resistance agent in addition to improving the wettability of the high resistance agent to the side surface portion of the sintered body. When the difference between the thermal expansion coefficients of the sintered body and the high resistance agent is too large, peeling occurs during baking of the high resistance agent, or peeling occurs because excessive heat is generated during the discharge withstand capability.
[0051]
In this case, when the base material is a sintered body containing zinc oxide as a main component, Al is contained in the high resistance agent.₆Si₂O₁₃Is preferably used as the main component.
[0052]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
[0053]
As shown in FIG. 1, the voltage non-linear resistor includes a sintered body 1, and first and second high resistance layers 3 and 4 are formed on the side surface portion of the sintered body 1, and both flat surfaces are formed. Polishing to a predetermined thickness and forming the aluminum electrode 2 on the polished surface.
[0054]
The embodiments of the voltage non-linear resistor according to the present invention are all related to the first and second high resistance layers 3 and 4, but before that, the manufacturing process of the sintered body 1 will be described first.
[0055]
That is, for the main component ZnO (zinc oxide), Bi₂O_Three(Bismuth oxide), MnO₂(Manganese oxide) 0.5 mol%, Co₂O_Three(Cobalt oxide), NiO (nickel oxide), Sb₂O_ThreeA raw material is prepared by adding 1 mol% of (antimony trioxide).
[0056]
Next, this raw material is mixed with water and organic binders in a mixing device to form a mixed slurry. This mixed slurry is sprayed and granulated with a spray dryer, and a predetermined weight of the granulated powder is put into a mold and pressed with a predetermined pressure, and formed into a disk shape having a diameter of, for example, 80 mm. Then, in order to remove the added organic binders in advance, heat treatment is performed at 400 to 500 ° C. in the air, and further, firing is performed at 1200 ° C. to obtain the sintered body 1.
[0057]
Next, a first embodiment of the first and second side resistance layers formed on the side surface of the sintered body 1 manufactured as described above will be described.
[0058]
The first high resistance layer 3 is made of Al.₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate) 1.0-25 wt%, MnFe₂O_Four(Ferrite) 0.1 to 15 wt%, Fe₂O_ThreeIt is comprised with the component which contains 0.1-15 wt% of (iron oxide). The first high resistance layer 3 having such a component structure is formed by the following process.
[0059]
First, Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃A slurry containing mullite as a main component is made, and MnFe is added to this slurry.₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is added and mixed to make a mixed slurry (mixing step). Subsequently, this mixed slurry is applied to the side surface of the sintered body 1 (application step). Then, the mixed slurry is baked to form the first high resistance layer 3 (baking step).
[0060]
The second high resistance layer 4 formed on the first high resistance layer 3 is made of SiO 2₂(Silica) or Al₂O_Three(Alumina) or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5(Organosilicate) is the main component. Such a second high resistance layer 4 is formed by the following process.
[0061]
First, SiO₂(Silica) or Al₂O_Three(Alumina) and SiOCH_ThreeAn aqueous solution containing (alkoxysilane), isopropanol, n-butanol, silicon surfactant and acetic acid as components is applied to the surface of the first high resistance layer 3 formed on the side surface of the sintered body 1 (application step). ). And the apply | coated aqueous solution is baked and the 2nd high resistance layer 4 is formed (baking process).
[0062]
Where Al₆Si₂O₁₃AlPO whose main component is mullite and whose content is different from the above_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite) and Fe₂O_ThreeSeveral types of voltage non-linear resistors in which the first high resistance layer is formed by baking with (iron oxide) as a subcomponent are prepared as samples, and these samples are compared with the sample corresponding to the first embodiment. .
[0063]
Also, AlPO having a content corresponding to the first embodiment_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite) and Fe₂O_ThreeOn the surface of the first high resistance layer 3 containing (iron oxide) as a subcomponent, SiO₂(Silica) or Al₂O_Three(Alumina) or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5A sample in which the second high-resistance layer 4 is formed using (organosilicate) as a main component is compared with a sample in which the second high-resistance layer is not formed.
[0064]
That is, AlPO_Four(Aluminum orthophosphate) is 0.1, 1, 25, 30 wt%, MnFe₂O_Four(Ferrite) is 0.1,1,15,20 wt%, Fe₂O_ThreeA voltage non-linear resistor in which several kinds of first high resistance layers 3 were formed so that the content of (iron oxide) was 0.01, 0.1, 15, and 20 wt was produced.
[0065]
Also, AlPO having a content corresponding to the first embodiment_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite) and Fe₂O_ThreeOn the surface of the first high resistance layer 3 formed with (iron oxide) as a subsidiary component, SiO 2₂(Silica) or Al₂O_Three(Alumina) or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5A sample in which the second high resistance layer 4 was formed using (organosilicate) as a main component and a sample in which the second high resistance layer was not formed were prepared.
[0066]
An impulse current having an 8/20 μs waveform was applied to each of the samples thus prepared in steps of 60 kA to 10 kA, and the current value at which the sample was broken was measured to evaluate the overvoltage protection capability of each sample. . The results are shown in Tables 1 and 2.
[0067]
[Table 1]

[0068]
[Table 2]

[0069]
Sample corresponding to the first embodiment, that is, AlPO_FourThe content of (aluminum orthophosphate) is 1,25 wt%, MnFe₂O_Four(Ferrite) content is 0.1,15 wt%, Fe₂O_ThreeSamples having the first high resistance layer 3 having a content of (iron oxide) of 0.1,15 wt% (sample numbers 22, 27, 30, 31, 42, 43, 46, 47 in Tables 1 and 2) ) Was broken by applying a high impulse current of 170 kA or more.
[0070]
On the other hand, the samples other than the above were broken by applying a relatively low impulse current of 100 to 130 kA. Also, AlPO having a content corresponding to the first embodiment_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite) and Fe₂O_ThreeOn the surface of the first high resistance layer 3 formed with (iron oxide) as a subcomponent, SiO 2₂(Silica) or Al₂O_Three(Alumina) or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5Samples (23 to 26, 48 to 51 in Tables 1 and 2) in which the second high resistance layer 4 is formed with (organosilicate) as the main component are broken by applying an extremely high impulse current of 190 to 200 kA. It was.
[0071]
As is clear from the above results, the first embodiment is made of Al.₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate) 1.0-25 wt%, MnFe₂O_Four(Ferrite) 0.1 to 15 wt%, Fe₂O_ThreeBy including the first high resistance layer 3 containing 0.1 to 15 wt% of (iron oxide), the first high resistance layer 3 can be strongly bonded to the side surface of the sintered body 1, and withstand voltage performance Will improve.
[0072]
Therefore, it can be seen that the voltage non-linear resistor dramatically improves the protection capability against the impulse current. In addition, SiO₂(Silica) or Al₂O_Three(Aluminum or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5It can be seen that by forming the second high-resistance layer 4 containing (organosilicate) as a main component, the ability to protect against impulse current is dramatically improved.
[0073]
As described above, as the component of the first high resistance layer 3, Al₆Si₂O₁₃(Mullite), AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeAlthough an example using only (iron oxide) as a component has been described, other TiO₂In addition to (titanium oxide), when adding a component for improving the adhesive strength of the high resistance layer, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeIt has been confirmed that the best impulse tolerance can be realized when the content of (iron oxide) is in the above range.
[0074]
Next, a second embodiment will be described.
[0075]
In the second embodiment, the thicknesses of the first and second high resistance layers 3 and 4 formed in the first embodiment are set to 10 μm to 1 mm.
[0076]
Here, several types of voltage nonlinear resistors having different thicknesses of the first and second high resistance layers 3 and 4 are manufactured, and the sample corresponding to the second embodiment is compared with other samples. Now, the function and effect of the second embodiment will be described.
[0077]
First Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeA first high-resistance layer 3 containing 5 wt% (iron oxide) is formed, and SiO 2 is formed thereon.₂(Silica) and CH_ThreeSiO_1.5An amorphous second high resistance layer 4 mainly composed of (organosilicate) is formed. At that time, samples were prepared by adjusting the thicknesses of the high resistance layers 3 and 4 to 0.1, 1, 10, 100, 500 μm and 1.2 mm, respectively, and a total of 7 types of samples were prepared.
[0078]
For each sample produced as described above, an impulse current having an 8/20 μs waveform is applied to each sample in increments of 60 kA to 10 kA, the current value at which the sample breaks is measured, and the overvoltage protection capability of each sample is evaluated. It was. The result is shown in FIG. Samples corresponding to the second embodiment, that is, samples having the thicknesses of the first and second high resistance layers 3 and 4 of 1, 10, 100, 500 μm and 1 mm, are broken by applying an impulse current of 190 kA or more. It was.
[0079]
In contrast, the sample not corresponding to the second embodiment, that is, the sample having a high resistance layer thickness of 0.1 μm and 2 mm, was broken by applying an impulse current as low as 100 to 130 kA. This is because, if the thicknesses of the first and second high resistance layers 3 and 4 are too small, it is impossible to obtain an excellent impulse current protection capability. If the thickness is too thick, the adhesive strength of the first and second high resistance layers 3 and 4 decreases as the thickness increases, and it is impossible to obtain an excellent impulse current protection capability. ing.
[0080]
From the above results, in the second embodiment, by setting the thickness of the first and second high resistance layers 3 and 4 to 10 μm to 1 mm, both appropriate adhesive strength and good withstand voltage performance can be obtained. Can be ensured, and the ability to protect the impulse current can be greatly improved.
[0081]
Next, a third embodiment will be described.
[0082]
In the third embodiment, among the steps of forming the first high resistance layer 3 in the first embodiment, MnFe₂O_Four(Ferrite) and Fe₂O_ThreeIn the mixing step of adding (iron oxide) to form a mixed slurry, MnFe having an average particle size of 0.01 to 10 μm₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is used.
[0083]
Here, in order to explain the operational effects of the third embodiment, MnFe₂O_Four(Ferrite) and Fe₂O_ThreeSeveral kinds of voltage non-linear resistors having different average particle diameters of (iron oxide) are produced.
[0084]
First, as in the second embodiment, Al₆SiO₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeA first high resistance layer 3 containing 5 wt% of (iron oxide) is formed. In forming the first high resistance layer 3, MnFe having an average particle diameter of 0.001, 0.01, 0.1, 1, 10 and 20 μm₂O_Four(Ferrite), Fe₂O_ThreeTwelve types of samples using (iron oxide) were prepared.
[0085]
For each of these samples, SiO2 (silica) and CH on the first high resistance layer 3._ThreeSiO_1.5An amorphous second high resistance layer 4 mainly composed of (organosilicate) was formed and used as an evaluation sample.
[0086]
By applying an impulse current of 8/20 μs waveform to each sample produced as described above in increments of 60 kA to 10 kA, and measuring the current value when the sample is destroyed, the overvoltage protection capability of each sample is measured. Evaluation was performed.
[0087]
The result is shown in FIG. A sample corresponding to the third embodiment, that is, MnFe₂O_Four(Ferrite) and Fe₂O_ThreeSamples with an average particle size of (iron oxide) of 0.01 to 10 μm were broken by applying an impulse current of 190 kA or more, but samples with an average particle size outside the above range were 100 to 130 kA. Destruction occurred by applying an impulse current.
[0088]
In general, the finer the average particle diameter of the powder, the worse the dispersibility. Therefore, the uniformity of the first high resistance layer 3 is deteriorated, and the average particle diameter is 0.01 μm of MnFe.₂O_Four(Ferrite) and Fe₂O_ThreeSamples using (iron oxide) do not have excellent protection against impulse current.
[0089]
On the other hand, if the average particle size of the powder to be used is coarse, it tends to be unevenly deposited in the high resistance layer component, so MnFe having an average particle size of 20 μm.₂O_Four(Ferrite) and Fe₂O_ThreeA sample using (iron oxide) does not have an excellent protection capability against impulse current.
[0090]
From the above results, in the third embodiment, MnFe having an average particle diameter in the range of 0.01 to 10 μm.₂O_Four(Ferrite) and Fe₂O_ThreeBy adding (iron oxide), the first high-resistance layer 3 can maintain appropriate uniformity, exhibits excellent withstand voltage performance, and has excellent ability to protect against impulse current.
[0091]
Next, a fourth embodiment will be described.
[0092]
In the fourth embodiment, when the first high resistance layer 3 is formed in the first embodiment, Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_ThreeAfter the mixing step of adding (iron oxide) to form a mixed slurry is completed, the coating step and the baking step are completed within 100 hours.
[0093]
Here, in order to explain the operation and effect of the fourth embodiment, the following sample was prepared.
[0094]
Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_ThreeIn addition, 5 wt% of each (iron oxide) was added and applied to the side surface of the sintered body 1 by spray coating and baking.₂O_Four(Ferrite) and Fe₂O_ThreeAfter adding (iron oxide), seven types of samples that were applied and baked after 1, 12, 24, 50, 100, 120, and 180 hours were prepared.
[0095]
For each of these samples, a SiO 2 layer on the first high resistance layer 3 is used.₂(Silica) and CH_ThreeSiO_1.5An amorphous second high resistance layer 4 mainly composed of (organosilicate) was formed and used as an evaluation sample.
[0096]
By applying an impulse current of 8/20 μs waveform to each sample produced as described above in increments of 60 kA to 10 kA, and measuring the current value when the sample breaks, the overvoltage protection capability of each sample is measured. Evaluation was performed.
[0097]
The result is shown in FIG. The sample corresponding to the fourth embodiment, that is, the slurry, MnFe₂O_Four(Ferrite) and Fe₂O_ThreeThe sample that was applied and baked within 100 hours after the addition of (iron oxide) was broken by applying an impulse current of 180 kA or more.
[0098]
In contrast, the slurry is MnFe₂O_Four(Ferrite) and Fe₂O_ThreeSamples applied and baked after 120 and 180 hours after addition of (iron oxide) were broken by applying an impulse current of 100 to 130 kA. The reason why the breakdown current value is small is considered as follows.
[0099]
Al (H₂PO_Four)_ThreeMnFe in (primary aluminum phosphate)₂O_Four(Ferrite) and Fe₂O_ThreeWhen (iron oxide) is added, the added MnFe₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) gradually dissolves and Al (H₂PO_Four)_ThreePrevents normal curing reaction of (primary aluminum phosphate).
[0100]
Therefore, the adhesive strength of the first high resistance layer 3 gradually decreases, and the first high resistance layer 3 adheres to the side surface of the sintered body 1 even if coating and baking are performed after 120 and 180 hours have passed since the addition. However, the withstand voltage performance was lowered and the protection capability against the impulse current was not excellent.
[0101]
From the above results, in the fourth embodiment, MnFe₂O_Four(Ferrite) and Fe₂O_ThreeBy applying and baking within 100 hours after adding (iron oxide), it can be formed on the side surface of the sintered body 1 before the adhesive strength of the first high resistance layer 3 is reduced. As a result, the voltage nonlinear resistor according to the fourth embodiment has an excellent protection capability against the impulse current.
[0102]
Next, a fifth embodiment will be described.
[0103]
In the fifth embodiment, when the first high resistance layer 3 is formed in the first embodiment, Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_ThreeAfter applying the mixed slurry in which (iron oxide) is added and mixed, when baking is performed, the maximum baking temperature is 200 ° C to 800 ° C.
[0104]
Here, the following sample was prepared in order to explain the function and effect of the fifth embodiment.
[0105]
Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is added at 5 wt% each, and when applying and baking the side surface of the sintered body 1 by spray application, baking is performed at a maximum temperature of 150, 200, 400, 600, 800 and 1000 ° C. Five types of samples were prepared.
[0106]
For each of these samples, a SiO 2 layer on the first high resistance layer 3 is used.₂(Silica) and CH_ThreeSiO_1.5An amorphous second high resistance layer 4 mainly composed of (organosilicate) was formed and used as an evaluation sample.
[0107]
An impulse current having an 8/20 μs waveform was applied to each sample produced as described above in increments of 60 kA to 10 kA, the current value at which the sample was broken was measured, and the overvoltage protection capability of each sample was evaluated.
[0108]
The result is shown in FIG. The sample corresponding to the fifth embodiment, that is, the sample that was baked at a maximum baking temperature of the first high resistance layer 3 in the range of 200 to 800 ° C., was broken by applying an impulse current of 190 kA or more.
[0109]
In contrast, the samples baked at 150 ° C. and 1000 ° C. were broken by applying an impulse current of 100 to 110 kA. The reason why the breakdown current value is small is considered as follows.
[0110]
At baking temperatures below 200 ° C., Al (H₂PO_Four)_ThreeSince the curing reaction of (primary aluminum phosphate) does not occur, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeSince the first high resistance layer 3 containing (iron oxide) was not formed, the degree of adhesion to the side surface of the sintered body 1 was poor, the withstand voltage was reduced, and the ability to protect against impulse current was excellent. did not become.
[0111]
Also, at baking temperatures higher than 800 ° C., Al (H₂PO_Four)_ThreeSince the normal curing reaction of (primary aluminum phosphate) cannot be caused, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeThe first high resistance layer 3 containing (iron oxide) is not formed. For this reason, the degree of adhesion to the side surface of the sintered body 1 was poor, the withstand voltage was lowered, and the ability to protect against impulse current was not excellent.
[0112]
From the above results, in the fifth embodiment, the highest temperature at which the first high-resistance layer 3 is baked is 200 to 800 ° C., so that the first high-resistance layer 3 is formed in the state where the adhesive strength is highest. It can be formed on the side surface of the sintered body 1. Thereby, the voltage non-linear resistor according to the fifth embodiment has an excellent protection capability against the impulse current.
[0113]
Next, a sixth embodiment will be described.
[0114]
In the sixth embodiment, when the first high resistance layer 3 is formed in the first embodiment, Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_ThreeAfter applying the mixed slurry in which (iron oxide) is added and mixed, when baking is performed, the temperature rising rate is at least 100 ° C. to the maximum temperature at 10 ° C./hrs to 300 ° C./hrs.
[0115]
Here, the following sample was prepared in order to explain the function and effect of the fifth embodiment.
[0116]
Al (H₂PO_Four)_Three(Primary aluminum phosphate) and Al₆Si₂O₁₃(Mullite) as the main component₂O_Four(Ferrite) and Fe₂O_Three(Iron oxide) is added in an amount of 5 wt%, and the temperature rise rate during baking is 5,10,100,200,300 and 400 ° C./hrs in applying and baking the side surface of the sintered body 1 by spray application. Six types of samples were baked.
[0117]
For each of these samples, a SiO 2 layer on the first high resistance layer 3 is used.₂(Silica) and CH_ThreeSiO_1.5An amorphous second high resistance layer 4 mainly composed of (organosilicate) was formed and used as an evaluation sample.
[0118]
An impulse current having a waveform of 8/20 μs was applied to each sample produced in this manner in increments of 60 kA to 10 kA, the current value at which the sample was broken was measured, and the overvoltage protection capability of each sample was evaluated. .
[0119]
The result is shown in FIG. In the sample corresponding to the sixth embodiment, that is, the sample subjected to baking at a baking temperature increase rate of 10 to 300 ° C./hrs in the first high resistance layer, destruction occurs by applying an impulse current of 190 kA or more. It was.
[0120]
In contrast, the samples baked at 5 ° C./hrs and 400 ° C./hrs were broken by applying an impulse current of 100 to 130 kA. The reason why the breakdown current value is small is considered as follows.
[0121]
By baking the first high resistance layer 3 at a temperature rising rate of 10 to 300 ° C./hrs, an optimum Al (H₂PO_Four)_ThreeThe curing reaction rate of (first aluminum phosphate) can be given, the degree of adhesion to the side surface of the sintered body 1 is extremely high, the withstand voltage is improved, and the ability to protect the impulse current is excellent.
[0122]
On the other hand, when the temperature rising rate becomes faster than 300 ° C./hrs, Al (H₂PO_Four)_ThreeThe curing reaction of (first aluminum phosphate) proceeds rapidly, and the degree of adhesion to the side surface of the sintered body 1 decreases.
[0123]
Further, at a baking temperature increase rate of less than 10 ° C./hhrs, Al (H₂PO_Four)_ThreeThe curing reaction of (primary aluminum phosphate) proceeds slowly, and Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeSince the first high resistance layer 3 containing (iron oxide) was not completely formed, the degree of adhesion to the side surface of the sintered body 1 was deteriorated, so the withstand voltage was lowered and the impulse discharge withstand characteristics were lowered. .
[0124]
From the above results, in the sixth embodiment, the first high-resistance layer 3 is baked at a rate of 10 to 300 ° C./hrs at which the first high-resistance layer 3 is baked. It is possible to form the layer 3 on the side surface of the sintered body 1. As a result, the voltage nonlinear resistor according to the sixth embodiment has an excellent protection capability against the impulse current.
[0125]
Next, a seventh embodiment will be described.
[0126]
In the seventh embodiment, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_ThreeOn the first high resistance layer 3 containing 5 wt% of (iron oxide), SiO 2₂(Silica), SiOCH_ThreeBy applying and baking an aqueous solution containing (alkoxylane), isopropanol, n-butanol, silicon surfactant and acetic acid as components, SiO₂(Silica) and CH_ThreeSiO_1.5When forming the 2nd high resistance layer 4 which has (organosilicate) as a main component, the baking maximum temperature of the 2nd high resistance layer 4 is performed in the range of 50-800 degreeC.
[0127]
Here, in order to explain the function and effect of the seventh embodiment, the following sample was prepared.
[0128]
On the first high resistance layer 3, SiO₂(Silica) and SiOCH_Three(Alkoxylane), isopropanol, n-butanol, silicon surfactant, and acetic acid as a component are applied and baked, and the maximum temperature during baking is 30,50,100,300,600,800, Seven types of samples baked at 1000 ° C. were prepared.
[0129]
An impulse current having a waveform of 8/20 μs was applied to each sample produced in this manner in increments of 60 kA to 10 kA, the current value at which the sample was broken was measured, and the overvoltage protection capability of each sample was evaluated. .
[0130]
The result is shown in FIG. The sample corresponding to the seventh embodiment and the sample that was baked at the maximum baking temperature of the second high-resistance layer 4 in the range of 50 to 800 ° C. were broken by the application of an impulse current of 190 kA or more.
[0131]
In contrast, the samples baked at 30 ° C. and 1000 ° C. were broken by applying an impulse current of 100 to 110 kA. The reason why the breakdown current value is small is considered as follows.
[0132]
Since the evaporation of isopropanol and n-butanol does not occur at a baking temperature of less than 50 ° C., the second high resistance layer 4 mainly composed of SiO 2 (silica) and CH 3 SiO 1.5 (organosilicate) was not formed. Good withstand voltage performance could not be obtained, and an excellent protection capability against impulse current could not be obtained.
[0133]
In addition, when the baking temperature exceeds 800 ° C., the evaporation of isopropanol and n-butanol occurs abruptly.₂(Silica) and CHSiO_1.5Since the second high-resistance layer 4 containing (organosilicate) as a main component was not formed in a normal state, good withstand voltage performance could not be obtained, and an excellent protection capability against impulse current could not be obtained. .
[0134]
From the above results, in the seventh embodiment, the second high resistance layer 4 having good withstand voltage performance is obtained by performing the maximum temperature for baking the second high resistance layer 4 at 50 to 800 ° C. It can be formed on the side surface of the sintered body 1 to which the first high resistance layer 3 is applied. As a result, the voltage nonlinear resistor according to the seventh embodiment has an excellent protection capability against the impulse current.
[0135]
As described above, as an example in which the baking temperature of the second high resistance layer 4 is limited, SiO 2₂(Silica) and CHSiO_1.5The case where the second high resistance layer 4 mainly composed of (organosilicate) is formed is described as a representative example.₂(Silica) or Al₂O_Three(Alumina) or Al₂O_Three(Alumina) and CHSiO_1.5It has been confirmed that even when the second high-resistance layer 4 containing (organosilicate) as a main component is formed, the best impulse resistance can be realized in the above baking temperature range.
[0136]
Next, an eighth embodiment of the present invention will be described.
[0137]
In the eighth embodiment, Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate), MnFe₂O_Four(Ferrite), Fe₂O_Three(SiO 2), SiOCH (SiO 2) on the first high resistance layer 3 containing 5 wt% of each (iron oxide)_ThreeBy applying and baking an aqueous solution containing (alkoxylane), isopropanol, n-butanol, silicon surfactant and acetic acid as components, SiO₂(Silica) and CH_ThreeSiO_1.5When forming the second high-resistance layer 4 containing (organosilicate) as a main component, the temperature increase rate of at least 30 ° C. to the maximum temperature during baking of the second high-resistance layer 4 is 10 to 300 ° C./hrs. It is performed in the range of.
[0138]
Here, in order to explain the function and effect of the eighth embodiment, the following sample was prepared.
[0139]
On the first high resistance layer 3, SiO₂(Silica) and SiOCH_Three(Alkoxylane), isopropanol, n-butanol, silicon surfactant, and acetic acid as a component are applied and baked. When baking, the maximum temperature during baking is 400 ° C. Six types of samples were prepared by baking at a heating rate of 5, 10, 100, 200, 300 and 400 ° C./hrs.
[0140]
While applying an impulse current having a waveform of 8/20 μs to each sample produced in this manner in steps of 60 kA to 10 kA, the current value at which the sample breaks is measured to evaluate the overvoltage protection capability of each sample. It was.
[0141]
The result is shown in FIG. The sample corresponding to the eighth embodiment and the sample baked in the range of the maximum baking temperature of the second high resistance layer 4 in the range of 10 to 300 ° C./hrs were broken by applying the impulse current of 190 kA or more. .
[0142]
In contrast, the samples baked at 5 ° C./hrs and 400 ° C./hrs were broken by applying a 100 to 130 kA impulse current. The reason why the breakdown current value is small is considered as follows.
[0143]
At a heating rate of less than 10 ° C./hrs, the reaction proceeds slowly and SiO 2₂(Silica) and CH_ThreeSIO_1.5Since the second high-resistance layer 4 containing (organosilicate) as a main component was not completely formed, good withstand voltage performance could not be obtained, and the protection capability against impulse current was lowered.
[0144]
Further, at a baking temperature exceeding 300 ° C./hrs, the evaporation of isopropanol and n-butanol abruptly occurs.₂(Silica) and CH_ThreeSIO_1.5Since the second high-resistance layer 4 containing (organosilicate) as a main component was not formed in a normal state, good withstand voltage performance was not obtained, and the ability to protect against impulse current was reduced.
[0145]
From the above results, in the eighth embodiment, the second high resistance layer having good withstand voltage performance is obtained by performing the maximum temperature for baking the second high resistance layer 4 at 10 to 300 ° C./hrs. 4 can be formed on the side surface of the sintered body 1 provided with the first high resistance layer 3. Thereby, the voltage non-linear resistor according to the eighth embodiment has an excellent protection capability against the impulse current.
[0146]
As described above, as an example in which the baking temperature of the second high resistance layer 4 is limited, SiO 2₂(Silica) and CH_ThreeSIO_1.5The case where the second high-resistance layer 4 mainly composed of (organosilicate) is formed has been described as a representative example.₂(Silica) or ALAl₂O_Three(Alumina) or Al₂O_Three(Alumina) and CH_ThreeSIO_1.5It has been confirmed that even when the second high-resistance layer 4 containing (organosilicate) as a main component is formed, the best impulse resistance can be realized in the above baking temperature range.
[0147]
As described in the first to eighth embodiments of the voltage nonlinear resistor and the manufacturing method thereof according to the present invention described above, the first high resistance formed on the side surface of the sintered body 1 Layer 3 is Al₆Si₂O₁₃(Mullite) as the main component, AlPO_Four(Aluminum orthophosphate) 1.0-25 wt%, MnFe₂O_Four(Ferrite) 0.1 to 15 wt%, Fe₂O_ThreeBy comprising a component containing 0.1 to 15 wt% of (iron oxide), the adhesive strength was high and excellent withstand voltage performance was achieved, and the ability to protect against surges such as lightning impulse overvoltage could be improved. . Furthermore, SiO 2 as the second high resistance layer 4 is formed on the first high resistance layer 3.₂(Silica) or Al₂O_Three(Alumina) or SiO₂(Silica) and CH_ThreeSiO_1.5(Organosilicate) or Al₂O_Three(Alumina) and CH_ThreeSiO_1.5By forming the amorphous second high-resistance layer 4 containing (organosilicate) as a main component, it is possible to further improve the withstand voltage performance and improve the protection capability against surges such as lightning impulse overvoltage. it can.
[0148]
Next, an embodiment of the voltage nonlinear resistor according to the present invention, which is composed of components different from those of the first to eighth embodiments described above, and a method for manufacturing the same will be described.
[0149]
In the ninth embodiment, Al is formed on the side surface of the sintered body containing zinc oxide as a main component.₆Si₂O₁₃A voltage non-linear resistor in which (Mulite) is the main component, a high resistance agent containing a manganese phosphate salt is applied to an aluminum phosphate salt, and a high resistance layer is formed by baking treatment will be described.
[0150]
FIG. 9 is a cross-sectional view of the ceramic element according to the present embodiment. As shown in FIG. 9, the sintered body 11 has a disk shape, and electrodes 12 are provided on both end faces (upper and lower surfaces of FIG. 9) of the sintered body 11.
[0151]
A first high resistance layer 13 is formed on the side surface (circumferential direction in FIG. 9) of the sintered body 11.
[0152]
Further, a second side high resistance film 14 is formed on the first high resistance layer 13.
[0153]
Here, a manufacturing process for obtaining the sintered body 11 of the ceramic element will be described.
[0154]
First, zinc oxide is prepared by adding 0.5 mol% each of bismuth oxide, manganese oxide, silicon dioxide, and chromium oxide and 1 mol% each of cobalt oxide, antimony oxide, and nickel oxide to zinc oxide (ZnO).
[0155]
Next, the raw material is mixed with water and organic binders in a mixing apparatus, and the mixture is spray granulated with a spray dryer.
[0156]
Next, this granulated powder is put into a mold and pressed, and formed into a disk having a diameter of 80 mm and a thickness of 30 mm, for example. For example, a test piece having a size of 100 mm × 100 mm × 30 mm is formed in advance.
[0157]
The molded body thus obtained is fired at a temperature of about 1200 ° C. to obtain a sintered body 11 and a test piece P1.
[0158]
Al to this test piece P1₆Si₂O₁₃(Mullite) as a main component, a high resistance agent prepared by adjusting aluminum phosphate and manganese phosphate to appropriate amounts is hung, and after examining the wetting angle, it is applied to another test piece P1 and sintered body 11, and this is applied. Baking is performed in a temperature range of 200 to 600 ° C. to form the first high resistance layer 13.
[0159]
At this time, an appropriate amount of high resistance agent is applied so that the film thickness of the first high resistance layer 13 formed on the test piece and the sintered body is constant.
[0160]
Next, in order to examine the adhesive strength, a surface perpendicular to the adhesion surface of the test piece P1 on which the first high resistance layer 13 is formed is polished to create a test piece P2 of 70 mm × 70 mm × 20 mm.
[0161]
On the other hand, both end surfaces of the sintered body 11 on which the first high resistance layer 13 is formed are polished, an aluminum electrode is sprayed, and an electrode 12 is provided to obtain a voltage nonlinear resistor.
[0162]
Here, the film thickness of the high resistance layer of the voltage nonlinear resistor and the film thickness of the test piece P2 were measured during polishing.
[0163]
As a comparative example, the same sintered body 11 and test piece P1 as those of the present invention were used, and Al₂O_ThreeWas prepared, and the wetting angle was examined and baked at the same temperature as in the present embodiment, and this was manufactured as Comparative Example 1.
[0164]
Table 3 shows the wetting angle, peeled area, impact adhesive strength, tensile adhesion strength, discharge withstand characteristics, electrical charging life characteristics, and moisture resistance characteristics of the product of the present invention and Comparative Example 1.
[0165]
[Table 3]

[0166]
8p of each test sample was prepared.
[0167]
Here, the peeled area indicates the external appearance of the non-linear resistor, that is, the total area where the high resistance layer 13 of the voltage non-linear resistor is peeled from the sintered body 11.
[0168]
The impact adhesive strength is based on the DuPont impact resistance test (see JIS K5400 8.3). The test piece is a test piece P2, and a weight of 500 ± 1 mm is dropped from a certain height to form a high and low resistance surface. Plot the average of the height positions where no cracks and no delamination occur.
[0169]
The tensile adhesion strength of the high resistance layer was determined based on JIS K5400 8.7. Here, test piece P2 was used as a test piece. Tensile strength is plotted as an average value.
[0170]
With respect to the discharge withstand characteristics, a 4/10 μs impulse was energized twice at 5-minute intervals, and the current value was increased from 40 kA to 20 kA until breakdown and creeping flashing occurred.
[0171]
The charging life characteristic is performed under the conditions of an ambient temperature of 120 ° C. and a charging rate of 95% (AC peak value), and the ratio It / I0 of the initial leakage current value I0 and the leakage current value It after T time exceeds 1.1. Time was measured.
[0172]
In the moisture resistance test, the ambient temperature is set to 20 ° C., and an aqueous potassium chloride solution is immersed in a desiccator in order to keep the inside of the test tank at a constant humidity. In this case, the relative humidity is adjusted to about 85%, and the voltage nonlinear resistor is left in the desiccator. After 60 hours, the voltage value V of DC 1 μA of the voltage nonlinear resistance₆₀, And the initial voltage value V₀The rate of change from Here, the rate of change (%) is (V₆₀-V₀) X 100 / V₀As calculated.
[0173]
As can be seen from Table 3, as shown in the present embodiment, Al₆Si₂O₁₃A high resistance agent containing (mullite) as a main component and adjusting aluminum phosphate and manganese phosphate to appropriate amounts has a smaller wetting angle than the comparative example.
[0174]
Furthermore, the wetting angle can be optimized by adjusting aluminum phosphate and manganese phosphate to appropriate amounts. If the wetting angle is 60 ° or less, the peel area is 100 mm or less, the impact adhesive strength is improved to 50 mm or more, and the tensile adhesion strength is improved to 0.8 MPa or more, but the thickness of the high resistance film is 50 to 200 μm. It can be seen that some have strong impact adhesive strength and tensile adhesion strength, and also have good discharge tolerance characteristics.
[0175]
Al₆Si₂O₁₃A high resistance agent containing (mullite) as a main component and adjusting aluminum phosphate and manganese phosphate to appropriate amounts is superior in both the electric life and humidity resistance compared to the comparative example.
[0176]
In the tenth embodiment, the high resistance agent having a wetting angle of 30 ° shown in the ninth embodiment is added to Fe.₂O_ThreeA suitable amount of MnFe₂O_FourEach of those containing an appropriate amount was baked to form a high and low resistance layer. In addition, SiO₂, Al₂O_ThreeAn amorphous high-resistance film 4 was formed by applying an amorphous high-resistance agent having a main component and then baking.
[0177]
As a comparative example, the high and low resistance layer made of a high resistance agent having a wetting angle of 30 ° shown in the ninth embodiment is made of SiO.₂, Al₂O_ThreeA non-linear resistor (Comparative Example 2) and Al coated with an amorphous high resistance agent mainly composed of₂O_ThreeIn a high resistance layer composed of a main component containing aluminum phosphate and an appropriate amount of aluminum phosphate.₂, Al₂O_ThreeA non-linear resistor (Comparative Example 3) was manufactured by baking an amorphous high-resistance agent having a main component of 100 to 350 ° C.
[0178]
Here, the coating amount is adjusted so that the thickness of the high resistance layer is constant.
[0179]
  Table 5The product of the present invention and Fe of Comparative Example 2 and Comparative Example 3₂O_ThreeAddition amount, MnFe₂O_FourAddition amount, presence / absence of amorphous high-resistance film, discharge withstand characteristics, electrical charging life characteristics, and moisture resistance characteristics are shown.
[0180]
[Table 4]

[0181]
  Table 5It can be seen from Al₆Si₂O₁₃(Mullite) as the main component, Fe is added to a high-resistance agent in which aluminum phosphate and manganese phosphate are adjusted to appropriate amounts.₂O_ThreeContaining a proper amount, and MnFe₂O_FourWhen containing a suitable amount, the moisture resistance is greatly improved, but Fe₂O_Three0.2-5 wt% or MnFe₂O_FourWhen the value is deviated from 1 to 10 wt%, the discharge withstand characteristic is deteriorated or the moisture resistance characteristic is deteriorated. Fe₂O_ThreeAnd MnFe₂O_FourIs within the above range, there is no effect even if both are used simultaneously.
[0182]
Further, on these high and low resistance layers, SiO₂, Al₂O_ThreeIn the case where an amorphous high and low resistance layer mainly composed of is formed, the moisture resistance is further improved.
[0183]
Next, an eleventh embodiment of the present invention will be described.
[0184]
  AlPO in the high resistance layer is adjusted by adjusting the amount of aluminum phosphate and manganese phosphate in the side high resistance agent._Four, Mn_Four(P₂O₇)_Three% By weight and baking temperature were examined. Furthermore, the baking temperature when the amorphous high resistance film was formed was also examined. The resultTable 4Shown in
[0185]
[Table 5]

[0186]
  Table 4From what you can seeMn _Four (P ₂ O ₇ ) _Three When the added amount is in the range of 0.5 to 3 wt%, the discharge withstand characteristics, the charging life characteristics, and the moisture resistance test show better characteristics than the comparative example, but further the baking temperature of the high resistance layer is 150 to Even better properties can be obtained if an amorphous high and low anti-resistive film is formed at 600 ° C. at 150 to 350 ° C.
[0187]
AlPO_FourIt can be seen that the discharge withstand amount is fixed when the value is out of 5 to 20 wt%. This is AlPO_FourThis is considered to be because the adhesion strength is fixed when the value is outside the above range.
[0188]
As shown in the eleventh embodiment, when the baking temperature is high, the electric charging life characteristic tends to be lowered. This is because, when baking is performed at these high temperatures, the crystal phase of the sintered body causes a phase transition. Therefore, it is desirable that the baking temperature is as low as possible.
[0189]
In addition, the present invention may be as follows.
[0190]
In the present invention, the main component of the high resistance layer is Al.₆Si₂O₁₃(Mullite) is used to match the thermal expansion coefficient with the sintered body. That is, when a large surge energy is injected into the element body, the temperature rises suddenly. Therefore, if the thermal expansion difference between the element body and the high resistance layer is large, the high resistance layer is peeled off from the element body, and the discharge withstand characteristics are reduced. End up.
[0191]
Al as main component of high resistance layer₆Si₂O₁₃When (mullite) is used, in the range of 20 to 200 ° C., the difference in thermal expansion coefficient between the element body and the high resistance layer is ± 2.0 × 10^-6/ ° C., and a stable high resistance layer can be obtained by using other metal oxides.
[0192]
The present invention is not limited to the embodiments described above and shown in the drawings, and can be implemented with appropriate modifications within a range not changing the gist thereof.
[0193]
  For example, in the present embodiment, Al is formed on the side surface of the sintered body mainly composed of zinc oxide.₆Si₂O₁₃(Mullite) as the main component, AlPO_Four5.0 to 20 wt%, Mn_Four(P₂O₇)_ThreeThe side resistance layer containing 0.5 to 3 wt% is described._Four(P₂O₇)_ThreeInstead ofMn ₂ PO ₇ ,Mg _Three (PO ₄ ) ₂ , Ca (PO_Three)₂It has been confirmed that the same effect can be obtained even if the is added.
[0194]
According to the ninth to eleventh embodiments of the present invention described above, the voltage non-linear resistor using the ceramic element having both better and stable discharge withstand characteristics and excellent characteristics deterioration. Can be obtained.
[0195]
【The invention's effect】
As described above, according to the present invention, a voltage that can improve the protection capability against surges such as lightning impulse and overvoltage by forming a high resistance layer that has high adhesive strength and can exhibit excellent withstand voltage performance. A non-linear resistor and a manufacturing method thereof can be provided.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a voltage nonlinear resistor according to first to eighth embodiments of the present invention.
FIG. 2 is a graph showing the relationship between the thicknesses of first and second high resistance layers and overvoltage protection capability in a voltage nonlinear resistor according to a second embodiment of the present invention.
FIG. 3 shows the average particle diameters of ferrite and iron oxide in the mixing step of forming the mixed slurry in the step of forming the first high resistance layer in the voltage nonlinear resistor according to the third embodiment of the present invention. A graph showing the relationship of overvoltage protection capability.
FIG. 4 shows the time from the addition of ferrite and iron oxide to the end of coating and baking in the step of forming the first high resistance layer in the voltage nonlinear resistor according to the fourth embodiment of the present invention. And graph showing the relationship between overvoltage protection capability.
FIG. 5 is a graph showing the relationship between the baking temperature and the overvoltage protection capability when the first high resistance layer is formed in the voltage nonlinear resistor according to the fifth embodiment of the present invention.
FIG. 6 is a graph showing the relationship between the baking temperature rise rate and the overvoltage protection capability when forming the first high-resistance layer in the voltage nonlinear resistor according to the sixth embodiment of the present invention.
FIG. 7 is a graph showing the relationship between the baking temperature and the overvoltage protection capability when the second high-resistance layer is formed in the voltage nonlinear resistor according to the seventh embodiment of the present invention.
FIG. 8 is a graph showing the relationship between the baking temperature rise rate and the overvoltage protection capability when forming the second high resistance layer in the voltage nonlinear resistor according to the eighth embodiment of the present invention.
FIG. 9 is a cross-sectional view showing a voltage nonlinear resistor according to ninth to eleventh embodiments of the present invention.
[Explanation of symbols]
1,11 ... Sintered body
2,12 ... Electrodes
3, 13 ... first high resistance layer
4, 14 ... second high resistance layer

Claims (11)

In a voltage non-linear resistor having a sintered body mainly composed of zinc oxide and having a high resistance layer on a side surface of the sintered body,
The high resistance layer is mainly composed of Al ₆ Si ₂ O ₁₃ (mullite), at least AlPO ₄ (aluminum orthophosphate) at 1.0 to 25 wt%, and MnFe ₂ O ₄ (ferrite) at 0.1 to 15 wt%. A voltage non-linear resistor comprising a component containing 0.1 to 15 wt% of Fe ₂ O ₃ (iron oxide). 2. The voltage non-linear resistor according to claim 1, wherein the high resistance layer is used as a first side resistance layer, and SiO ₂ (silica), Al ₂ O ₃ (alumina), SiO ₂ (silica) and CH are further formed thereon. Voltage non-linearity characterized by forming an amorphous second high resistance layer mainly composed of ₃ SiO _1.5 (organosilicate) or Al ₂ O ₃ (alumina) and CH ₃ SiO _1.5 (organosilicate) Resistor.   3. The voltage non-linear resistor according to claim 1, wherein the high resistance layer has a thickness of 10 [mu] m to 1 mm. The method for manufacturing a voltage nonlinear resistor according to any one of claims 1 to 3, wherein Al (H ₂ PO ₄ ) ₃ (first aluminum phosphate) and Al ₆ Si ₂ O ₁₃ ( A mixing step in which MnFe ₂ O ₄ (ferrite) and Fe ₂ O ₃ (iron oxide) are added to a slurry containing mullite as a main component and mixed to form a mixed slurry; A method for producing a voltage non-linear resistor, wherein the first high-resistance layer is formed by an application step of applying to a side surface and a baking step of baking the mixed slurry. 5. The method of manufacturing a voltage nonlinear resistor according to claim 4, wherein when the first high resistance layer is formed, MnFe ₂ O ₄ (ferrite) having an average particle diameter of 0.01 to 10 μm in the mixing step. And Fe ₂ O ₃ (iron oxide). A method for manufacturing a voltage non-linear resistor.   6. The method for manufacturing a voltage non-linear resistor according to claim 4, wherein the coating step and the baking step are completed within 100 hours after the mixing step. .   In the method for manufacturing a voltage non-linear resistor according to any one of claims 4 to 6, when the first high resistance layer is formed, a maximum baking temperature is 200 ° C to 800 ° C in the baking step. A method for producing a voltage non-linear resistor, wherein baking is performed in the range of ° C.   The method for manufacturing a voltage non-linear resistor according to any one of claims 4 to 7, wherein when forming the first high resistance layer, at least 100 ° C during baking is the highest in the baking step. Baking is carried out at a temperature rising rate of 10 ° C./hrs to 300 ° C./hrs. A method for producing a voltage nonlinear resistor according to any one of claims 2 to 8, wherein SiO ₂ (silica) or Al ₂ O ₃ (alumina), SiOCH ₃ (alkoxysilane), isopropanol, n -After the coating step of applying an aqueous solution containing butanol, a silicon-based surfactant and acetic acid as components to the side surface of the sintered body on which the first high-resistance layer has been formed, the second high A method for producing a voltage nonlinear resistor, comprising forming a resistance layer.   10. The method of manufacturing a voltage non-linear resistor according to claim 9, wherein when the second high resistance layer is formed, a maximum baking temperature is set in a range of 50 to 800 [deg.] C. in the baking step. Manufacturing method of linear resistor.   The method for manufacturing a voltage non-linear resistor according to claim 9 or 10, wherein when the second high resistance layer is formed, a temperature increase rate of at least 30 ° C to a maximum temperature during baking is 10 ° C / hrs to 300 ° C. / Hrs is performed in the range of the voltage non-linear resistance body characterized by the above-mentioned.

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