JPH10163009A - Manufacture of non-linear resistor dependent on voltage - Google Patents

Manufacture of non-linear resistor dependent on voltage

Info

Publication number
JPH10163009A
JPH10163009A JP8334486A JP33448696A JPH10163009A JP H10163009 A JPH10163009 A JP H10163009A JP 8334486 A JP8334486 A JP 8334486A JP 33448696 A JP33448696 A JP 33448696A JP H10163009 A JPH10163009 A JP H10163009A
Authority
JP
Japan
Prior art keywords
varistor
ceramic substrate
ceramic
voltage
roughened
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8334486A
Other languages
Japanese (ja)
Inventor
Yoji Funabiki
要次 船引
Toshiaki Murakami
俊昭 村上
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP8334486A priority Critical patent/JPH10163009A/en
Publication of JPH10163009A publication Critical patent/JPH10163009A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a varistor which prevents clearance between a ceramic substrate and an insulating resin film. SOLUTION: A method for manufacturing a varistor comprises the process of forming a ceramic substrate exhibiting properties of a varistor, the process of making the surface of the ceramic substrate coarse, the process of forming an electrode on the ceramic substrate and the process of coating the ceramic substrate with an insulating resin film. The surface of the ceramic substrate can be made coarse by corroding with a chemical agent containing hydrofluoric acid or by sand blasting or barreling.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】この発明は電圧非直線性と大
きな誘電率を備えた電圧依存非直線抵抗体(以下、「バ
リスタ」という。)の製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a voltage-dependent non-linear resistor (hereinafter, referred to as a "varistor") having voltage non-linearity and a large dielectric constant.

【0002】[0002]

【従来の技術】バリスタは構成材料によって種々のもの
があり、その製造方法はその構成材料毎に異なる。例え
ばチタン酸ストロンチウム系のバリスタは一般に次のよ
うにして製造される。
2. Description of the Related Art There are various types of varistors depending on constituent materials, and the manufacturing method differs for each constituent material. For example, a strontium titanate-based varistor is generally manufactured as follows.

【0003】まず、酸化チタン、炭酸ストロンチウム及
び炭酸カルシウムに酸化アルミニウム、酸化珪素、酸化
ニオブ、酸化イットリウムなどの添加物を微量添加し、
ボールミルで充分に混合して原料粉末を得る。
First, a small amount of additives such as aluminum oxide, silicon oxide, niobium oxide and yttrium oxide are added to titanium oxide, strontium carbonate and calcium carbonate,
The raw material powder is obtained by sufficiently mixing with a ball mill.

【0004】次に、この原料粉末に有機バインダーを加
えて造粒し、これを成形機で圧縮成形して円板状の成形
体を得る。そして、この成形体を窒素と水素ガスからな
る還元性雰囲気中で焼成し、半導体化して低抵抗になっ
たセラミック素地(焼結体)を得る。
[0004] Next, an organic binder is added to the raw material powder and granulated, and the resultant is compression-molded by a molding machine to obtain a disk-shaped molded body. Then, the molded body is fired in a reducing atmosphere composed of nitrogen and hydrogen gas to obtain a ceramic body (sintered body) which has been converted into a semiconductor and has reduced resistance.

【0005】次に、このセラミック素地を空気中で再加
熱して、セラミック素地の内部の粒界を酸化させて高抵
抗化させ、粒界バリアを形成してバリスタ特性を示すセ
ラミック素地を得る。
Next, the ceramic body is reheated in the air to oxidize the grain boundaries inside the ceramic body to increase the resistance, and form a grain boundary barrier to obtain a ceramic body exhibiting varistor characteristics.

【0006】次に、このセラミック素地の表と裏の面に
銀ペーストを塗布して焼き付け、形成された電極層にリ
ード端子を各々接続し、これらをリード端子の一部を残
して絶縁性樹脂で被覆し、バリスタを得る。
Next, a silver paste is applied to the front and back surfaces of the ceramic base and baked, lead terminals are respectively connected to the formed electrode layers, and these are left in an insulating resin while leaving a part of the lead terminals. To obtain a varistor.

【0007】[0007]

【発明が解決しようとする課題】ところで、上述したよ
うな方法によってバリスタを製造した場合、セラミック
素地と絶縁性樹脂被膜との間に隙間が形成されてしまう
ことがある。そして、この隙間が形成されたバリスタは
セラミック素地面の絶縁抵抗が低下してしまい、異常電
圧吸収時にこの隙間内でセラミック素地面に沿って放電
が生じ、所望のバリスタ特性が得られないという問題を
生じてしまう。
When a varistor is manufactured by the above-described method, a gap may be formed between the ceramic substrate and the insulating resin film. The varistor with the gap formed has a problem that the insulation resistance of the ceramic base is reduced, and discharge occurs along the ceramic base in the gap when abnormal voltage is absorbed, so that desired varistor characteristics cannot be obtained. Will occur.

【0008】本発明はセラミック素地と絶縁性樹脂被膜
との間に隙間が生じないようにしたバリスタの製造方法
を提供することを目的とする。
An object of the present invention is to provide a method for manufacturing a varistor in which no gap is formed between the ceramic substrate and the insulating resin film.

【0009】[0009]

【課題を解決するための手段】この発明は、バリスタ特
性を示すセラミック素地を形成する工程と、該セラミッ
ク素地に電極を形成する工程と、該セラミック素地を絶
縁性樹脂被膜で被覆する工程とを備えたバリスタの製造
方法において、該セラミック素地の表面を粗面化するこ
とにより上記課題を解決した。
The present invention comprises a step of forming a ceramic base exhibiting varistor characteristics, a step of forming an electrode on the ceramic base, and a step of coating the ceramic base with an insulating resin film. In a method for manufacturing a varistor provided with the above, the above problem is solved by roughening the surface of the ceramic base.

【0010】ここで、セラミック素地の表面を粗面化す
る方法としては、例えばセラミック素地を弗酸を含む化
学薬品に浸漬して表面を腐食させる方法、セラミック素
地の表面をサンドブラストで削る方法、セラミック素地
の表面をバレルで削る方法を採用することができる。
Here, as a method of roughening the surface of the ceramic body, for example, a method of immersing the ceramic body in a chemical containing hydrofluoric acid to corrode the surface, a method of sandblasting the surface of the ceramic body, A method of shaving the surface of the base with a barrel can be employed.

【0011】[0011]

【実施例】【Example】

実施例1 まず、酸化チタン、炭酸ストロンチウム及び炭酸カルシ
ウムを秤量し、これらに酸化アルミニウム、酸化珪素、
酸化ニオブ、酸化イットリウムなどの添加物を微量添加
し、ボールミルで充分に混合して原料粉末を得た。
Example 1 First, titanium oxide, strontium carbonate and calcium carbonate were weighed, and aluminum oxide, silicon oxide,
Additives such as niobium oxide and yttrium oxide were added in a small amount and mixed sufficiently with a ball mill to obtain a raw material powder.

【0012】次に、この原料粉末に有機バインダーを加
えて造粒し、これを成形機で圧縮成形して直径9mm、
厚さ1.5mmの円板状の成形体を得た。そして、この
成形体を窒素と水素ガスからなる還元性雰囲気中で焼成
し、半導体化して低抵抗になったセラミック素地(焼結
体)を得た。
Next, an organic binder is added to the raw material powder to form a granule, which is compression-molded by a molding machine to have a diameter of 9 mm.
A disk-shaped molded body having a thickness of 1.5 mm was obtained. Then, the formed body was fired in a reducing atmosphere composed of nitrogen and hydrogen gas to obtain a ceramic base (sintered body) having a semiconductor and reduced resistance.

【0013】次に、このセラミック素地を空気中で再加
熱し、セラミック素地の内部の粒界を酸化させて高抵抗
化させて、粒界バリアを形成してバリスタ特性を示すセ
ラミック素地を得た。
Next, the ceramic body is reheated in the air to oxidize the grain boundaries inside the ceramic body to increase the resistance, thereby forming a grain boundary barrier to obtain a ceramic body exhibiting varistor characteristics. .

【0014】次に、このセラミック素地を常温でHF:
HNO3 :H2 O=1:5:50の溶液を用いてバレル
浸漬を1分間行なってセラミック素地の表面をわずかに
腐食させて粗面化した。ここで、セラミック素地の表面
粗度Raを調べたところ、表1に示す通りであった。
Next, this ceramic substrate is heated at room temperature in HF:
Barrel immersion was performed for 1 minute using a solution of HNO 3 : H 2 O = 1: 5: 50 to slightly corrode and roughen the surface of the ceramic substrate. Here, when the surface roughness Ra of the ceramic base was examined, it was as shown in Table 1.

【0015】次に、このセラミック素地を水洗して乾燥
させ、セラミック素地の表と裏の面に銀ペーストを塗布
して焼き付け、形成された電極層にリード端子を各々接
続し、これらをリード端子の一部を残して絶縁性樹脂で
被覆し、バリスタを得た。
Next, the ceramic base is washed with water and dried, and a silver paste is applied to the front and back surfaces of the ceramic base and baked, and lead terminals are connected to the formed electrode layers, and these are connected to the lead terminals. Was covered with an insulating resin except for a part of the varistor.

【0016】次に、このバリスタのバリスタ電圧V1
非直線指数α、静電容量C、サージ耐量ΔV1 を調べた
ところ、表1に示す通りであった。
Next, the varistor voltage V 1 of this varistor
When the non-linear index α, the capacitance C, and the surge resistance ΔV 1 were examined, the results were as shown in Table 1.

【0017】実施例2 HCl:H2 O=1:20に溶解促進剤として硫酸化高
級アルコールの界面活性剤を1重量%加えた溶液にセラ
ミック素地を40℃で30分間バレル浸漬して表面を粗
面化した以外は実施例1と全く同様にしてバリスタを作
成した。そして、このバリスタのバリスタ電圧V1 、非
直線指数α、静電容量C、サージ耐量ΔV1 を調べたと
ころ、表1に示す通りであった。
Example 2 A ceramic base was immersed in a solution obtained by adding 1% by weight of a sulfated higher alcohol surfactant as a dissolution promoter to HCl: H 2 O = 1: 20 at 40 ° C. for 30 minutes to form a surface. A varistor was prepared in exactly the same manner as in Example 1, except that the surface was roughened. The varistor voltage V 1 , the non-linear index α, the capacitance C, and the surge withstand voltage ΔV 1 of this varistor were examined.

【0018】実施例3 セラミック素地の表面に粒度20メッシュの砂粒(ケイ
砂)を圧縮空気を用いて吹き付け衝突させて、セラミッ
ク素地の表面を粗面化させた以外は実施例1と全く同様
にしてバリスタを作成した。そして、このバリスタのバ
リスタ電圧V1、非直線指数α、静電容量C、サージ耐
量ΔV1 を調べたところ、表1に示す通りであった。
Example 3 The same procedure as in Example 1 was carried out except that the surface of the ceramic substrate was roughened by blowing sand particles (silica sand) having a particle size of 20 mesh onto the surface of the ceramic substrate using compressed air to impinge on the surface. Created a varistor. The varistor voltage V 1 , the non-linear index α, the capacitance C, and the surge withstand voltage ΔV 1 of this varistor were examined.

【0019】実施例4 セラミック素地と研磨剤(酸化アルミニウム:30μ)
を六角バレル内にバレル容積比で50%、磁器と研磨比
で1:6になるように投入し、バレルの回転数を14r
pmに保ち10分間処理して、セラミック素地の表面を
粗面化した以外は実施例1と全く同様にしてバリスタを
作成した。そして、このバリスタのバリスタ電圧V1
非直線指数α、静電容量C、サージ耐量ΔV1 を調べた
ところ、表1に示す通りであった。
Example 4 Ceramic body and abrasive (aluminum oxide: 30 μ)
Into a hexagonal barrel so that the barrel volume ratio is 50% and the porcelain and polishing ratio is 1: 6, and the rotational speed of the barrel is 14r.
A varistor was prepared in exactly the same manner as in Example 1 except that the surface of the ceramic substrate was roughened while maintaining the varnish at pm for 10 minutes. And the varistor voltage V 1 of this varistor,
When the non-linear index α, the capacitance C, and the surge resistance ΔV 1 were examined, the results were as shown in Table 1.

【0020】比較例1 セラミック素地の表面を粗面化しなかった以外は実施例
1と全く同様にしてバリスタを作成した。そして、この
バリスタのバリスタ電圧V1 、非直線指数α、静電容量
C、サージ耐量ΔV1 を調べたところ、表1に示す通り
であった。
Comparative Example 1 A varistor was prepared in exactly the same manner as in Example 1 except that the surface of the ceramic substrate was not roughened. The varistor voltage V 1 , the non-linear index α, the capacitance C, and the surge withstand voltage ΔV 1 of this varistor were examined.

【0021】[0021]

【表1】 [Table 1]

【0022】表1に示された結果から、セラミック素地
の表面を粗面化しないもののサージ耐量が800Aであ
るのに対し、粗面化した実施例1〜4のサージ耐量は1
000〜1200Aであり、セラミック素地の表面を粗
面化した方がサージ耐量が向上していることがわかる。
From the results shown in Table 1, although the surface of the ceramic substrate was not roughened, the surge withstand capability was 800 A, but the surge withstand capability of the roughened Examples 1-4 was 1
000 to 1200 A, and it can be seen that the surge resistance is improved when the surface of the ceramic substrate is roughened.

【0023】[0023]

【発明の効果】この発明によれば、セラミック素地に絶
縁性樹脂被膜が充分に密着し、セラミック素地の表面の
電気抵抗が高まり、電極間の絶縁抵抗が高まるので、バ
リスタ特性が改善され、異常電圧吸収時にセラミック素
地面に沿って放電を生ずることがなくなるという効果が
ある。
According to the present invention, the insulating resin film is sufficiently adhered to the ceramic substrate, the electric resistance of the surface of the ceramic substrate is increased, and the insulation resistance between the electrodes is increased. There is an effect that no discharge is generated along the ceramic ground when the voltage is absorbed.

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 バリスタ特性を有するセラミック素地を
形成する工程と、該セラミック素地の表面を粗面化する
工程と、該セラミック素地に電極を形成する工程と、該
セラミック素地を絶縁性樹脂被膜で被覆する工程とを備
えたことを特徴とする電圧依存非直線抵抗体の製造方
法。
1. A step of forming a ceramic base having varistor characteristics, a step of roughening the surface of the ceramic base, a step of forming electrodes on the ceramic base, and a step of forming the ceramic base with an insulating resin film. A method of manufacturing a voltage-dependent nonlinear resistor comprising a step of coating.
【請求項2】 前記セラミック素地の表面を弗酸を含む
化学薬品で腐食させることにより粗面化することを特徴
とする請求項1に記載の方法。
2. The method according to claim 1, wherein the surface of the ceramic substrate is roughened by corrosion with a chemical containing hydrofluoric acid.
【請求項3】 前記セラミック素地の表面をサンドブラ
ストにより粗面化することを特徴とする請求項1に記載
の方法。
3. The method according to claim 1, wherein the surface of the ceramic substrate is roughened by sandblasting.
【請求項4】 前記セラミック素地の表面をバレルによ
り粗面化することを特徴とする請求項1に記載の方法。
4. The method according to claim 1, wherein the surface of the ceramic substrate is roughened by a barrel.
JP8334486A 1996-11-29 1996-11-29 Manufacture of non-linear resistor dependent on voltage Pending JPH10163009A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8334486A JPH10163009A (en) 1996-11-29 1996-11-29 Manufacture of non-linear resistor dependent on voltage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8334486A JPH10163009A (en) 1996-11-29 1996-11-29 Manufacture of non-linear resistor dependent on voltage

Publications (1)

Publication Number Publication Date
JPH10163009A true JPH10163009A (en) 1998-06-19

Family

ID=18277942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8334486A Pending JPH10163009A (en) 1996-11-29 1996-11-29 Manufacture of non-linear resistor dependent on voltage

Country Status (1)

Country Link
JP (1) JPH10163009A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8854599B2 (en) 2003-08-29 2014-10-07 Nikon Corporation Liquid recovery apparatus, exposure apparatus, exposure method, and device manufacturing method
CN114709038A (en) * 2022-04-25 2022-07-05 西安石油大学 Piezoresistor matrix chip, high-energy surge protector valve plate and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8854599B2 (en) 2003-08-29 2014-10-07 Nikon Corporation Liquid recovery apparatus, exposure apparatus, exposure method, and device manufacturing method
CN114709038A (en) * 2022-04-25 2022-07-05 西安石油大学 Piezoresistor matrix chip, high-energy surge protector valve plate and manufacturing method thereof

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