JP4128586B2 - Method for manufacturing display device - Google Patents

Description

  The present invention relates to a display device using a transparent conductive film as an electrode of a display unit such as a liquid crystal display device. In particular, the present invention relates to improving the electrode structure and obtaining a display device with excellent reliability.

  Conventionally, a plasma display, a liquid crystal display device, etc. are known as a display device using a transparent conductive film for a display portion. These display devices use the properties of electro-optic materials such as liquid crystal materials to control the voltage, current, etc., thereby changing the optical properties of the electro-optic materials such as translucency, light reflection and scattering. And getting the display.

  In the active matrix liquid crystal display device, row wiring and column wiring are formed on a first substrate using a multilayer wiring technique, and a pixel electrode made of a transparent conductive film is provided at a portion where these wirings intersect, An active element such as a thin film transistor (TFT) is connected to the pixel electrode. On the other hand, a counter electrode made of a transparent conductive film is provided on the second substrate. The first substrate and the second substrate are arranged so that the pixel electrode and the counter electrode face each other, and a liquid crystal material is sealed between these substrates.

  When a voltage / current is applied between an arbitrary row wiring on the first substrate and an arbitrary column wiring on the second substrate, the potential and current of the pixel electrode at the intersecting portion are controlled by the switching TFT. As a result, the translucency, light reflection / scattering properties, etc. of the liquid crystal material between the electrodes are selectively changed, so that matrix display is possible. On the other hand, in the plasma display, a gas is sealed between the first substrate and the second substrate, and the characteristic is that the gas is turned into plasma by applying a high electric field between the substrates to emit light.

  In any case, since the display portion needs transparency, a transparent conductive film is used for the pixel electrode. In general, ITO (Indium Tin Oxide) mainly composed of indium oxide is used for the transparent conductive film, and the pixel electrode has a structure in which the ITO film is in direct contact with the semiconductor layer of the TFT. Have. The semiconductor layer of the TFT is composed of silicon (amorphous silicon or polysilicon).

  FIG. 6 is a state diagram of the oxidation potential of the metal used for the electrode / wiring of the TFT. As shown in FIG. 6, since the oxidation potential of silicon is lower than that of indium, indium is reduced at the interface between silicon and ITO at a high temperature, and the oxidation-reduction equilibrium proceeds in the direction in which silicon is oxidized. As a result, silicon oxide, which is an insulator, is generated at the interface, resulting in an increase in contact resistance and display failure.

  Moreover, tin oxide and zinc oxide are known as low-resistance transparent conductive films other than ITO. However, as shown in FIG. 6, since any metal oxide has a lower oxidation potential than silicon, an oxidation-reduction phenomenon occurs in which silicon is oxidized by heating as in the case of ITO.

  Titanium oxide is known as a transparent conductive film having a lower oxidation potential than silicon, but its resistance is too high for use as a pixel electrode.

  In general, in a TFT manufacturing process, a heat treatment in a hydrogen atmosphere, so-called hydrogenation treatment, is performed as a final step. Thereby, silicon defects in the semiconductor layer are compensated, and the electrical characteristics of the TFT, particularly the off-current characteristics can be improved. In order to obtain an off-current characteristic suitable for the TFT connected to the pixel electrode, it is preferable to heat at a temperature of 300 to 400 ° C.

  However, if the heat treatment is performed in the above temperature range, as described above, the contact resistance between the semiconductor layer made of silicon and the pixel electrode made of ITO, tin oxide or the like increases, so that the hydrogenation is performed at a sufficiently high temperature. Processing cannot be performed, and the off-current characteristics of the TFT in the pixel portion cannot be sufficiently improved. A large off-state current of the TFT in the pixel portion means that image data cannot be held reliably, leading to a decrease in the reliability of the display device.

  Conventionally, as a method for preventing the oxidation of silicon, a method of preventing the oxidation of silicon by forming a pad with titanium nitride, titanium or the like serving as a barrier layer in the contact portion has been adopted. However, in order to form the pad, various processes such as film formation of the pad material, resist patterning, and etching are required, so that the process is greatly increased. Further, the provision of the pad reduces the aperture ratio of the pixel portion.

  An object of the present invention is to solve the above-described problems and provide a display device having a pixel electrode having a small contact resistance with silicon and capable of heat treatment at a high temperature without increasing the number of steps. is there.

In order to solve the above problems, the configuration of the display device according to the present invention is as follows.
In a pixel portion having a thin film transistor using silicon as a semiconductor layer and a pixel electrode connected to the thin film transistor,
The pixel electrode has a first transparent conductive film electrically connected to the semiconductor layer, and a second transparent conductive film disposed on the first transparent conductive film,
The first transparent conductive film is made of an oxide of a first metal having an oxidation potential lower than that of silicon, and the second transparent conductive film is an oxide layer of a second metal having an oxidation potential higher than that of silicon. It is characterized by comprising.

The configuration of a display device according to another invention is as follows:
In a pixel portion having a thin film transistor using silicon as a semiconductor layer and a pixel electrode connected to the thin film transistor,
The pixel electrode has a first transparent conductive film electrically connected to the semiconductor layer, and a second transparent conductive film disposed on the first transparent conductive film,
The first transparent conductive film is composed of an oxide layer in which a first metal having an oxidation potential lower than that of silicon is oxidized by heating,
The second transparent conductive film is composed of an oxide layer of a second metal having an oxidation potential higher than that of silicon.

Further, the structure of a method for manufacturing a display device according to another invention is as follows.
Forming a thin film transistor using silicon as a semiconductor layer;
Forming a pixel electrode electrically connected to the semiconductor layer of the thin film transistor, and a method for manufacturing a display device comprising:
The pixel electrode forming step includes:
Forming a first transparent conductive film layer made of an oxide layer of a first metal having an oxidation potential lower than that of silicon so as to be in electrical contact with the semiconductor layer;
Forming a second transparent conductive film layer made of a second metal oxide having a higher oxidation potential than silicon on the surface of the first metal oxide film;
It is characterized by having.

The structure of a method for manufacturing a display device according to another invention is as follows.
Forming a thin film transistor using silicon as a semiconductor layer;
Forming a pixel electrode electrically connected to a semiconductor layer of the thin film transistor, and a method for manufacturing a display device comprising:
The pixel electrode forming step includes:
Forming a metal layer having a lower oxidation potential than silicon so as to be in electrical contact with the semiconductor layer;
Forming a transparent conductive film layer made of a metal oxide having a higher oxidation potential than silicon on the surface of the metal film;
A step of making the metal layer transparent by heat treatment;
It is characterized by having.

  In the display device according to the present invention, the pixel electrode is a two-layer film made of a transparent conductor, the transparent conductor on the interface side with silicon has a lower oxidation potential than silicon, and the upper transparent conductor is oxidized more than silicon. A metal oxide layer with high potential was used. As a result, the metal oxide in contact with silicon at the interface between the pixel electrode and the silicon layer has a lower oxidation potential than silicon and the second transparent conductive film, and is thus thermally stable.

  For this reason, since the interface with the silicon pixel electrode is not oxidized by heat treatment such as hydrogenation treatment, an increase in contact resistance can be prevented. Accordingly, since the hydrogenation treatment can be performed at a high temperature, the electrical characteristics of the pixel TFT, particularly the off-current characteristics can be improved. For this reason, the reliability of the display device can be improved.

  Furthermore, since it is not necessary to manufacture an opaque pad, the aperture ratio of the pixel does not decrease. In addition, since the pixel electrode having a two-layer structure according to the present invention can be formed without adding a new patterning step, the number of steps does not increase significantly.

  In the basic configuration of the display device of the present invention, an electrical wiring, a switching TFT, and a pixel electrode connected to the TFT are arranged on a transparent substrate. Further, in order to be completed as a display device, an electrode, a liquid crystal material, or other electro-optical material disposed opposite to the pixel electrode is necessary.

The embodiment of the present invention will be described with reference to FIGS.
Silicon is used for the semiconductor layer 103 of the TFT, and the pixel electrode 114 is electrically connected to the silicon layer 103. The pixel electrode 114 is composed of two layers of transparent conductive films 114a and 114b. The first transparent conductive film 114a in contact with silicon is made of a metal oxide having a lower oxidation potential than silicon, and the second transparent conductive film 114b formed on the metal oxide has an oxidation potential higher than that of silicon. Of the second metal oxide layer.

  In the above configuration, the metal oxide in contact with silicon at the interface between the pixel electrode and the silicon layer has a lower oxidation potential than that of silicon and the second transparent conductive film, and thus is thermally stabilized. Yes. Therefore, since the interface with the silicon pixel electrode is not oxidized by heat treatment such as hydrogenation treatment, an increase in contact resistance can be prevented.

  For example, titanium oxide can be used for the first transparent conductive film in contact with silicon from the state diagram shown in FIG. In addition, a widely used ITO film can be used for the second transparent conductive film. Since the titanium oxide thin film is transparent and conductive, it does not need to be patterned in the form of a pad as in the conventional example, and can have the same shape as the pixel electrode.

There are two methods for forming a pixel electrode having the above structure.
In the first manufacturing method, after forming the first transparent conductive film layer made of the first metal oxide layer having a lower oxidation potential than silicon so as to be in electrical contact with the semiconductor layer made of silicon, A method of forming a second transparent conductive film layer made of a second metal oxide having a higher oxidation potential than silicon on the surface of the one metal oxide film can be employed.

FIG. 2F and FIG. 3F illustrate an embodiment of a first manufacturing method.
In the pixel electrode manufacturing process, first, after forming the titanium oxide film 114a, the ITO film 114b is formed and patterned to form the pixel electrode 114.

  As a second method for manufacturing the pixel electrode, a metal layer having an oxidation potential lower than that of silicon is formed so as to be in electrical contact with the semiconductor layer of the TFT, and an oxidation potential higher than that of silicon is formed on the surface of the metal film. It is possible to adopt a method of forming a transparent conductive film layer made of a high metal oxide and making the metal layer transparent by heat treatment.

4F and 5G illustrate an embodiment of a second manufacturing method.
A titanium film 219a is formed as a metal layer having an oxidation potential lower than that of silicon, and then an ITO film 219b is formed as a metal oxide having an oxidation potential higher than that of silicon. Finally, by heating, the titanium film 219a is oxidized and transformed into a transparent and conductive acid 219b titanium oxide film 219c. As a result, a pixel electrode 219 made of a two-layered transparent conductive film such as a titanium oxide film 219c and an ITO film is obtained.

  In this heating step, since titanium has an oxidation potential lower than that of silicon, only titanium is oxidized and silicon oxide is not formed at the silicon interface. Therefore, an increase in contact resistance between silicon and the pixel electrode is suppressed. Note that the step of making the metal layer transparent can be performed at the same time as annealing of the silicon constituting the semiconductor layer if the heat treatment step is performed in a hydrogen atmosphere.

  In order to evaluate the pixel electrode obtained by the present invention, the present inventors measured the contact resistance between the pixel electrode and silicon and the transmittance of the titanium / ITO laminated film.

  FIG. 7 is a graph of the contact resistance between the pixel electrode and polycrystalline silicon with respect to the heat treatment temperature. The conventional pixel electrode has 40 contact chains made of a single-layer ITO film having a thickness of 120 nm and the thickness of the present invention. Resistance was measured for each of 40 contact chains of pixel electrodes formed of a two-layer film of a 5 nm thick titanium film and a 120 nm thick ITO film. The heat treatment temperature was room temperature (no heat treatment) and 300 ° C. (in a hydrogen atmosphere).

  As shown in FIG. 7, the pixel electrode made of a single ITO film is heated to increase the contact resistance. On the other hand, the contact resistance of the pixel electrode made of a titanium / ITO two-layer film hardly changes before and after heating. This indicates that titanium functions as a silicon oxidation stopper.

  FIG. 8 is a graph of the transmittance of a pixel electrode made of a titanium / ITO layer with respect to the thickness of titanium, and shows the measurement results for a pixel electrode that has been subjected to hydrogenation treatment at 300 ° C. and an untreated pixel electrode. In addition, the film thickness of ITO is 120 nm, and the transmittance | permeability is with respect to the light of wavelength 500nm.

  As shown in FIG. 8, when the thickness of titanium is greater than 10 nm, it is not possible to obtain a transmissible transmittance for both processed and unprocessed pixel electrodes. When the film thickness is about 5 nm, the heat treatment at 300 ° C. increases the transmittance of the pixel electrode, so that almost the same transmittance as that of the ITO single layer film can be obtained. This indicates that titanium was oxidized and transformed into a more transparent titanium oxide. Therefore, in order to obtain a displayable pixel electrode, the film thickness of titanium is set to 10 nm or less. More preferably, it is about 5 nm.

  FIG. 1 is a top view of a pixel portion of an active matrix type liquid crystal display device according to the first and second embodiments. A gate signal line 12 and an image signal line 11 are arranged on a substrate in a lattice pattern, and the gate signal line 12 A pixel electrode 13 made of a transparent conductive film is disposed on a lattice formed by the signal lines 11. Note that the gate signal line 12, the image signal line 11, and the pixel electrode 13 are electrically insulated by an insulating film (not shown). Further, a TFT for performing voltage control to be applied to the pixel electrode 13 is formed. In the active layer 14 of the TFT, the channel intersects with the gate signal line 11 through an insulating film (not shown), the source is electrically connected to the image signal line 11, and the drain is electrically connected to the pixel electrode 13. .

  Hereinafter, a manufacturing process of the pixel portion illustrated in FIG. 1 will be described in detail based on the first and second embodiments.

  In this embodiment, the present invention is applied to a pixel TFT of an active matrix liquid crystal display device. FIGS. 2 and 3 are cross-sectional views for each manufacturing process of the pixel TFT of Embodiment 1. FIG. FIG. 3 is a cross-sectional view taken along a plane parallel to the channel length direction of the pixel TFT cut along a dotted line XX ′; FIG. It is sectional drawing. 2A to 2F and FIGS. 3A to 3F show the same state.

  As shown in FIGS. 2A and 3A, a silicon oxide film as a base film 102 is formed to a thickness of 100 nm to 500 nm on a glass substrate 101 (Corning 1737 or Corning 7059) by sputtering. Here, the film is formed to a thickness of 200 nm.

  Next, an amorphous silicon film is formed to a thickness of 10 nm to 150 nm by plasma CVD. Here, the film is formed to a thickness of 80 nm. Then, the amorphous silicon film is crystallized by a crystallization method such as heating or laser irradiation. Thereafter, the crystallized silicon film is patterned to form the active layer 103. Further, a silicon oxide film having a thickness of 50 nm to 150 nm is formed as the gate insulating film 104 by plasma CVD. In this embodiment, the thickness of the silicon oxide film is 100 nm.

  Next, an aluminum film is deposited to a thickness of 400 nm by sputtering and patterned to form the gate electrode 105. The gate electrode 105 corresponds to the gate signal line 12 in FIG. In addition, when about 0.2 wt% of scandium is previously contained in aluminum, generation of hillocks and whiskers can be suppressed in the subsequent heating step. (Fig. 2 (A), Fig. 3 (A))

  As shown in FIGS. 2B and 3B, the gate electrode 105 is covered with an anodic oxide 106 having a film thickness of 150 nm to 200 nm by the anodizing technique disclosed in Japanese Patent Laid-Open No. 5-267667. To do. In the present embodiment, a voltage is applied with the gate electrode 105 as an anode in an electrolytic solution obtained by neutralizing an ethylene glycol solution containing 3% tartaric acid to pH 6.9 with aqueous ammonia. Here, a dense and strong anodic oxide 106 is formed to a thickness of 150 nm around the gate electrode 105. The length of the offset is determined by the film thickness of the anodic oxide 106. The film thickness of the anodic oxide 106 can be controlled by the voltage applied to the gate electrode 105.

As shown in FIGS. 2C and 3C, an impurity is implanted into the active layer 103 by ion doping using the gate electrode 105 as a mask. In this embodiment, phosphorus is implanted to form a P-channel TFT. Phosphine (PH ₃ ) is used as the doping gas. As a result, the source region 107, the drain region 108, and the channel region 109 are formed in the active layer 103 in a self-aligned manner. After the doping step, thermal annealing, laser annealing, or the like is performed to activate the doped phosphorus ions.

  In this embodiment, since the anodic oxide 106 is formed around the gate electrode 105, an offset region is formed in the lower layer of the anodic oxide 106, and the source region 107 and the drain region 108 are gated by the thickness of the anodic oxide 106. It is displaced from the end face of the electrode 105. Since the offset region functions as a high resistance region, off-state current can be reduced.

  As shown in FIGS. 2D and 3D, a silicon oxide film having a thickness of 600 nm is formed as the first interlayer insulating film 110 by a plasma CVD method. As the first interlayer insulating film 110, a single layer film of silicon nitride or a multilayer film of a silicon oxide film and a silicon nitride film can be used instead of the single layer film of the silicon oxide film.

  As shown in FIGS. 2E and 3E, the first interlayer insulating film 110 and the gate insulating film 104 made of a silicon oxide film are etched by a known photoresist method to form a source region 107, a drain, A contact hole in the region 108 is formed. An aluminum film is formed only in the contact hole on the source region 107 side and patterned to form an upper layer wiring / electrode 111. The upper layer wiring / electrode 111 corresponds to the image signal line 11 in FIG.

  Next, a silicon nitride film functioning as a passivation film is formed as the second interlayer insulating film 112 to a thickness of 200 nm by plasma CVD. Then, the second interlayer insulating film 112 is etched to complete the contact hole 113 in the drain region 108.

  Note that a resin film such as a polyimide resin or an acrylic resin can be used as the second interlayer insulating film 112. In this case, the surface of the second interlayer insulating film 112 can be easily flattened by forming a resin film by a spin coating method. Also. Since the resin film is a low dielectric constant material, the capacitance formed between the wiring / electrode on the interlayer insulating film and the element can be reduced.

  As shown in FIGS. 2F and 3F, a pixel electrode 114 is formed in the contact hole 113 in the drain region 108. The pixel electrode 114 corresponds to the pixel electrode 13 in FIG. First, by sputtering or reactive sputtering, the titanium oxide film 114a is formed to a thickness of several nm to 10 nm, in this embodiment, to a thickness of 5 nm, and the ITO film 114b is formed to a thickness of 120 nm. The pixel electrode 114 is formed by patterning the titanium oxide film 114a and the ITO film 114b in the same shape. Note that the titanium oxide film 114a and the ITO film 114b are preferably formed continuously.

  Finally, heat treatment is performed at a temperature of 300 ° C. in a hydrogen atmosphere. In this embodiment, a titanium oxide film 114a having an oxidation potential lower than that of indium oxide, which is the main component of silicon and the ITO film 114b, is formed at the interface of the drain region 108. It is possible to prevent the silicon that is present from being oxidized. For this reason, since the hydrogenation treatment can be performed at a high temperature, the electrical characteristics, particularly the off-current characteristics, of the pixel TFT can be sufficiently improved.

  In this embodiment, the present invention is applied to a pixel TFT of an active matrix liquid crystal display device. FIGS. 4 and 5 are cross-sectional views for each manufacturing process of the pixel TFT of Embodiment 1, and FIG. FIG. 5 is a cross-sectional view taken along a plane parallel to the channel length direction of the pixel TFT cut along one dotted line XX ′, and FIG. 5 is a cross section taken along a plane perpendicular to the channel length direction of the pixel TFT cut along the dotted line YY ′. It is sectional drawing. 4A to 4G and 5A to 5G show the same state.

  As shown in FIGS. 4A and 5A, a silicon oxide film is formed as a base film 202 on a glass substrate 201 (Corning 1737 or Corning 7059) to a thickness of 100 to 500 nm by sputtering. Then, the film is formed to a thickness of 200 nm.

  Next, an amorphous silicon film is formed to a thickness of 10 nm to 150 nm, here 80 nm, by plasma CVD. The amorphous silicon film is crystallized and patterned by an appropriate crystallization method such as heating or laser irradiation to form the active layer 203. Further, a 100 nm-thick silicon oxide film 204 that functions as a gate insulating film is formed by plasma CVD.

  Next, an aluminum film constituting the gate electrode 205 is deposited to a thickness of 500 nm by sputtering. If 0.2% by weight of scandium is contained in the aluminum in advance, generation of hillocks and whiskers can be suppressed in the subsequent heating step and the like.

  Next, the surface of the aluminum film is anodized to form a dense anodic oxide 208 (not shown) that is extremely thin. Next, a resist mask 206 is formed on the surface of the aluminum film. At this time, since a dense anodic oxide 208 (not shown) is formed on the surface of the aluminum film, the resist mask 206 can be formed in close contact. The gate electrode 205 is formed by etching the aluminum film using the resist mask 206. The gate electrode 205 corresponds to the gate signal line 12 in FIG.

  As shown in FIGS. 4B and 5B, the gate electrode 205 is anodized while the resist mask 206 remains, and a porous anodic oxide 207 is formed to a thickness of 400 nm. At this time, since the resist mask 206 is in close contact with the surface of the gate electrode 205, the porous anodic oxide 207 is formed only on the side surface of the gate electrode 205.

  Next, as shown in FIGS. 4C and 5C, after peeling off the resist mask 206, the gate electrode 205 is anodized again in an electrolytic solution to form a dense anodic oxide 208 having a thickness of 100 nm. The thickness is formed.

  The formation of the anodic oxide may be performed by changing the electrolytic solution used. When forming the porous anodic oxide 207, an acidic solution containing 3 to 20% citric acid, oxalic acid, chromic acid or sulfuric acid is used. Use it. On the other hand, when the dense anodic oxide 208 is formed, an electrolytic solution in which PH is adjusted to about 7 with an ethylene glycol solution containing 3 to 10% of tartaric acid, boric acid, or nitric acid may be used.

  As shown in FIGS. 4D and 5D, the silicon oxide film 204 is etched using the gate electrode 205 and the porous anodic oxide 207 and dense anodic oxide 208 around the gate electrode 205 as a mask. Then, a gate insulating film 209 is formed.

As shown in FIGS. 4E and 5E, the porous anodic oxide 207 is removed. Impurities are implanted into the active layer 203 by ion doping using the gate electrode 205, the dense anodic oxide 208, and the gate insulating film 209 as a mask. In this embodiment, phosphorous ions are doped using phosphine (PH ₃ ) as a doping gas in order to form a P-channel TFT. During doping, conditions such as a dose amount and an acceleration voltage are controlled so that the gate insulating film 209 functions as a semi-transmissive mask.

  As a result of doping, a region not covered with the source region 210 is implanted with phosphorus ions at a high concentration to form the source region 210 and the drain region 211. Further, in the region covered only with the gate insulating film 209, phosphorus ions are implanted at a low concentration, so that low concentration impurity regions 212 and 213 are formed. Since the impurity is not implanted into the region immediately below the gate electrode 205, the channel region 214 is formed. After the doping process, thermal annealing, laser annealing, or the like is performed to activate the doped phosphorus ions.

  Since the low-concentration impurity regions 212 and 213 function as high-resistance regions, they contribute to reduction of off-state current. In particular, the low concentration impurity region 213 on the drain region 211 side is called LDD. Further, by making the dense anodic oxide 208 sufficiently thick, a region immediately below the dense anodic oxide 208 can be set as an offset region, and off current can be further reduced.

  As shown in FIGS. 4F and 5F, a silicon oxide film having a thickness of 500 nm is formed as the first interlayer insulating film 215 by plasma CVD. Note that as the first interlayer insulating film 215, a single layer film of a silicon nitride film or a stacked film of a silicon oxide film and a silicon nitride film may be formed instead of a single layer film of a silicon oxide film.

  Next, the first interlayer insulating film 215 made of a silicon oxide film is etched by a known etching method to form contact holes in the source region 210 and the drain region 211, respectively.

  Then, an aluminum film having a thickness of 400 nm is formed only in the contact hole on the source region 210 side by a sputtering method, and this is etched to form an upper layer wiring / electrode 216. The upper layer wiring / electrode 216 corresponds to the image signal line 11 in FIG.

Further, a silicon nitride film is formed to a thickness of 200 nm as the second interlayer insulating film 217 by plasma CVD. Then, the second interlayer insulating film 217 is etched to complete the contact hole 218 in the drain region 211.
Note that a resin film may be formed as the second interlayer insulating film 217 instead of the silicon nitride film.

  As shown in FIGS. 4G and 5G, a pixel electrode 219 is formed in the contact hole 218 in the drain region 211. The pixel electrode 219 corresponds to the pixel electrode 13 in FIG.

  In order to form the pixel electrode 219, first, a titanium film 219a is formed to a thickness of several nm to 10 nm, in this embodiment, 5 nm by sputtering. Next, an ITO film 219b is formed to a thickness of 120 nm by sputtering. Each of the titanium film 219a and the ITO film 219b is patterned into the shape of the pixel electrode 13 shown in FIG. Note that the titanium film 219a and the ITO film 219b are preferably formed continuously.

  Finally, heat treatment is performed at a temperature of 300 ° C. in a hydrogen atmosphere. At this time, the defect of the active layer 203 is repaired, and at the same time, the titanium film 219a is oxidized to become a light-transmitting titanium oxide film 219c, and the pixel electrode 219 is completed.

  In this embodiment, a titanium film 219a having an oxidation potential lower than that of silicon and higher than that of indium oxide, which is the main component of the ITO film 219b, is formed at the interface of the drain region 211. Only the titanium film 219a is oxidized without oxidizing the silicon of the ITO film 114b. Therefore, an increase in contact resistance between the titanium oxide film 219c and silicon due to heat treatment can be prevented. Accordingly, since the hydrogenation treatment can be performed at a high temperature, the electrical characteristics of the pixel TFT, particularly the off current characteristics can be improved.

  Further, since the titanium film 219a is formed to a thickness of several nanometers, as shown in FIG. 8, the titanium film 219a is oxidized to form a titanium oxide film 219c, whereby the transmittance of the pixel electrode 219 is reduced to ITO. The transmittance can be the same as that of the single layer film.

  In the first and second embodiments described above, the structure of the thin film transistor is the top gate type, but this embodiment shows a manufacturing process of a thin film transistor called a bottom gate type in which the gate electrode is closer to the substrate side than the active layer.

  FIG. 9 shows a manufacturing process of this example. First, as shown in FIG. 9A, a silicon oxide film 302 is formed as a base film over a glass substrate 301 by a sputtering method. Next, an aluminum film is formed and patterned to form the gate electrode 303.

  At this time, 0.18% by weight of scandium is contained in the aluminum film. In addition, other impurities are tried to reduce the concentration as much as possible. These ideas are for suppressing the formation of protrusions called hillocks and whiskers due to abnormal growth of aluminum in the subsequent process.

  Next, a silicon oxide film is formed as a gate insulating film 304 to a thickness of 50 nm by plasma CVD.

  Further, an amorphous silicon film (which will later become a crystalline silicon film 305) serving as a starting film constituting the active layer of the thin film transistor is formed by plasma CVD. In addition to the plasma CVD method, a low pressure thermal CVD method may be used.

  Next, laser light irradiation is performed to crystallize an amorphous silicon film (not shown). Thus, a crystalline silicon film 305 is obtained. In this way, the state shown in FIG.

  After obtaining the state shown in FIG. 9A, patterning is performed to form the active layer 306 shown in FIG. 9B.

  Next, a silicon nitride film (not shown) is formed, and a mask pattern 307 made of a silicon nitride film is formed by performing exposure from the back side of the substrate 301 using the gate electrode 303.

The mask pattern 307 is formed as follows.
First, a resist mask pattern is formed by exposure from the back side of the substrate 301 using the pattern of the gate electrode 303. Further, ashing is performed to recede the resist mask pattern. The silicon nitride film is patterned using the receded resist mask pattern (not shown) to obtain a pattern 307. In this way, the state shown in FIG.

  Next, doping of impurities using the mask pattern 307 is performed. Here, P (phosphorus) is used as a dopant, and a plasma doping method is used as a means for doping.

  In this step, P is doped in the regions 308 and 309. The region 310 is not doped with P.

  After completion of the doping, laser beam irradiation is performed from the upper surface to activate the doped region and anneal damage caused by the impact of the dopant ions.

  Thus, a region 308 is formed as a source region as shown in FIG. Further, 309 is formed as a drain region. 310 is defined as the channel region.

  Next, as a first interlayer insulating film 311 made of a silicon nitride film, a silicon nitride film is formed to a thickness of 300 nm by plasma CVD.

  As the first interlayer insulating film used here, in addition to the silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a laminated film of a silicon oxide film and a silicon nitride film (whichever comes first) is used. Can be used.

  Next, contact holes 312 for the source region 308 and the drain region 309 are formed in the first interlayer insulating film 311, and an upper layer wiring / electrode 313 that contacts the source region 308 is formed. In this way, the state shown in FIG. 9C is obtained.

  Next, as shown in FIG. 9D, a second interlayer insulating film 314 having a flat surface is formed using a transparent polyimide resin or acrylic resin. For example, a spin coating method may be employed as the film forming method.

  Next, an opening connected to the contact hole 312 is formed in the second interlayer insulating film 314 by etching, and the contact hole reaching the drain region 309 is completed. Next, as illustrated in FIG. 9D, the pixel electrode 315 is formed in the contact hole of the drain region 310.

  In order to form the pixel electrode 315, first, a titanium film 315a is formed to a thickness of several nm to 10 nm, in this embodiment, 5 nm by sputtering. Next, an ITO film 315b is formed to a thickness of 120 nm by sputtering. Each of the titanium film 315a and the ITO film 315b is patterned into the shape of the pixel electrode 13 shown in FIG. Note that the titanium film 315a and the ITO film 315b are preferably formed continuously.

Finally, heat treatment is performed at a temperature of 300 ° C. in a hydrogen atmosphere. At this time, the defect of the active layer 203 is repaired, and at the same time, the titanium film 315a is oxidized to become a light-transmitting titanium oxide film 315c, and the pixel electrode 315 is completed.
Through the above steps, the thin film transistor illustrated in FIG. 9D is completed.

  In this embodiment, the titanium oxide film 315c of the pixel electrode 315 is formed by oxidizing the titanium film 315a. However, a titanium oxide film may be directly formed as in the first embodiment.

FIG. 3 is a top view of a pixel portion of an active matrix type liquid crystal display device in Examples 1 and 2. FIG. 2 is a cross-sectional view for each manufacturing process of the pixel TFT of Example 1, and is a cross-sectional view taken along the dotted line X-X ′ in FIG. FIG. 3 is a cross-sectional view for each manufacturing process of the pixel TFT of Example 1, and is a cross-sectional view taken along the dotted line Y-Y ′ in FIG. 1. FIG. 6 is a cross-sectional view for each manufacturing process of the pixel TFT of Example 2, and is a cross-sectional view taken along a dotted line X-X ′ in FIG. 1. FIG. 4 is a cross-sectional view for each manufacturing process of a pixel TFT of Example 2, and is a cross-sectional view taken along a dotted line Y-Y ′ in FIG. 1. It is a phase diagram of the oxidation potential of the metal used for the electrode of TFT. It is a graph of the contact resistance between the pixel electrode and silicon with respect to the heating temperature. It is a graph of the transmittance | permeability of the two-layer pixel electrode of titanium / ITO with respect to the film thickness of titanium. 6 is a cross-sectional view for each manufacturing process of a pixel TFT of Example 3. FIG.

Explanation of symbols

11 Image signal line 12 Gate signal line 13 Pixel electrode 14 Active layer 103 Active layer 107 Source region 108 Drain region 111 Upper layer wiring / electrode 114 Pixel electrode 114a Titanium oxide film 114b ITO film 210 Source region 211 Drain region 216 Upper layer wiring / electrode 219 Pixel electrode 219a Titanium film 219b ITO film 219c Titanium oxide film 210 Source region 309 Drain region 313 Upper wiring / electrode 315 Pixel electrode 315a Titanium film 315b ITO film 315c Titanium oxide film

Claims (6)

Forming a thin film transistor using silicon as a semiconductor layer;
Forming a first transparent conductive film having an oxidation potential lower than that of silicon so as to be in contact with the semiconductor layer;
Forming a second transparent conductive film having an oxidation potential higher than that of the silicon so as to be in contact with the first transparent conductive film;
In an atmosphere containing hydrogen, the thin film transistor, have the line heat treatment of the first transparent conductive film, and said second transparent conductive film,
A method for manufacturing a display device, wherein the first transparent conductive film and the second transparent conductive film are used as pixel electrodes . Forming a thin film transistor using silicon as a semiconductor layer;
Forming a first transparent conductive film using titanium oxide so as to be in contact with the semiconductor layer;
Forming a second transparent conductive film using either indium oxide, tin oxide or zinc oxide as a main component so as to be in contact with the first transparent conductive film;
In an atmosphere containing hydrogen, the thin film transistor, have the line heat treatment of the first transparent conductive film, and said second transparent conductive film,
A method for manufacturing a display device, wherein the first transparent conductive film and the second transparent conductive film are used as pixel electrodes . In claim 1 or claim 2 ,
A method for manufacturing a display device, wherein the first transparent conductive film is formed to a thickness of 10 nm or less. Forming a thin film transistor using silicon as a semiconductor layer;
Forming a metal film having an oxidation potential lower than that of silicon so as to be in contact with the semiconductor layer;
Forming a transparent conductive film having an oxidation potential higher than that of silicon so as to be in contact with the metal film;
In an atmosphere containing hydrogen, the thin film transistor, the metal film, and the transparent conductive film are heat-treated, and the heat treatment makes the metal film transparent ,
A method for manufacturing a display device, wherein the metal film and the transparent conductive film are used as pixel electrodes . Forming a thin film transistor using silicon as a semiconductor layer;
Forming a metal film using titanium so as to contact the semiconductor layer,
Forming a transparent conductive film using either indium oxide, tin oxide, or zinc oxide as a main component so as to be in contact with the metal film;
In an atmosphere containing hydrogen, the thin film transistor, the metal film, and the transparent conductive film are heat-treated, and the heat treatment makes the metal film transparent ,
A method for manufacturing a display device, wherein the metal film and the transparent conductive film are used as pixel electrodes . In claim 4 or claim 5 ,
A method for manufacturing a display device, wherein the metal film is formed with a thickness of 10 nm or less.

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