JP4128428B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
JP4128428B2
JP4128428B2 JP2002326047A JP2002326047A JP4128428B2 JP 4128428 B2 JP4128428 B2 JP 4128428B2 JP 2002326047 A JP2002326047 A JP 2002326047A JP 2002326047 A JP2002326047 A JP 2002326047A JP 4128428 B2 JP4128428 B2 JP 4128428B2
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Japan
Prior art keywords
insulating film
formed
film
semiconductor layer
gate insulating
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JP2004165221A (en
JP2004165221A5 (en
Inventor
哲司 山口
健吾 秋元
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株式会社半導体エネルギー研究所
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Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an insulated gate field effect transistor typified by a thin film transistor (TFT) and a manufacturing method thereof.
[0002]
[Prior art]
In recent years, display devices such as liquid crystal display devices and light-emitting devices have been actively developed due to an increase in demand for portable devices. The technology for forming pixels and driving circuits using transistors formed of polycrystalline semiconductor (polysilicon) on an insulator greatly contributes to miniaturization and low power consumption, and is being actively developed. Yes.
[0003]
As an example, a top-gate transistor can be used to increase the efficiency of activation of the source region and the drain region without increasing the size of the thin film transistor and without worrying about damage to the glass substrate having a strain point of 700 degrees or less. There is one in which a metal film is disposed under the polycrystalline silicon constituting (see, for example, Patent Document 1). In addition, by adopting RTA (rapid thermal anneal) in the annealing process, an RTA polycrystalline silicon film is placed under the polycrystalline silicon that constitutes the top gate type transistor in order to improve productivity and display quality. (For example, refer to Patent Document 2).
[0004]
[Patent Document 1]
JP 2001-102585 A
[Patent Document 2]
JP-A-5-53143
[0005]
[Problems to be solved by the invention]
As a method of heat treatment for a gate insulating film or a semiconductor constituting a thin film transistor, there is instantaneous thermal annealing (RTA) in which annealing is performed at a high temperature in a short time. However, when performing RTA, the substrate temperature needs to be 700 ° C. Therefore, when the entire substrate is heated, a thermally fragile substrate such as a glass substrate is damaged such as warpage. Therefore, an object of the present invention is to provide a thin film transistor that does not affect a thermally fragile substrate and a manufacturing method thereof even when RTA is used in a heat treatment step.
[0006]
[Means for Solving the Problems]
In order to solve the above-described problems of the prior art, the following measures are taken in the present invention.
[0007]
In the present invention, instantaneous thermal annealing (RTA, local heating) is performed using a lamp (typically a halogen lamp) that performs heat treatment only at a desired location. Furthermore, in the present invention, instantaneous thermal annealing is performed after a metal layer or an amorphous semiconductor that absorbs heat is provided on a substrate. Then, the semiconductor and the gate insulating film of the thin film transistor are heated to about 700 degrees, but the temperature of the substrate becomes about 400 degrees, and damage to the substrate can be prevented. In the present invention, two processes of a heat treatment for the gate insulating film and an activation process for the impurity element added to the semiconductor or a gettering step for the metal element added to the semiconductor are simultaneously performed using RTA. Furthermore, since RTA can be performed in a short time, the present invention is expected to improve productivity.
[0008]
In the present invention, a gate insulating film is formed using a sputtering apparatus which uses an inert gas and has a simple configuration. Furthermore, the present invention provides a dielectric constant of a thin film used for each layer in order to form a gate insulating film thick enough to obtain a desired withstand voltage and to make it difficult to reduce the capacitance between the semiconductor constituting the TFT and the gate electrode. Is set so that a desired capacitance can be obtained as a TFT. Specifically, the gate insulating film has a two-layer structure, and the two-layer gate insulating film is continuously formed by a sputtering method. The first layer of the gate electrode / gate insulating film is a silicon nitride film (dielectric constant: about 7.5) / the second layer of the gate insulating film is a silicon oxide film (dielectric constant: about 3.5) / active layer Laminate sequentially. Then, by performing the instantaneous thermal annealing on the gate insulating film, its CV characteristics (capacitance voltage dependency) are improved, the hysteresis is improved, and the reliability is improved.
[0009]
In the present invention, a metal layer is formed on an insulating surface, and a gate electrode is formed so as to overlap the metal layer. A silicon nitride film and a silicon oxide film are continuously formed on the gate electrode by a sputtering method, a semiconductor is formed on the silicon oxide film so as to overlap the gate electrode, and an impurity element is formed on the semiconductor using a mask. Added. Thereafter, instantaneous thermal annealing is performed on the silicon nitride film, the silicon oxide film, and the semiconductor to which the impurity element is added.
[0010]
In the present invention, a gate electrode is formed on an insulating surface, and a silicon nitride film and a silicon oxide film are continuously formed on the gate electrode by a sputtering method. A first amorphous semiconductor is formed on the silicon oxide film so as to overlap with the gate electrode, a metal element is added to the first amorphous semiconductor and heated to form a crystalline semiconductor, and the crystal A second amorphous semiconductor is formed on the quality semiconductor. Thereafter, instantaneous thermal annealing is performed on the silicon nitride film, the silicon oxide film, the crystalline semiconductor, and the second amorphous semiconductor to convert the metal element contained in the crystalline semiconductor into the second amorphous semiconductor. It is characterized by performing gettering that causes segregation.
[0011]
In the present invention, a gate electrode is formed on an insulating surface, and a silicon nitride film and a silicon oxide film are continuously formed on the gate electrode by a sputtering method. An amorphous semiconductor is formed on the silicon oxide film so as to overlap the gate electrode, and instantaneous thermal annealing is performed on the silicon nitride film, the silicon oxide film, and the amorphous semiconductor.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
An embodiment of the present invention will be described with reference to FIGS. Here, by using the method for manufacturing a thin film transistor of the present invention, a driver circuit formed of a CMOS circuit and a pixel portion having an N-channel TFT (for switching) and a P-channel TFT (for driving) are formed over the same substrate. A manufacturing process to be formed will be described.
[0013]
As the substrate 200, a glass substrate or the like is used (FIG. 2A). Note that since the present invention is a manufacturing method which does not adversely affect a thermally fragile substrate, it is preferable to use such a substrate. In this embodiment, the glass substrate 200 is used.
[0014]
On the substrate 200, a metal having an excellent heat resistance capable of withstanding the RTA processing temperature such as W—Si, Ag, and TaN is subjected to predetermined patterning and etching so as to have a desired shape, and the metal layer 202. -205 is formed to a thickness of 50-500 nm. In this embodiment, as the metal layers 202 to 205, W—Si is formed to a thickness of 200 nm by a sputtering method using a W target. A top view at this time is shown in FIG. The metal layers 202 to 205 have a shape that covers a semiconductor layer to be formed later. By providing the metal layers 202 to 205, light incident on a semiconductor layer to be formed later is blocked, so that an effect of suppressing generation of leakage current can be obtained. Further, the occurrence of crosstalk can be suppressed by suppressing the generation of leakage current.
[0015]
Then, a base film 206 made of an insulating film is formed so as to cover the metal layers 202 to 205. In the case of forming the base film 206 with a two-layer structure, the first layer of the base film 206 is formed to a thickness of 10 to 200 nm using a known method (sputtering method, plasma CVD method, etc.). The eyes are formed to a thickness of 50 to 200 nm. In this embodiment, a sputtering method is used to form a silicon nitride oxide film with a thickness of 50 nm as the first layer of the base film 206, a silicon oxynitride film with a thickness of 50 nm as the second layer, The surface was flattened by a known method such as a CMP method. Note that the base film 206 is not limited to a two-layer structure, and may be a single layer or a structure in which three or more layers are stacked. However, the base film 206 is preferably set to have a large film thickness with a material having a low dielectric constant in order to reduce parasitic capacitance.
[0016]
Then, on the base film 206, a metal having excellent heat resistance that can withstand the RTA processing temperature such as W-Si, Ag, and TaN is subjected to predetermined patterning and etching so as to have a desired shape. Gate electrodes 207 to 210 are formed to a thickness of 50 to 500 nm (FIG. 2B). In this embodiment, as the gate electrodes 207 to 210, W—Si is formed to a thickness of 200 nm by a sputtering method using a W target. A top view at this time is shown in FIG.
[0017]
Subsequently, a gate insulating film 211 is formed over the gate electrodes 207 to 210. The gate insulating film 211 is formed of an insulating film containing silicon with a thickness of 30 to 200 nm by a sputtering method. In this embodiment, the gate insulating film 211 has a two-layer structure, the silicon nitride film 211a is formed as a first layer with a thickness of 30 nm, and the silicon oxide film 211b is formed as a second layer with a thickness of 20 nm.
In the present invention, the gate insulating film 211 is thus produced by the sputtering method. Since the sputtering apparatus uses an inert gas such as Ar and has a simple configuration, it requires less labor to maintain the apparatus as compared with the case where a plasma CVD method (CVD apparatus) is used.
In order to improve the withstand voltage, it is generally preferable to form a thick gate insulating film. On the other hand, the capacitance between the semiconductor and the gate electrode depends on the dielectric constant of the thin film employed for the gate insulating film and its film thickness. That is, the thickness of the gate insulating film is set based on the balance between the withstand voltage and the capacity. Therefore, the present invention forms the gate insulating film thick enough to obtain a desired withstand voltage. Furthermore, in the present invention, in order to make it difficult to reduce the capacitance between the semiconductor constituting the TFT and the gate electrode, a silicon oxide film (SiO 2 , About 3.5), a silicon nitride film (SiN, about 7.5) is laminated and formed so as to be a lower layer of the silicon oxide film. Then, the withstand voltage can be improved and the capacity can be sufficient.
That is, the dielectric constant of the silicon oxide film is about 3.8, whereas the dielectric constant of the silicon nitride film is about 7.5. Therefore, by including the silicon nitride film in the gate insulating film formed of the silicon oxide film, Substantially the same effect as achieving a thinner gate insulating film can be obtained. In addition, gate leakage can be reduced, and an advantageous effect can be obtained for miniaturization of elements based on the scaling law. In addition, by using a dense silicon nitride film as a component of the gate insulating film, it can function as a protective film for impurities entering from the outside, forming a clean interface between the gate insulating film and the semiconductor. can do. That is, the ability to form a dense gate insulating film that does not contain hydrogen and does not contain fixed charges by heat treatment contributes to stabilization of transistor characteristics. In addition, since the silicon nitride film and the silicon oxide film can be continuously formed by a sputtering method, physical contamination such as fine particles and chemical contamination from the surrounding environment can be prevented.
[0018]
Note that the gate insulating film 22 is not limited to a two-layer structure, and may have a structure of three or more layers, or may be configured using a material other than a silicon oxide film or a silicon nitride film, but is used for each layer. In consideration of the dielectric constant of the thin film, the TFT is set so as to obtain a desired capacitance.
[0019]
Next, semiconductor layers 214 to 217 are formed over the gate insulating film 211 (FIG. 2C). For the semiconductor layers 214 to 217, first, a semiconductor film is formed to a thickness of 25 to 80 nm (preferably 30 to 60 nm) by a known method (sputtering method, LPCVD method, plasma CVD method, or the like). Next, the semiconductor film is crystallized by using a known crystallization method (a laser crystallization method, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like). Then, the obtained crystalline semiconductor film is patterned into a desired shape to form semiconductor layers 214 to 217. Note that as the semiconductor film, a compound semiconductor film having an amorphous structure such as an amorphous semiconductor film, a microcrystalline semiconductor film, a crystalline semiconductor film, or an amorphous silicon germanium film may be used.
[0020]
In this embodiment mode, an amorphous silicon film with a thickness of 50 nm is formed by plasma CVD. Thereafter, a solution containing nickel is held on the amorphous silicon film, and after dehydrogenation (500 ° C., 1 hour) is performed on the amorphous silicon film, thermal crystallization (550 ° C., 4 hours) is performed. A crystalline silicon film was formed. After that, semiconductor layers 214 to 217 were formed by a patterning process using a photolithography method. A top view at this time is shown in FIG.
[0021]
Note that when a crystalline semiconductor film is formed by a laser crystallization method, a continuous-wave or pulsed gas laser or solid-state laser may be used. Examples of the former gas laser include an excimer laser, a YAG laser, and the like. Examples of the latter solid-state laser include YAG, YVO doped with Cr, Nd, and the like. Four A laser using a crystal such as In order to obtain a crystal with a large grain size in crystallization of the amorphous semiconductor film, it is preferable to use a solid-state laser capable of continuous oscillation and apply the second to fourth harmonics of the fundamental wave. In the case of using the above laser, the semiconductor film may be irradiated with a laser beam emitted from a laser oscillator in a linear shape by an optical system. The conditions for crystallization are appropriately set. When an excimer laser is used, the pulse oscillation frequency is 300 Hz, and the laser energy density is 100 to 700 mJ / cm. 2 (Preferably 200 to 300 mJ / cm 2 ) When a YAG laser is used, the second harmonic is used to set the pulse oscillation frequency to 1 to 300 Hz and the laser energy density to 300 to 1000 mJ / cm. 2 (Preferably 350 to 500 mJ / cm 2 ) Then, a laser beam condensed in a linear shape with a width of 100 to 1000 μm (preferably a width of 400 μm) is irradiated over the entire surface of the substrate, and the superposition ratio (overlap ratio) of the linear beam at this time is 50 to 98%. You can go.
[0022]
However, in this embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an amorphous silicon film having a thickness of 50 to 100 nm is formed on the crystalline silicon film, and heat treatment (RTA method, thermal annealing using a furnace annealing furnace, etc.) is performed, and the amorphous silicon film Metal elements are diffused, and the amorphous silicon film is removed by etching after the heat treatment. As a result, the content of the metal element in the crystalline silicon film can be reduced or removed. In addition, after forming the semiconductor layers 214 to 217, a small amount of impurity element (boron or phosphorus) may be doped (channel doping) in order to control the threshold value of the TFT.
[0023]
Next, a resist mask 218 is formed by photolithography, and first doping treatment is performed, and an impurity element imparting N-type conductivity is added to the semiconductor layers 214 to 217 at a low concentration (FIG. 3A). ). The first doping process may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is a dose of 1 × 10 13 ~ 5x10 14 /cm 2 The acceleration voltage is 40 to 80 keV. As an impurity element imparting N-type conductivity, an element belonging to Group 15 may be used, and typically phosphorus (P) or arsenic (As) is used. In this embodiment, the dose amount is 5.0 × 10 5 by ion doping. 13 /cm 2 The impurity regions 219 to 222 were formed in a self-aligning manner using an acceleration voltage of 50 keV and P (phosphorus) as an impurity element imparting N-type conductivity. At this time, the first impurity regions 219 to 222 have 1 × 10 18 ~ 1x10 20 /cm Three An impurity element imparting N-type was added in a concentration range of.
[0024]
Subsequently, after removing the resist mask 218, a resist mask 223 is newly formed, and a second doping process is performed at an acceleration voltage higher than that of the first doping process (FIG. 3B). The condition of the ion doping method is a dose of 1 × 10 13 ~ 3x10 15 /cm 2 The acceleration voltage is set to 60 to 120 keV. In this embodiment, the dose amount is 3.0 × 10 15 /cm 2 As a result of performing the doping process under the condition of the acceleration voltage of 65 keV, the impurity regions 224 and 225 have 1 × 10 19 ~ 5x10 twenty one /cm Three An impurity element imparting N-type was added in a concentration range of. In addition, regions where no impurity element is added or regions where a small amount of impurity element is added (collectively referred to as channel formation regions in the present invention) 226 and 227 are formed.
[0025]
Next, after the resist mask 223 is removed, a resist mask 228 is newly formed (FIG. 3C). Thereafter, a third doping process is performed to form an impurity region in which an impurity element imparting a conductivity type opposite to the first conductivity type is added to the semiconductor layer which is an active layer of the P-channel TFT. In this embodiment mode, a resist mask 228 is used as a mask for the impurity element, an impurity element imparting p-type conductivity is added, and impurity regions 229 and 230 are formed in a self-aligning manner. The dose is 1 × 10 16 /cm 2 Under the condition that the acceleration voltage is 80 keV, diborane (B 2 H 6 ) Using an ion doping method. By this doping treatment, the concentration of the impurity element imparting P-type is 1 × 10 19 ~ 5x10 twenty one atoms / cm Three It was doped so as to be. In addition, channel formation regions 246 and 247 were formed.
[0026]
Note that a desired impurity region may be formed by two or more times of doping treatment by appropriately changing the conditions for performing the doping treatment.
[0027]
Next, as shown in FIG. 3D, the resist mask 228 is removed, and the heat treatment for the gate insulating film 211 and the activation treatment of the impurity element added to the semiconductor layer are performed at the same time. This treatment is preferably performed using the RTA method at a temperature of 600 to 800 degrees C. for a short time of about 1 to 240 seconds. At this time, the semiconductor layer and the gate insulating film are heated to about 700 ° C. due to the difference in heat absorption rate of each material, but the temperature of the substrate 200 becomes about 400 ° C., so that damage to the substrate 200 is suppressed. can do. In addition, by performing rapid heating for about 1 to 240 seconds, even in the above temperature range, the same effect can be obtained even for a thermally fragile glass substrate having a strain point of 700 degrees or less and distortion due to heat can be obtained. It becomes possible to suppress. In addition, since it is sufficient to perform RTA only on the portion where the TFT is formed, a region to be heated at a time can be reduced, and damage to the substrate can be suppressed.
Further, by heat treatment on the gate insulating film, minute silicon clusters taken into the film can be oxidized or nitrided, and internal strain can be relaxed to reduce the defect density in the film and the interface defect density.
Furthermore, since the metal layers 201 to 205 have a function of accumulating heat, heat is efficiently supplied to the semiconductor layers also from the metal layers 201 to 205, so that the activation efficiency can be increased. Furthermore, this process improves the CV characteristics (capacitance voltage dependency) of the TFT in which the gate insulating film is formed by the sputtering method, improves the hysteresis, and improves the reliability. For improvement of the CV characteristics, Japanese Patent Application No. 2002-226056 filed by the present applicant may be referred to.
Note that the RTA process may be performed after the gate insulating film 211 is formed (FIG. 2B), and only the heat treatment of the gate insulating film 211 may be performed. Alternatively, after the gate insulating film 211 and the semiconductors 214 to 217 are formed (FIG. 2C), the gate insulating film 211 and the semiconductors 214 to 217 may be subjected to heat treatment at the same time.
Alternatively, the step may be performed after a first interlayer insulating film made of an inorganic material is formed over the semiconductors 214 to 217. Then, hydrogen in the interlayer insulating film made of an inorganic material can be used to hydrogenate the semiconductor layer at the same time.
[0028]
Then, a first interlayer insulating film 231 made of an insulating film is formed (FIG. 3E). The first interlayer insulating film 231 is formed of an insulating film containing silicon with a thickness of 100 to 200 nm using a plasma CVD method or a sputtering method. In this embodiment mode, a silicon oxynitride film 231 having a thickness of 100 nm is formed by a plasma CVD method.
[0029]
A second interlayer insulating film 232 is formed on the first interlayer insulating film 231. As the second interlayer insulating film 232, a silicon oxide film formed by a CVD method, a silicon oxide film applied by an SOG (Spin On Glass) method or a spin coating method, an organic insulating film such as acrylic, or a non-photosensitive film The organic insulating film is formed with a thickness of 0.7 to 5 μm (preferably 2 to 4 μm). In this embodiment, the acrylic film 50 having a film thickness of 1.6 μm is formed by the CVD method. Note that the second interlayer insulating film 232 is preferably a film having excellent flatness because it has a strong meaning of alleviating unevenness due to the TFT formed over the substrate 200 and flattening.
[0030]
Next, a third interlayer insulating film 233 is formed on the second interlayer insulating film 232. As the third interlayer insulating film 233, a silicon nitride film or a silicon nitride oxide film is formed with a thickness of 0.1 to 0.2 μm by a sputtering method. In this embodiment, the silicon nitride film 233 is formed with a thickness of 0.1 μm by a sputtering method.
[0031]
By providing the first to third interlayer insulating films 231 to 233, it is possible to obtain a blocking action that prevents intrusion of various ionic impurities including oxygen and moisture in the air.
[0032]
Then, contact holes are formed by dry etching or wet etching (FIG. 1A). In this embodiment mode, the first to third interlayer insulating films 231 to 233 are etched to form contact holes reaching the impurity regions 224, 225, 229, and 230.
[0033]
Next, wirings 234 to 240 electrically connected to the impurity regions are formed. In this embodiment, the wirings 234 to 240 are formed by continuously forming a Ti film with a thickness of 100 nm, an Al film with a thickness of 350 nm, and a Ti film with a thickness of 100 nm by sputtering, and patterning and etching into a desired shape. Formed. Note that the structure is not limited to a three-layer structure, and may be a structure having two or less layers or a stacked structure having four or more layers. The wiring material is not limited to Al and Ti, and other conductive films may be used.
[0034]
Through the above steps, a driving circuit portion having a CMOS circuit including an N-channel TFT 242 and a P-channel TFT 243, an N-channel TFT (switching TFT) 244, and a P-channel TFT (driving TFT) 245 are provided. The pixel portion can be formed over the same substrate.
[0035]
The N-channel TFT 242 in the driver circuit portion includes a channel formation region 226 that overlaps with the gate electrode 207 and an impurity region 224 that functions as a source region or a drain region. A P-channel TFT 243 that is connected to the N-channel TFT 242 with a wiring 235 to form a CMOS circuit has a channel formation region 246 that overlaps with the gate electrode 208 and an impurity region 229 that functions as a source region or a drain region.
[0036]
The N-channel TFT 244 in the pixel portion includes a channel formation region 227 that overlaps with the gate electrode 209 and an impurity region 225 that functions as a source region or a drain region. The P-channel TFT 245 includes a channel formation region 247 that overlaps with the gate electrode 210 and an impurity region 230 that functions as a source region or a drain region.
[0037]
In the present invention, a metal layer is provided below the semiconductor layer of each of the TFTs 242-245. Therefore, the threshold voltage is stabilized, and variations in threshold voltage among a plurality of transistors on the substrate can be reduced.
[0038]
In this embodiment mode, the heat treatment of the gate insulating film and the activation treatment of the impurity element added to the semiconductor are performed simultaneously using rapid thermal annealing (RTA). When RTA is performed, heat is absorbed by the metal layer, and since instantaneous thermal annealing is performed only on a desired portion, heat treatment can be performed without adversely affecting the substrate. Productivity can be improved by this invention which has the said structure.
[0039]
(Embodiment 2)
An embodiment of the present invention will be described with reference to FIGS. Here, a manufacturing process in which a driver circuit including a CMOS circuit and a pixel portion including a switching TFT and a driving TFT are formed over the same substrate will be described.
[0040]
A glass substrate or the like is used for the substrate 300 (FIG. 4A). Note that since the present invention is a manufacturing method which does not adversely affect a thermally fragile substrate, it is preferable to use such a substrate. In this embodiment, a glass substrate 300 is used.
[0041]
On the substrate 300, a metal having excellent heat resistance that can withstand the RTA processing temperature such as W-Si, Ag, and TaN is subjected to predetermined patterning and etching so as to have a desired shape, and the gate electrode 302 is formed. ˜305 is formed to a thickness of 50˜500 nm. In this embodiment, as the gate electrodes 302 to 305, W—Si is formed to a thickness of 200 nm by a sputtering method using a W target. A top view at this time is shown in FIG.
[0042]
Next, a gate insulating film 306 that covers the gate electrodes 302 to 305 is formed. The gate insulating film 306 is formed with an insulating film containing silicon with a thickness of 30 to 200 nm by a sputtering method. In this embodiment mode, a silicon nitride film 306a is formed with a thickness of 30 nm as the first layer of the gate insulating film 306, and a silicon oxide film 306b is formed with a thickness of 20 nm as the second layer. As described above, the effect produced by stacking the silicon nitride film 306a and the silicon oxide film 306b as the gate insulating film 306 is as described in Embodiment Mode 1, and thus is omitted here.
[0043]
Note that the gate insulating film 306 is not limited to a two-layer structure, and may have a structure of three or more layers. Alternatively, the gate insulating film 306 may be formed using a material other than a silicon oxide film and a silicon nitride film. In consideration of the dielectric constant of the thin film, the TFT is set so as to obtain a desired capacitance.
[0044]
Subsequently, an amorphous silicon film 307 is formed over the gate insulating film 306 (FIG. 4B). In this embodiment, an amorphous silicon film having a thickness of 55 nm is formed by plasma CVD. Thereafter, the solution 308 containing nickel is held on the amorphous silicon film, dehydrogenation (500 ° C., 1 hour) is performed on the amorphous silicon film, and then thermal crystallization (550 ° C., 4 hours). To form a crystalline silicon film.
[0045]
In this embodiment, since the amorphous silicon film is crystallized using a metal element that promotes crystallization, the metal element remains in the crystalline silicon film. Therefore, an insulating film is formed with a thickness of 5 to 500 nm on the crystalline silicon film, and then an amorphous silicon film is laminated and formed with a thickness of 5 to 500 nm on the insulating film. After that, patterning is performed so as to obtain a desired shape, and crystalline silicon 311 to 314, insulating layers 309a to 309d, and amorphous silicon 310a to 310d are stacked (FIG. 4C). In this embodiment, silicon oxides 309a to 309d having a thickness of 50 nm are formed over the crystalline silicon 311 to 314 as insulating layers, and then amorphous silicon containing argon (used as gettering sites) 310a to 310d is formed. It was formed with a thickness of 150 nm. After that, instantaneous thermal annealing (RTA) is performed only on a desired portion on the substrate 300, and gettering treatment for diffusing (segregating) metal elements in the amorphous silicon 310a to 310d and heat treatment for the gate insulating film 306 are performed. These two processes are performed simultaneously. By this treatment, the content of the metal element in the crystalline silicon 311 to 314 can be reduced or removed. Silicon oxides 309a to 309d and amorphous silicon 310a to 310d are removed by etching after RTA.
In this RTA, the amorphous silicon films 310a to 310d absorb the light of RTA, and the gate insulating film 304 is heat-treated at the same time. However, since the amorphous silicon film 310 is crystallized when heated at a high temperature and the gettering characteristics are deteriorated, the gettering characteristics are lowered. Ring treatment and heat treatment can be performed simultaneously.
The RTA treatment is preferably performed using the RTA method at a temperature of 600 to 800 degrees and a short time of about 1 to 240 seconds. At this time, the semiconductor layer and the gate insulating film are heated to about 700 ° C. due to the difference in heat absorption rate of each material, but the temperature of the substrate 300 becomes about 400 ° C., so that damage to the substrate 300 is suppressed. can do. In addition, by performing rapid heating for about 1 to 240 seconds, even in the above temperature range, the same effect can be obtained even for a thermally fragile glass substrate having a strain point of 700 degrees or less and distortion due to heat can be obtained. It becomes possible to suppress. In addition, since it is sufficient to perform RTA only on the portion where the TFT is formed, a region to be heated at a time can be reduced, and damage to the substrate can be suppressed.
Further, by heat treatment on the gate insulating film, minute silicon clusters taken into the film can be oxidized or nitrided, and internal strain can be relaxed to reduce the defect density in the film and the interface defect density.
[0046]
After that, semiconductor layers 311 to 314 were formed by patterning using a photolithography method (FIG. 4D). A top view at this time is shown in FIG. Note that after the semiconductor layers 311 to 314 are formed, a small amount of impurity element (boron or phosphorus) may be doped (channel doping) in order to control the threshold value of the TFT.
[0047]
Note that the semiconductor layers 311 to 314 are not limited to an amorphous semiconductor film, and a compound semiconductor film having an amorphous structure such as a microcrystalline semiconductor film, a crystalline semiconductor film, or an amorphous silicon germanium film may be formed. Good.
[0048]
Next, a resist mask 315 is formed by photolithography, a first doping process is performed, and an impurity element imparting n-type conductivity is added to the semiconductor layers 311 to 314 at a low concentration (FIG. 5A). ). The first doping process may be performed by an ion doping method or an ion implantation method. In this embodiment, the dose amount is 5.0 × 10 5 by ion doping. 13 /cm 2 Impurity regions 316 to 319 were formed in a self-aligning manner using an acceleration voltage of 50 keV and P (phosphorus) as an impurity element imparting N-type conductivity. At this time, the impurity regions 316 to 319 have 1 × 10 18 ~ 1x10 20 /cm Three An impurity element imparting N-type was added in a concentration range of.
[0049]
Subsequently, after removing the resist mask 315, a new resist mask 320 is formed, and a second doping process is performed at a higher acceleration voltage than the first doping process (FIG. 5B). In this embodiment, the dose amount is 3.0 × 10 15 /cm 2 As a result of performing the doping process under the condition of the acceleration voltage of 65 keV, the impurity regions 321 and 322 are 1 × 10 19 ~ 5x10 twenty one /cm Three An impurity element imparting N-type was added in a concentration range of. In addition, channel formation regions 323 and 324 are formed.
[0050]
Next, after removing the resist mask 320, a resist mask 325 is newly formed (FIG. 5C). Thereafter, a third doping process is performed. In this embodiment mode, a resist mask 325 is used as a mask for the impurity element, an impurity element imparting p-type conductivity is added, and impurity regions 326 and 327 are formed in a self-aligning manner. The dose is 1 × 10 16 /cm 2 Under the condition that the acceleration voltage is 80 keV, diborane (B 2 H 6 ) Using an ion doping method. By this treatment, the concentration of the impurity element imparting P-type is 1 × 10. 19 ~ 5x10 twenty one atoms / cm Three It was doped so as to be. In addition, channel formation regions 328 and 329 were formed.
[0051]
Note that a desired impurity region may be formed by two or more times of doping treatment by appropriately changing the conditions for performing the doping treatment.
[0052]
Next, heat treatment (heat treatment) is performed to recover the crystallinity of the semiconductor layer and to activate the impurity element added to the semiconductor layer. This heat treatment is performed using a known method such as a thermal annealing method using a furnace annealing furnace. The thermal annealing method may be performed at 400 to 700 ° C. in a nitrogen atmosphere with an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. In this embodiment, heat treatment is performed at 410 ° C. for 1 hour using a furnace annealing furnace. In addition to the thermal annealing method, a laser annealing method or an RTA method may be used.
[0053]
Next, the resist mask 325 is removed, and a first interlayer insulating film 330 made of an insulating film is formed (FIG. 5D). As the first interlayer insulating film 330, in this embodiment, a silicon oxynitride film 330 having a thickness of 100 nm is formed by a plasma CVD method.
[0054]
A second interlayer insulating film 331 is formed on the first interlayer insulating film 330. In this embodiment, the acrylic film 103 having a thickness of 1.6 μm is formed as the second interlayer insulating film 331 by a CVD method. Note that the second interlayer insulating film 331 is preferably a film having excellent flatness because it has a strong meaning of alleviating unevenness due to the TFT formed on the substrate 300 and flattening.
[0055]
Next, a third interlayer insulating film 332 is formed over the second interlayer insulating film 331. As the third interlayer insulating film 332, in this embodiment, the silicon nitride film 51 is formed with a thickness of 0.1 μm by a sputtering method.
[0056]
Next, contact holes are formed by dry etching or wet etching (FIG. 1B). In this embodiment mode, the first to third interlayer insulating films 330 to 332 are etched to form contact holes reaching the impurity regions 321, 322, 326, and 327.
[0057]
Next, wirings 333 to 339 electrically connected to the impurity regions are formed. In this embodiment, the wirings 333 to 339 are formed by continuously forming a Ti film with a thickness of 100 nm, an Al film with a thickness of 350 nm, and a Ti film with a thickness of 100 nm by sputtering, and patterning and etching into a desired shape. Formed. Note that the structure is not limited to a three-layer structure, and may be a structure having two or less layers or a stacked structure having four or more layers. The wiring material is not limited to Al and Ti, and other conductive films may be used.
[0058]
Through the above steps, a pixel having a drive circuit portion having a CMOS circuit composed of an N-channel TFT 340 and a P-channel TFT 341, an N-channel TFT (switching TFT) 342, and a P-channel TFT (drive TFT) 343. Can be formed on the same substrate
[0059]
The N-channel TFT 340 in the driver circuit portion includes a channel formation region 323 that overlaps with the gate electrode 302 and an impurity region 321 that functions as a source region or a drain region. A P-channel TFT 341 that is connected to the N-channel TFT 340 through a wiring 334 to form a CMOS circuit has a channel formation region 328 that overlaps with the gate electrode 303 and an impurity region 326 that functions as a source region or a drain region.
[0060]
The N-channel TFT 342 in the pixel portion includes a channel formation region 324 that overlaps with the gate electrode 304 and an impurity region 322 that functions as a source region or a drain region. In addition, the P-channel TFT 343 includes a channel formation region 329 that overlaps with the gate electrode 305 and an impurity region 327 that functions as a source region or a drain region.
[0061]
In this embodiment mode, the heat treatment of the gate insulating film and the gettering treatment of the impurity element added to the crystalline semiconductor are simultaneously performed using rapid thermal annealing (RTA). When RTA is performed, heat is absorbed by the amorphous semiconductor, and since instantaneous thermal annealing is performed only on a desired portion, heat treatment can be performed without adversely affecting the substrate. Productivity can be improved by this invention which has the said structure.
[0062]
This embodiment can be freely combined with Embodiment 1.
[0063]
(Embodiment 3)
In the above embodiment 2, as shown in FIG. 4B, after the amorphous silicon film 307 is formed, a solution containing a metal element 308 is applied to promote crystallization of the silicon film. . However, other methods described below may be used.
[0064]
First, as illustrated in FIG. 4A, a base film 301 is formed over a substrate 300, and gate electrodes 302 to 305 are formed over the base film 301. Thereafter, a gate insulating film 306 is formed so as to cover the gate electrodes 302 to 305. Next, an amorphous silicon film is formed so as to be in contact with the gate insulating film 306. Then, after patterning the amorphous silicon film into a desired shape, RTA is performed on the amorphous silicon film and the gate insulating film 306. Then, the crystallization process of the amorphous silicon film and the heat treatment of the gate insulating film 309 can be performed at the same time. At this time, heat is absorbed by the amorphous silicon film, and instantaneous thermal annealing is performed only at a desired location, so that heat treatment can be performed without adversely affecting the substrate. The subsequent steps may be performed as shown in the above-described embodiment 2 (FIGS. 5A to 5D).
[0065]
This embodiment can be freely combined with Embodiments 1 and 2.
[0066]
(Embodiment 4)
An embodiment of the present invention will be described with reference to FIGS. In this embodiment mode, a cross-sectional structure in the case where a display device is formed using the TFT of the present invention will be described.
[0067]
After the TFTs arranged in the driver circuit portion and the pixel portion are formed over the insulating surface by the manufacturing process described in Embodiment Mode 1 (FIG. 1A), the TFT is electrically connected to the wiring 239 of the driver TFT 245. As described above, the first electrode 125 made of a transparent conductive film is formed. As the transparent conductive film, it is desirable to use a material having a high work function. For example, indium oxide and tin oxide compound (ITO), indium oxide and zinc oxide compound, zinc oxide, tin oxide, indium oxide And titanium nitride. In this embodiment, an ITO film with a thickness of 0.1 μm is formed as the first electrode 125 by a sputtering method.
[0068]
In this embodiment mode, after the wiring 239 is formed, the transparent conductive film is formed so as to be electrically connected to the wiring 239. However, another method may be used. For example, after forming a transparent conductive film and patterning the transparent conductive film, the TFT wiring 239 may be formed. A cross-sectional structure at that time is shown in FIG. Further, after the TFT wiring 239 is formed, an insulating film is formed, and then a contact hole is opened in the insulating film so as to reach the wiring 239. A transparent conductive film may be formed so as to be electrically connected to the wiring 239. A cross-sectional structure at that time is shown in FIG.
[0069]
Next, an insulating film 128 is formed so as to cover the end surface of the first electrode 125. The material for forming the insulating film 128 is not particularly limited, and the insulating film 128 can be formed using an inorganic or organic material. However, when the insulating film 128 is formed using a photosensitive organic material, the shape of the opening is different from that formed when the light emitting layer is deposited. This is preferable because it is difficult for cutting and the like to occur. For example, when a negative photosensitive resin is used as the material of the insulating film 128, a curved surface having a first radius of curvature at the upper end portion of the insulating film 128 and the lower end portion of the insulating film 128 as shown in FIG. Are formed to have a curved surface having a second radius of curvature. The first and second radii of curvature are preferably 0.2 μm to 3 μm, and the angle of the wall surface of the opening with respect to ITO is preferably 35 ° or more. When a positive photosensitive resin is used, the shape of the opening is a curved surface having a radius of curvature at the upper end of the insulating film as shown in FIG. Further, when the opening of the insulating film 128 is formed by dry etching, the shape is as shown in FIG.
[0070]
Then, it wipes using a PVA (polyvinyl alcohol) type porous body and removes dust and the like. In this embodiment, fine powder (dust) generated when the ITO or insulating film is etched is removed by wiping using a PVA porous material.
[0071]
Next, the light-emitting layer 126 is formed so as to be in contact with the first electrode 125. The light emitting layer 126 is formed by a vapor deposition method or a coating method (such as a spin coating method or an ink jet method). In this embodiment, vapor deposition was performed using the vapor deposition apparatus while moving the vapor deposition source. For example, the degree of vacuum is 5 × 10 -3 Torr (0.665 Pa) or less, preferably 10 -Four -10 -6 Deposition was performed in a deposition chamber evacuated to Torr. At the time of vapor deposition, the organic compound is vaporized in advance by resistance heating, and is scattered in the direction of the substrate by opening the shutter at the time of vapor deposition. That is, the vaporized organic compound was scattered upward and deposited on the substrate through the opening provided in the metal mask, whereby the light emitting layer 256 was formed.
[0072]
In addition, you may apply | coat PEDOT to the whole and perform baking for the vapor deposition pre-processing of the light emitting layer 126. FIG. At this time, since PEDOT does not have good wettability with ITO, it is preferable to apply PEDOT once, wash with water, and apply PEDOT again. Then, after heating at normal pressure to remove moisture, heating is performed in a reduced pressure atmosphere.
[0073]
In the present invention, one or a plurality of layers provided between the first and second electrodes constituting the light emitting element are collectively referred to as a light emitting layer 126. The light-emitting layer 126 can be formed using a low molecular weight organic compound material, a high molecular weight organic compound material, or an appropriate combination of both. Alternatively, a mixed layer in which an electron transporting material and a hole transporting material are appropriately mixed, or a mixed junction in which a mixed region is formed at each joint interface may be formed. In addition to organic materials, inorganic light emitting materials may be used. Further, the structure of the light emitting layer 126 is not particularly limited, and may be a structure in which layers made of a low molecular material are laminated, or a structure in which a layer made of a polymer material and a layer made of a low molecular material are laminated.
[0074]
Subsequently, a second electrode 127 is formed over the light emitting layer 126. The second electrode 127 is formed using a thin film including a metal (Li, Mg, Cs) having a small work function and a stacked film including a transparent conductive film stacked over a thin film including Li, Mg, or the like. The film thickness may be appropriately set so as to act as a cathode, but is formed to a thickness of about 0.01 to 1 μm by a known method (electron beam evaporation method or the like). However, when the electron beam evaporation method is used, if the acceleration voltage is too high, radiation is generated and the TFT is damaged. However, even if the acceleration voltage is too low, the film forming speed is lowered and productivity is lowered. Therefore, the second electrode 127 is not formed excessively than the film thickness that can function as a cathode. When the second electrode 127 is thin, the productivity is not greatly affected even when the deposition rate is low. However, although the problem of high resistance due to the thin film thickness of the cathode also occurs, it can be solved by forming a low resistance metal Al or the like on the cathode by resistance heating vapor deposition or sputtering method, etc. to form a laminated structure. To do. In this embodiment, Al—Li is formed to a thickness of 0.1 μm as the second electrode 127 by an electron beam evaporation method.
[0075]
Next, a protective film 129 is formed over the insulating film 128 and the second electrode 127. As the protective film 129, a film that hardly transmits a substance that causes deterioration of the light-emitting element such as moisture or oxygen as compared with other insulating films is used. Typically, it is desirable to use a DLC film, a carbon nitride film, a silicon nitride film formed by an RF sputtering method, or the like. The film thickness is preferably about 10 to 200 nm. In this embodiment mode, the silicon nitride film is formed with a thickness of 100 nm by a sputtering method.
[0076]
A stacked body of the first electrode 125, the light emitting layer 126, and the second electrode 127 formed in the steps up to here corresponds to the light emitting element 130. The first electrode 125 corresponds to an anode, and the second electrode 127 corresponds to a cathode. In the present invention, the excited state of the light emitting element 130 includes singlet excitation and triplet excitation, but light emission may pass through either excited state.
[0077]
FIG. 6B is a top view of one pixel in a display device using a light-emitting element. FIG. 6B shows a state where up to the pixel electrode 125 is formed. In the top view of FIG. 6B, a cross-sectional view corresponding to ABC is equivalent to FIG. FIG. 6C shows a circuit diagram of one pixel corresponding to FIG. 6B and 6C, reference numerals 204 and 205 denote metal layers, 121 a source line, 122 a gate line, 123 a power supply line, 124 a capacitor, 125 a first electrode (pixel electrode), and 244 Switching TFTs 245 correspond to driving TFTs.
[0078]
In this embodiment mode, a case where so-called bottom emission is performed in which light emitted from the light emitting element 30 is extracted from the substrate 200 side (bottom surface) is shown. However, so-called top emission, in which light is extracted from the surface of the substrate 200, may be performed. In that case, the first electrode 125 may be formed to correspond to a cathode, the second electrode 127 may be formed to correspond to an anode, and the second electrode 127 may be formed using a transparent material. The driving TFT 245 is preferably formed using an N-channel TFT. Note that the conductivity type of the driving TFT 245 may be changed as appropriate, but the capacitor element 124 is disposed so as to hold the gate-source voltage of the driving TFT 245. Note that this embodiment mode shows the case of a light-emitting device using the thin film transistor and the light-emitting element of the present invention; however, the present invention may be used for other display devices such as a liquid crystal display device.
[0079]
This embodiment can be freely combined with Embodiments 1 and 2.
[0080]
(Embodiment 5)
An embodiment of the present invention will be described with reference to FIG. FIG. 8 is a top view of a display panel formed by sealing a substrate on which a TFT is formed with a sealing material, and FIG. 8B is a cross-sectional view taken along the line BB ′ of FIG. 8C and 8D are cross-sectional views taken along line AA ′ of FIG. 8C is a cross-sectional view of a display panel that emits light from the bottom surface that emits light in the direction of the TFT substrate, and FIG. 8D is a cross-sectional view of a display panel that emits light from the top surface that emits light in the direction of the counter substrate.
[0081]
8A to 8D, on a substrate 401, a pixel portion (display portion) 402, a signal line driver circuit 403 and scan line driver circuits 404a and 404b provided so as to surround the pixel portion 402 are provided. The sealing material 406 is provided so as to surround them. For the structure of the pixel portion 402, the above embodiment and the description thereof may be referred to. As the sealing material 406, a glass material, a metal material (typically a stainless steel material), a ceramic material, or a plastic material (including a plastic film) is used.
[0082]
The sealant 406 may be provided so as to overlap with part of the signal line driver circuit 403 and the scan line driver circuits 404a and 404b.
In the display panel illustrated in FIG. 8C, a sealing material 407 is provided using a sealing material 406, and a sealed space 408 is formed by the substrate 401, the sealing material 406, and the sealing material 407. The sealing material 407 is previously provided with a hygroscopic agent (barium oxide, calcium oxide, or the like) 409 in the recess, and adsorbs moisture, oxygen, or the like inside the sealed space 408 to maintain a clean atmosphere. Plays a role in suppressing deterioration. This recess is covered with a fine mesh-like cover material 410. The cover material 410 allows air and moisture to pass but does not allow the moisture absorbent 409 to pass. Note that the sealed space 408 may be filled with a rare gas such as nitrogen or argon, and may be filled with a resin or a liquid if inactive.
8D, a transparent counter substrate 421 is provided using a sealant 406, and a sealed space 422 is formed by the substrate 401, the counter substrate 421, and the sealant 406. The counter substrate 421 is provided with a color filter 420 and a protective film 423 for protecting the color filter. Light emitted from the light-emitting elements arranged in the pixel portion 402 is emitted to the outside through the color filter 420, and the display panel performs multicolor display. The sealed space 422 is filled with an inert resin or liquid. When performing multicolor display, the light emitting layer is set to emit each color of RGB, or a pixel provided with a light emitting layer that emits white light is disposed and a color filter or a color conversion layer is used. It may be set.
[0083]
An input terminal portion 411 for transmitting a signal to the signal line driver circuit 403 and the scanning line driver circuits 404a and 404b is provided on the substrate 401. Data such as a video signal is input to the input terminal portion 411 via the FPC 412. A signal is transmitted. A cross section of the input terminal portion 411 is as shown in FIG. 8B. An input wiring 413 including a wiring formed simultaneously with a scanning line or a signal line and a wiring 415 provided on the FPC 412 side are connected to a conductor 416. Is electrically connected using a resin 417 in which is dispersed. Note that the conductor 416 may be a spherical polymer compound that is plated with gold or silver.
[0084]
In this embodiment mode, an example in which the present invention is applied to a light-emitting panel using a light-emitting element is described; however, the present invention may be applied to a liquid crystal panel using a liquid crystal display element.
[0085]
This embodiment can be freely combined with Embodiments 1 to 3.
[0086]
(Embodiment 6)
As an electronic device to which the present invention is applied, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio, audio component, etc.), a notebook type personal computer, a game machine, portable information Plays back a recording medium such as a terminal (mobile computer, mobile phone, portable game machine or electronic book), and a recording medium (specifically, Digital Versatile Disc (DVD)) and displays the image. And the like). Specific examples of these electronic devices are shown in FIGS.
[0087]
FIG. 9A illustrates a light-emitting device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The present invention can be applied to the display portion 2003. Since the light-emitting device is a self-luminous type, a backlight is not necessary and a display portion thinner than a liquid crystal display can be obtained. Note that the light emitting device includes all display devices for displaying information such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.
[0088]
FIG. 9B shows a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The present invention can be applied to the display portion 2102.
[0089]
FIG. 9C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention can be applied to the display portion 2203.
[0090]
FIG. 9D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The present invention can be applied to the display portion 2302.
[0091]
FIG. 9E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. Although the display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information, the present invention can be applied to the display portions A, B 2403, and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0092]
FIG. 9F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. The present invention can be applied to the display portion 2502.
[0093]
FIG. 9G shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and the like. . The present invention can be applied to the display portion 2602.
[0094]
FIG. 9H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The present invention can be applied to the display portion 2703. Note that the display portion 2703 can suppress current consumption of the mobile phone by displaying white characters on a black background.
[0095]
As described above, the applicable range of the present invention is so wide that it can be used for electronic devices in various fields. In addition, any of the configurations described in Embodiments 1 to 5 may be used for the electronic device of this embodiment.
[0096]
【The invention's effect】
In the present invention, instantaneous thermal annealing (RTA, local heating) is performed using a lamp (typically a halogen lamp) that performs heat treatment only at a desired location. Furthermore, in the present invention, instantaneous thermal annealing is performed after a metal layer or an amorphous semiconductor that absorbs heat is provided on a substrate. Then, the semiconductor and the gate insulating film of the thin film transistor are heated to about 700 degrees, but the temperature of the substrate becomes about 400 degrees, and damage to the substrate can be prevented. In the present invention, two processes of a heat treatment for the gate insulating film and an activation process for the impurity element added to the semiconductor or a gettering step for the metal element added to the semiconductor are simultaneously performed using RTA. Furthermore, since RTA can be performed in a short time, the present invention is expected to improve productivity.
[0097]
Further, in the present invention, a gate insulating film is manufactured using a sputtering apparatus that uses an inert gas and has a simple configuration. Furthermore, the present invention provides a dielectric constant of a thin film used for each layer in order to form a gate insulating film thick enough to obtain a desired withstand voltage and to make it difficult to reduce the capacitance between the semiconductor constituting the TFT and the gate electrode. Is set so that a desired capacitance can be obtained as a TFT. Specifically, the gate insulating film has a two-layer structure, and the two-layer gate insulating film is continuously formed by a sputtering method. The first layer of the gate electrode / gate insulating film is a silicon nitride film (dielectric constant: about 7.5) / the second layer of the gate insulating film is a silicon oxide film (dielectric constant: about 3.5) / active layer Laminate sequentially. Then, by performing the instantaneous thermal annealing on the gate insulating film, its CV characteristics (capacitance voltage dependency) are improved, the hysteresis is improved, and the reliability is improved.
[0098]
[Brief description of the drawings]
FIG. 1 shows a cross-sectional structure of a thin film transistor of the present invention.
FIGS. 2A to 2C illustrate a manufacturing process of a thin film transistor of the present invention. FIGS.
FIGS. 3A to 3C illustrate a manufacturing process of a thin film transistor of the present invention. FIGS.
4A to 4C illustrate a manufacturing process of a thin film transistor of the present invention.
FIGS. 5A and 5B illustrate a manufacturing process of a thin film transistor of the present invention. FIGS.
6 is a cross-sectional view of a thin film transistor of the present invention. FIG.
7 is a cross-sectional view of a thin film transistor of the present invention. FIG.
FIG. 8 shows a display panel.
FIG 9 illustrates an electronic device.

Claims (4)

  1. Forming a metal layer on a glass substrate having a strain point of 700 ° C. or lower,
    Forming an insulating film on the metal layer;
    Forming a gate electrode on the insulating film so as to overlap the metal layer;
    A first gate insulating film made of silicon nitride and a second gate insulating film made of silicon oxide are continuously formed on the gate electrode by a sputtering method,
    Forming a first amorphous semiconductor layer on the second gate insulating film so as to overlap the gate electrode;
    Forming a crystalline semiconductor layer by adding and heating a metal element to the first amorphous semiconductor layer;
    Forming a second amorphous semiconductor layer on the crystalline semiconductor layer;
    The first gate insulating film and the second gate insulating film, and the crystalline semiconductor layer and the second amorphous semiconductor layer are locally heated by RTA at a temperature of 600 to 800 ° C. for 1 to 240 seconds. Process,
    A method for manufacturing a semiconductor device, characterized by diffusing the metal element contained in the crystalline semiconductor layer into the second amorphous semiconductor layer.
  2. On a glass substrate having a strain point of 700 ° C. or lower, a metal layer is formed using any one of tungsten silicide, silver, and tantalum nitride ,
    Forming a gate electrode so as to overlap the metal layer;
    A first gate insulating film made of silicon nitride and a second gate insulating film made of silicon oxide are continuously formed on the gate electrode by a sputtering method,
    Forming a first amorphous semiconductor layer on the second gate insulating film so as to overlap the gate electrode;
    Forming a crystalline semiconductor layer by adding and heating a metal element to the first amorphous semiconductor layer;
    Forming a second amorphous semiconductor layer on the crystalline semiconductor layer;
    The first gate insulating film and the second gate insulating film, and the crystalline semiconductor layer and the second amorphous semiconductor layer are locally heated by RTA at a temperature of 600 to 800 ° C. for 1 to 240 seconds. Process,
    A method for manufacturing a semiconductor device, characterized by diffusing the metal element contained in the crystalline semiconductor layer into the second amorphous semiconductor layer.
  3. On a glass substrate having a strain point of 700 ° C. or lower, a metal layer is formed using any one of tungsten silicide, silver, and tantalum nitride ,
    Forming an insulating film on the metal layer;
    Forming a gate electrode on the insulating film so as to overlap the metal layer;
    A first gate insulating film made of silicon nitride and a second gate insulating film made of silicon oxide are continuously formed on the gate electrode by a sputtering method,
    Forming a first amorphous semiconductor layer on the second gate insulating film so as to overlap the gate electrode;
    Forming a crystalline semiconductor layer by adding and heating a metal element to the first amorphous semiconductor layer;
    Forming a second amorphous semiconductor layer on the crystalline semiconductor layer;
    The first gate insulating film and the second gate insulating film, and the crystalline semiconductor layer and the second amorphous semiconductor layer are locally heated by RTA at a temperature of 600 to 800 ° C. for 1 to 240 seconds. Process,
    A method for manufacturing a semiconductor device, characterized by diffusing the metal element contained in the crystalline semiconductor layer into the second amorphous semiconductor layer.
  4. In any one of claims 1 to 3, the method for manufacturing a semiconductor device, wherein the metal element is nickel.
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