JP2007123297A - Semiconductor device and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor device having a capacitor element which can be miniaturized while increasing the capacity and in which failures such as dielectric breakdown and leakage current are reduced. <P>SOLUTION: The semiconductor device comprises a thin film transistor and a capacitor element 42 on an insulating substrate wherein the thin film transistor comprises a semiconductor layer 43 having a channel 43c, and a source 43s and a drain 43d arranged on the side of the channel 43c, a first insulation film 3 arranged on the channel 43c, and a first electrode 5 located on the first insulation film 3 oppositely to the channel 43c. The capacitor element 42 comprises a first electrode 5, a second insulation film 4 and a second electrode 6 arranged in this order from the insulating substrate side, and the outer edge of the second electrode 6 is located on the outer edge of the first electrode 5 or on the inside thereof. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a semiconductor device and a manufacturing method thereof. More specifically, a semiconductor device suitable for an active matrix substrate used for a display device such as a liquid crystal display device or an organic electroluminescence display device, a manufacturing method thereof, a power supply circuit obtained using them, an active matrix substrate, and a display It relates to the device.

A semiconductor device is an electronic device that includes an active element that utilizes electrical characteristics of a semiconductor, and is widely applied to, for example, audio equipment, communication equipment, computers, and home appliances. In particular, a semiconductor device including a three-terminal active element such as a thin film transistor (hereinafter also referred to as “TFT”) or a MOS (Metal Oxide Semiconductor) transistor is a display such as an active matrix liquid crystal display device (hereinafter also referred to as “liquid crystal display”). In the apparatus, it is used as a switching element provided for each pixel, a control circuit for controlling each pixel, and the like, thereby enabling high-definition display and high-speed moving image display.

In recent years, with respect to display devices such as liquid crystal display devices, with higher display quality, higher aperture ratio and higher brightness in pixels are required. Here, examples of the constituent member that hinders the opening of the pixel include a TFT in the pixel portion, wiring for driving and controlling the TFT in the pixel portion, a capacitor element, and the like. Among these, in particular, the occupied area of the capacitive element installed to hold the pixel potential is large, and further downsizing of the capacitive element is strongly demanded.

Therefore, in order to realize a high aperture ratio of the pixel, the capacitance per unit surface area of the capacitive element is increased by thinning the upper insulating film disposed between the capacitive element electrodes of the capacitive element, and the capacitive element Has been disclosed (for example, see Patent Document 1). However, in order to reduce the thickness of the upper insulating film, an etching process is required, and it is difficult to control the film thickness of each capacitor element, and there is room for improvement in that the capacitance varies.

On the other hand, the TFT of the drive circuit section has a gate overlap LDD structure (GOLD structure) including a second gate insulating film and a second gate electrode, and the capacitor element is formed from the lower layer to the semiconductor layer, the first gate insulating. A semiconductor device formed of a film, a first gate electrode, a second gate insulating film, and a second gate electrode is disclosed (see, for example, Patent Document 2). According to this, since the capacitor electrode is composed of the three electrodes of the semiconductor layer, the first gate electrode, and the second gate electrode, the capacitance per unit area is increased, and the capacitor element can be reduced in size. However, in this semiconductor device, dielectric breakdown and leakage current are likely to occur near the capacitive element, and there is room for further improvement.
Therefore, in order to increase the capacity and size of the capacitive element, there is still room for improvement in terms of reducing defects such as capacitance variation, dielectric breakdown, and leakage current.
JP 2003-241687 A JP 2005-57167 A

The present invention has been made in view of the above-described situation, and an object thereof is to provide a semiconductor device having a capacitive element that can be increased in capacity and reduced in size, and has reduced defects such as dielectric breakdown and leakage current. It is what.

The inventor conducted various studies on a semiconductor device having a capacitive element that can be increased in capacity and reduced in size and reduced in defects such as dielectric breakdown and leakage current. In the semiconductor device described in Patent Document 2, It has been found that since the first gate electrode of the capacitor electrode has a region protruding outside the lower semiconductor layer, electric field concentration is likely to occur in that region, and defects such as dielectric breakdown are likely to occur. Therefore, the present inventor further studied, and in the configuration of the capacitive element, the first electrode, the second insulating film, and the second electrode are arranged in this order, and the side surface of the first electrode is more than the side surface of the second electrode. By finding that it is located on the outside, it has been found that the capacity of the capacitor element can be increased, reduced in size, and reduced in defects, and the inventors have conceived that the above problems can be solved brilliantly and have reached the present invention. Is.

That is, the present invention is a semiconductor device including a thin film transistor and a capacitor over an insulating substrate, and the thin film transistor is disposed on a channel, a semiconductor layer having a source and a drain disposed beside the channel, and the channel. The capacitor element includes a first insulating film and a first electrode disposed at a position facing the channel on the first insulating film. The capacitor element is insulated from the first electrode, the second insulating film, and the second electrode. The semiconductor device is arranged in this order from the substrate side, and the outer edge of the second electrode is located inside or on the outer edge of the outer edge of the first electrode.
The present invention is described in detail below.

The semiconductor device of the present invention includes a thin film transistor and a capacitor over an insulating substrate. Accordingly, the TFT and the capacitor can be connected, and the potential supplied from the TFT can be held in the capacitor. The insulating substrate is not particularly limited as long as it has an insulating surface, but a glass substrate or the like is preferably used.

The thin film transistor includes a channel, a semiconductor layer having a source and a drain disposed beside the channel, a first insulating film disposed on the channel, and a first layer disposed at a position facing the channel on the first insulating film. Electrode. Here, in the TFT, the first insulating film functions as a gate insulating film, and the first electrode functions as a gate electrode.
The material constituting the semiconductor layer is not particularly limited, but can be formed by a low-temperature process and has excellent field effect mobility. Therefore, continuous grain boundary crystalline silicon (CG silicon), polycrystalline silicon (polysilicon) Etc. are preferred. Moreover, the dimension of a semiconductor layer is not specifically limited.
In the source and drain, the semiconductor layer is usually doped with N-type or P-type impurities. Impurities are ions (atoms) that generate carriers (holes or electrons) in a semiconductor. Holes are carriers in the P-type impurity region, and electrons are carriers in the N-type impurity region. Examples of the N-type impurity include phosphorus, and examples of the P-type impurity include boron.
The material of the first insulating film is not particularly limited, and examples thereof include silicon dioxide (SiO ₂ ) and silicon nitride (SiNx; x is an arbitrary number). Moreover, the dimension of a 1st insulating film is not specifically limited.
The material of the first electrode is not particularly limited, but a refractory metal such as tungsten (W), molybdenum (Mo), tantalum (Ta), titanium (Ti), nitride of the refractory metal, aluminum (Al), etc. Is preferred. The configuration of the gate electrode is not particularly limited, and a stack of two or more materials may be used. Moreover, the dimension of a 1st electrode is not specifically limited.

In the capacitive element, the first electrode, the second insulating film, and the second electrode are arranged in this order from the insulating substrate side. Here, in the capacitor element, the first electrode functions as a lower layer capacitor electrode, the second insulating film functions as a dielectric film, and the second electrode functions as an upper layer capacitor electrode. Thus, by providing the second insulating film for the dielectric film of the capacitor element separately from the first insulating film that is the gate insulating film of the TFT, an insulating film having characteristics suitable for the capacitor element can be used. Therefore, it is possible to reduce the thickness of the second insulating film, adopt a high dielectric constant insulating film, or the like.
The material of the second insulating film is not particularly limited, but a material having a dielectric constant larger than that of the first insulating film is preferable. For example, tantalum oxide such as ditantalum pentoxide (Ta ₂ O ₅ ), dialuminum trioxide (Al _And aluminum oxide such as ₂ O ₃ ). Further, the thickness of the second insulating film is not particularly limited.
The material of the second electrode is not particularly limited, and substantially the same material as the first electrode in the TFT can be used. Moreover, the dimension of a 2nd electrode is not specifically limited.
As the material of the first electrode of the capacitive element, generally the same material as that of the first electrode in the TFT is used. As a result, the first electrode as the gate electrode of the TFT and the first electrode as the lower-layer capacitor electrode of the capacitor element can be simultaneously patterned, so that the manufacturing process can be simplified. In addition, the dimension of the first electrode in the capacitive element is not particularly limited, but the film thickness is generally substantially the same as the first electrode in the TFT from the same viewpoint.

In the capacitive element, the outer edge of the second electrode is located on the inner side or on the outer edge of the outer edge of the first electrode. Usually, the insulating film formed on the electrode has a tendency that the film thickness at the end of the electrode is thin and the covering property tends to be poor, and the electrode end has a step, and the electric field tends to concentrate on the shape. Therefore, when the upper electrode of the capacitive element is larger than the lower electrode, a short circuit or a leak current is likely to occur at the end of the lower electrode. Therefore, in the capacitive element, the second electrode (upper layer electrode) does not protrude from the first electrode (lower layer electrode), and is disposed within the first electrode surface or in alignment with the first electrode, whereby the first electrode end It is possible to effectively suppress the occurrence of defects and inter-electrode leakage current due to short-circuiting between electrodes. As a result, the yield in the manufacturing process can be improved. Furthermore, since it is not necessary to consider the coverage of the end portion of the first electrode, the second insulating film, which is a dielectric film, can be thinned, so that a capacitive element having a large capacity can be formed with a small area. It becomes.

The configuration of the semiconductor device of the present invention is not particularly limited as long as such a component is formed as an essential component, and may or may not include other components. .
A preferred embodiment of the semiconductor device of the present invention will be described in detail below.

In the present invention, at least one of the thin film transistors has a structure in which a low-concentration impurity region and a high-concentration impurity region are provided in order from the channel side at least in the drain, and further, on the first electrode, the second insulating film and It has a 2nd electrode in this order, It is preferable that the said 2nd electrode is electrically connected with the 1st electrode, and is arrange | positioned so that a low concentration impurity region may be covered at least. Here, the structure in which the low concentration impurity region and the high concentration impurity region are provided in order from the channel side is a so-called LDD (Lightly Doped Drain) structure. As described above, in the TFT, the second electrode functions as a second gate electrode, the second insulating film functions as an insulating film between the two gate electrodes, and has a GOLD structure, thereby increasing current driving force and carrier deterioration characteristics. Can be improved. Therefore, a TFT having such a GOLD structure is suitable for a semiconductor element constituting a peripheral driver circuit in a liquid crystal display device in which a peripheral driver circuit and a pixel are integrated, that is, a so-called monolithic liquid crystal display.
As the material of the second insulating film of the TFT, generally the same material as that of the second insulating film in the capacitive element is used. As a result, the second insulating film as the dielectric film of the capacitive element and the second insulating film as the insulating film between the first and second gate electrodes of the TFT can be patterned simultaneously. Simplification is possible. The film thickness of the second insulating film in the TFT is usually substantially the same as that of the second insulating film in the capacitive element from the same viewpoint.
As the material of the second electrode of the TFT, generally the same material as that of the second electrode in the capacitive element is used. Thereby, similarly to the second insulating film, the manufacturing process can be simplified. The dimension of the second electrode in the TFT is not particularly limited, but the film thickness is usually substantially the same as that of the second electrode in the capacitive element from the same viewpoint.
In this specification, “low concentration” and “high concentration” in the low concentration and high concentration impurity regions simply mean that the concentration of the impurity contained in one impurity region is relative to that in the other impurity region. It means low and high. In the present invention, as long as it can be confirmed that the impurity concentration of the low-concentration impurity region is different from that of the high-concentration impurity region, the boundary between these regions does not have to exist clearly.

In the present invention, the semiconductor device preferably includes an electrode (external electrode) connected to a potential different from that of the first electrode of the capacitor element in a region other than the lower portion of the first electrode of the capacitor element. Thus, since the first electrode and the external electrode of the capacitive element do not have a portion overlapping when viewed from the normal direction of the substrate, even when the interelectrode insulating film between the first electrode and the external electrode of the capacitive element is thin, It is possible to effectively suppress the occurrence of defects due to a short circuit or the like. Examples of the external electrode include an electrode constituting a TFT and a wiring for driving / controlling the TFT.
In the present invention, in the semiconductor device, it is particularly preferable that the semiconductor layer is provided in a region other than the lower portion of the first gate electrode of the capacitor. When crystalline silicon is used for a semiconductor layer of a TFT, a silicon layer crystallized with a laser is usually used in many cases. At this time, the silicon surface formed by laser crystallization has projection-shaped unevenness (silicon ridge), and electric field concentration is likely to occur at this location, so that it becomes a leakage current generation source of the capacitive element. In particular, the silicon ridge formed at the end of the silicon electrode deteriorates the insulating film coverage of the upper layer, causing problems such as an increase in leakage current and breakdown of the insulating film. Therefore, by not providing the semiconductor layer below the first electrode of the capacitor element, the occurrence of the defect can be effectively suppressed.

In the present invention, the semiconductor device preferably includes a capacitor wiring formed of substantially the same material as the first electrode. As a result, the first electrode of the capacitive element and the capacitive wiring can be integrally formed, so that the manufacturing process can be simplified.

In the present invention, the second insulating film preferably has a larger capacity per unit area than the first insulating film. Thereby, the area occupied by the capacitive element can be reduced as compared with the case where the dielectric film of the capacitive element is formed of the first insulating film which is the gate insulating film of the TFT. In addition, since the second insulating film is formed of an insulating film different from the first insulating film of the TFT, even if the capacity of the capacitor element is increased by reducing the thickness of the second insulating film, the insulating film withstand voltage of the TFT is reduced. There is nothing to do.
From the same viewpoint, the second insulating film is preferably formed of a material having a dielectric constant larger than that of the material of the first insulating film, and further has a film configuration different from that of the first insulating film. Is preferred. Since the dielectric film of the capacitor element is less necessary to consider the characteristic variation of the insulating film due to charge trapping or the like with respect to the gate insulating film of the thin film transistor, various high dielectric constant insulating films can be employed. Therefore, by using a high dielectric constant insulating film as the second insulating film, the capacitive element can be reduced in size. As the high dielectric constant insulating film, a SiN film formed by a CVD (Chemical Vapor Deposition) method, a compound such as an Al ₂ O ₃ film or a Ta ₂ O ₅ film formed by a sputtering method, a laminated film of the above compounds, or the like is used. be able to.
The second insulating film is preferably made of an oxide of the first electrode material. That is, it is preferable that the first electrode material is Al, Ta, or the like, the metal oxide film is formed by oxidizing the first electrode, and the second insulating film is formed. As a result, a metal oxide film, for example, an Al ₂ O ₃ film, a Ta ₂ O ₅ film, etc., which is a material having a higher dielectric constant than the SiO ₂ film generally used for the gate insulating film of the TFT, is formed uniformly and thinly. Since the capacitance per unit area of the capacitive element is increased, the capacitive element can be reduced. Examples of the oxidation method include anodic oxidation, thermal oxidation, and plasma oxidation.

In the present invention, the second electrode is preferably thinner than the first electrode. When the second electrode is used only as the second gate electrode for forming the GOLD structure and the upper capacitor electrode of the capacitor and not used as the wiring, the thickness of the second electrode is as thin as about 20 nm to 100 nm. It becomes possible to do. Thereby, since the level | step difference by a 2nd electrode becomes small, the coverage of the interlayer film, wiring electrode, etc. which are formed on a 2nd electrode becomes favorable. In addition, the processing capacity of production can be improved by thinning.

The present invention is also a method for manufacturing a semiconductor device having the GOLD structure, wherein the manufacturing method is also a method for manufacturing a semiconductor device in which a second insulating film is formed after patterning a first electrode. When forming a GOLD structure in which the gate electrode of the TFT is composed of a first electrode and a second electrode, and the second electrode and the low concentration impurity regions of the source and drain overlap, the first electrode pattern is formed in the lower layer. There is a possibility that a certain first insulating film is thinned by etching, and the withstand voltage between the first electrode and the source and drain is lowered. However, by forming the second insulating film after forming the first electrode pattern, it is possible to sufficiently ensure the withstand voltage between the second electrode on the second insulating film and the source and drain.

The present invention further relates to a method of manufacturing a semiconductor device having the GOLD structure, wherein the manufacturing method includes forming a second electrode after patterning the first electrode and the second insulating film with the same mask. It is also a manufacturing method. Thus, the second insulating film can be formed only on the upper surface of the first electrode by performing the first electrode and second insulating film pattern forming step. After that, by performing the second electrode forming step, the second electrode can be formed not only on the second insulating film but also on the side surface of the first electrode. It is possible to make an electrical connection without using a wiring. Therefore, it is not necessary to provide an extra contact hole formation region for electrically connecting the first electrode and the second electrode, and the TFT can be miniaturized.

The present invention is also a method for manufacturing a semiconductor device having the GOLD structure, wherein the manufacturing method includes doping a low concentration impurity using the first electrode as a mask, and doping a high concentration impurity using the second electrode as a mask. And a process for manufacturing the semiconductor device. Since both the low concentration impurity region and the high concentration impurity region of the source and drain are doped using the first electrode and the second electrode which are the gate electrodes of the TFT as masks, each impurity region has a self-aligned structure with respect to the gate electrode. Therefore, it is possible to form a TFT having a GOLD structure having no extra load capacity and load resistance.

The present invention is also a power supply circuit including the semiconductor device. Since the semiconductor device of the present invention includes a large-capacity capacitive element, it is suitable for a charge pumping circuit or the like used for a power supply circuit. The present invention is also an active matrix substrate including the semiconductor device. The semiconductor device of the present invention is suitable for an active matrix substrate used for a display device or the like because it includes a large capacity capacitor element and a thin film transistor having excellent TFT characteristics. The present invention is also a display device including the active matrix substrate. Since the display device of the present invention has a small and large-capacity capacitive element, it is possible to increase the aperture ratio of the pixel, and as a result, it is possible to increase the definition and increase the brightness of the display device. It is suitable for display devices and organic EL display devices.

According to the semiconductor device of the present invention, the gate insulating film of the thin film transistor and the dielectric film of the capacitor element have different film forms, so that the dielectric film can be made thinner and higher in capacity. In addition, by arranging the side of the upper capacitive electrode of the capacitive element in line with or on the inner side of the lower capacitive electrode, it is possible to effectively suppress defects due to short-circuit between electrodes at the end of the lower capacitive electrode and leakage current between electrodes. can do. As a result, it is possible to reduce the size and capacity of the capacitor element in the semiconductor device, and to reduce defects such as dielectric breakdown and leakage current.

EXAMPLES Although an Example is hung up below and this invention is demonstrated still in detail with reference to drawings, this invention is not limited only to these Examples.

Example 1
The semiconductor device of this embodiment will be described with reference to FIG. FIG. 1 is a schematic cross-sectional view showing the configuration of the semiconductor device of this example.
As shown in FIG. 1, the semiconductor device of the present embodiment includes a glass substrate 1 that is a transparent substrate, a base layer 2 formed on the glass substrate 1, a peripheral driver unit 20 and a pixel unit disposed on the base layer 2. 40. The peripheral driver unit 20 includes a CMOS (complementary MOS) circuit, and a P-type TFT 21 and an N-type TFT 22 are arranged. The pixel unit 40 includes a pixel TFT 41 and a capacitor element 42 that are switching elements. Here, the pixel TFT 41 has an N-type conductivity type. The pixel TFT 41 of this embodiment is a multi-gate type having two gate electrodes, but may be a single gate type having one gate electrode for each TFT.

The pixel TFT 41 includes a semiconductor layer 43 including an active region, a first insulating film 3 covering the semiconductor layer 43, two first electrodes 5 provided on the first insulating film 3, and each first electrode 5. The second insulating film 4 to be covered is arranged in this order. The semiconductor layer 43 is a so-called LDD in which a channel 43c disposed at a position facing each first electrode 5, and an N-type low-concentration impurity region 44 and an N-type high-concentration impurity region 45 are disposed in this order from the channel 43c side. It has a structure. Further, the semiconductor layer 43 between the two channels 43c has an arrangement of N-type low concentration impurity region 44 / N-type high concentration impurity region 45 / N-type low concentration impurity region 44. The outermost N-type low concentration impurity region 44 and N-type high concentration impurity region 45 function as the source 43s and the drain 43d of the pixel TFT 41. The first insulating film 3 and the second insulating film 4 are also formed in the same layer in the capacitor element 42 and the peripheral driver unit 20 described later. In the pixel TFT 41, the first insulating film 3 functions as a gate insulating film, and the first electrode 5 functions as a gate electrode.
Further, a source electrode 8 and a drain electrode 9 are formed on the pixel TFT 41 via an interlayer insulating film 7. Further, a contact hole 10 s penetrating the first insulating film 3, the second insulating film 4 and the interlayer insulating film 7 is formed above the N-type high concentration impurity region 45 of the source 43 s. The contact hole 10s is filled with a conductive material, and the source 43s and the source electrode 8 are connected. Similarly, a contact hole 10d penetrating the first insulating film 3, the second insulating film 4, and the interlayer insulating film 7 is formed above the N-type high concentration impurity region 45 of the drain 43d. The contact hole 10d is filled with a conductive material, and the drain 43d and the drain electrode 9 are connected. Further, the drain electrode 9 is connected to a second electrode 6 of a capacitive element 42 described later via a contact hole 10.

The capacitive element 42 is formed on the first insulating film 3 formed on the same layer as the pixel TFT 40, on the first electrode 5, on the second insulating film 4 covering the first electrode 5, and on the second insulating film 4. It has the formed 2nd electrode 6 in this order. Here, the 2nd electrode 6 is arrange | positioned so that there may be no area | region which protrudes from the 1st electrode 5 in a lower layer, when it sees from the glass substrate 1 normal line direction. In the capacitive element 42, the first electrode 5 functions as a lower layer capacitive electrode, the second insulating film 4 functions as a dielectric film, and the second electrode 6 functions as an upper layer capacitive electrode.
In addition, an interlayer insulating film 7 and a contact hole 10 penetrating the interlayer insulating film 7 are formed on the capacitor element 42. The contact hole 10 is filled with a conductive material, and the second electrode 6 and the drain electrode 9 of the pixel TFT 41 described above are connected.

The P-type TFT 21 of the peripheral driver unit 20 includes a semiconductor layer 43 including an active region, a first insulating film 3 covering the semiconductor layer 43, a first electrode 5 provided on the first insulating film 3, and a first It has the 2nd insulating film 4 which covers the electrode 5 in this order. The semiconductor layer 43 includes a source 43s and a drain 43d doped with a P-type impurity, and a channel 43c disposed at a position facing the first electrode 5 between the source 43s and the drain 43d. In the P-type TFT 21, the first insulating film 3 functions as a gate insulating film, and the first electrode 5 functions as a gate electrode.
Further, a source electrode 8 and a drain electrode 9 are formed on the P-type TFT 21 via an interlayer insulating film 7. Furthermore, a contact hole 10 s penetrating the first insulating film 3, the second insulating film 4 and the interlayer insulating film 7 is formed above the source 43 s. The contact hole 10s is filled with a conductive material, and the source 43s and the source electrode 8 are connected. Similarly, a contact hole 10d penetrating the first insulating film 3, the second insulating film 4, and the interlayer insulating film 7 is formed above the drain 43d. The contact hole 10d is filled with a conductive material, and the drain 43d and the drain electrode 9 are connected.

The N-type TFT 22 of the peripheral driver unit 20 includes a semiconductor layer 43 including an active region, a first insulating film 3 covering the semiconductor layer 43, a first electrode 5 provided on the first insulating film 3, and a first It has the 2nd insulating film 4 which covers the electrode 5, and the 2nd electrode 6 which covers the 2nd insulating film 4 in this order. The semiconductor layer 43 includes a source 43s, a drain 43d, and a channel 43c disposed at a position facing the first electrode 3 between the source 43s and the drain 43d. The source 43s and the drain 43d are provided with an N-type low concentration impurity region 44 and an N-type high concentration impurity region 45 from the channel 43c side. The second electrode 6 covers the N-type low concentration impurity region 44 via the first insulating film 3, the second electrode 6 and the second insulating film 4, and the N-type TFT 22 has a so-called GOLD structure. In the N-type TFT 22, the first insulating film 3 functions as a gate insulating film, the first electrode 5 functions as a gate electrode, and the second electrode 6 functions as a second gate electrode.
A source electrode 8 and a drain electrode 9 are formed on the N-type TFT 22 via an interlayer insulating film 7. Further, a contact hole 10 penetrating the first insulating film 3, the second insulating film 4 and the interlayer insulating film 7 is formed above the N-type high concentration impurity region 45 of the source 43 s. The contact hole 10s is filled with a conductive material, and the source 43s and the source electrode 8 are connected. Similarly, a contact hole 10d penetrating the first insulating film 3, the second insulating film 4, and the interlayer insulating film 7 is formed above the N-type high concentration impurity region 45 of the drain 43d. The contact hole 10d is filled with a conductive material, and the drain 43d and the drain electrode 9 are connected.

Hereinafter, a method for manufacturing the semiconductor device of this embodiment will be described with reference to FIG. FIGS. 2-1 (a) to (g) and FIGS. 2-2 (h) to (k) are cross-sectional schematic views showing the manufacturing flow of the semiconductor device of this example.
First, as shown in FIG. 2-1 (a), after forming the underlayer 2 on the surface of the glass substrate 1, an amorphous silicon (a-Si) layer 11 was formed. As the underlayer 2, a SiO ₂ film, a SiNx film, or a SiNO film may be formed, or a laminate of these films may be formed. The method for forming the a-Si layer 11 is not particularly limited. For example, the a-Si layer 11 can be formed by a plasma CVD (Chemical Vapor Deposition) method using SiH ₄ , Si ₂ H ₆ or the like as a source gas.

Next, the a-Si layer 11 was crystallized to form a polysilicon (poly-Si) layer 12. The a-Si layer 11 can be crystallized using an excimer laser annealing method using an excimer laser, a solid phase growth method in which heat treatment is performed, or the like. Subsequently, as shown in FIG. 2-1 (b), a first photoresist film 13 was patterned on the poly-Si layer 12. Subsequently, as shown in FIG. 2C, the poly-Si layer 12 was patterned by dry etching using the first photoresist film 13 as a patterning mask. At this time, the poly-Si layer 12 was left only in the region to be the peripheral driver unit 20 and the pixel TFT 41, and was completely removed by etching in the region to be the capacitive element. The gas used for dry etching is not particularly limited, and examples thereof include a mixed gas of carbon tetrafluoride gas and oxygen gas, a mixed gas of sulfur hexafluoride gas and hydrogen chloride gas, and the like. As an etching method, a plasma etching (PE) mode, a reactive ion etching (RIE) mode, or the like can be used.

Next, after peeling off the first photoresist film 13, the first insulating film 3 and the first electrode layer 17 covering the poly-Si layer 12 were formed on the entire surface of the glass substrate 1 in this order. Examples of the first insulating film 3 include a SiO ₂ film, a SiNx film, a SiNO film, and the like, and a laminate of these films may be used. Examples of a method for forming the first insulating film 3 include atmospheric pressure CVD, LPCVD, plasma CVD, and remote plasma CVD. Each source gas used for film formation includes ethyl silicate (TEOS) for SiO ₂ film, mixed gas of monosilane (SiH ₄ ) and ammonia (NH ₃ ) for SiNx film, and monosilane (SiH for SiNO film). ₄ ), a mixed gas of nitrous oxide gas (N ₂ O) and nitrogen gas (N ₂ ), or the like can be used.
As the first electrode layer 17, for example, a compound containing aluminum (Al), tantalum (Ta), tungsten (W), molybdenum (Mo), or the like is used. Moreover, the 1st electrode layer 17 is good also as a laminated body which consists of said several material. Examples of a method for forming the first electrode layer 17 include a sputtering method.

Next, as shown in FIG. 2D, a second photoresist film 14 was formed in a pattern on the first electrode layer 17 in the region to be the first electrode 5. Subsequently, dry etching was performed using the second photoresist film 14 as a mask, and the first electrode layer 17 was patterned to form the first electrode 5. Subsequently, after the second photoresist film 14 is peeled off, as shown in FIG. 2E, the first electrode 5 is used as a mask to ionize phosphorus 30 as impurity ions at a low concentration in a self-aligning manner. Implantation was performed to form an N-type low-concentration impurity region 44 in the poly-Si layer 12. At this time, since impurity ions are not implanted below the first electrode 5 of the poly-Si layer 12, a channel 43c is formed.

Next, as shown in FIG. 2-1 (f), after patterning the third photoresist film 15, the third photoresist film 15 is used as a mask to form phosphorus ions that are impurity ions in a self-aligning manner. 30 was ion-implanted at a high concentration to form an N-type high concentration impurity region 44 in the poly-Si layer 12. Here, the third photoresist film 15 is formed on the N-type TFT 22 of the peripheral driver unit 20, the first electrode 5 of the pixel TFT 41, a part of the N-type low concentration impurity region 44 next to the channel 43 c, and the peripheral driver unit 20. It was formed on the P-type TFT 21 and the capacitor element 42. As a result, the N-type high concentration impurity region 45 is formed in the poly-Si layer 12 of the N-type TFT 22 and the pixel TFT 41.

Next, after the third photoresist film 15 is peeled off, the fourth photoresist film 16 is patterned in a region other than the P-type TFT 21 in the peripheral driver section 20 as shown in FIG. Then, using the first electrode 5 of the P-type TFT 21 as a mask, boron 31 which is an impurity ion is ion-implanted at a high concentration in a self-aligned manner, and the source 43 s formed of a P-type high-concentration impurity region in the poly-Si layer 12. And the drain 43d was formed. Here, the amount of boron 31 implanted is not particularly limited, but in order to give the TFT a P-type conductivity, more boron 31 was implanted than the previously implanted phosphorus 30.

Next, after the fourth photoresist film 16 is peeled off, the second insulating film 4 and the second electrode layer 18 covering the first electrode 5 are formed on the glass substrate 1 in this order as shown in FIG. Formed on the entire surface. The second insulating film 4 is preferably made of a material having a dielectric constant higher than that of the SiO ₂ film, such as a SiN film formed by a CVD method, an Al ₂ O ₃ film formed by a sputtering method, a Ta ₂ O ₅ film, or the like. Can be mentioned. Thereby, the capacity of the capacitive element 42 can be increased. Further, when an Al ₂ O ₃ film, a Ta ₂ O ₅ film, or the like is used as the second insulating film 4, it can be formed by oxidizing the first electrode 5, and the first electrode 5 is formed on the first electrode 5. 2 The insulating film 4 can be formed uniformly thin. Therefore, the capacity of the capacitive element 42 can be further increased. Examples of the oxidation method at this time include anodic oxidation, thermal oxidation, and plasma oxidation.
The second electrode layer 18 can be formed by the same material and film formation method as the first electrode layer 17. The film thickness of the second electrode layer 18 is preferably thinner than that of the first electrode 5.

Next, as shown in FIG. 2-2 (i), the second electrode layer 18 is patterned, and the second electrode 6 is formed on the N-type TFT 22 of the peripheral driver unit 20 and the second insulating film 4 of the capacitive element 42. Formed. Here, in the N-type TFT 22, the second electrode 6 is patterned at a position facing the first electrode 5 and the N-type low concentration impurity region 44. Thereafter, a contact hole (not shown) is formed in the second insulating film 4 of the N-type TFT 22, filled with a conductive material, and the first electrode 5 and the second electrode 6 are connected. Formed. In the capacitor element 42, the second electrode 6 was patterned so as not to protrude from the first electrode 5 when viewed from the normal direction of the glass substrate 1. Thereby, generation | occurrence | production of defects, such as a leakage current and a dielectric breakdown, in the edge part of the 1st electrode 5 which is a lower layer capacitive electrode can be suppressed effectively.

Next, as shown in FIG. 2-2 (j), after an interlayer insulating film 7 is formed on the entire surface, on the N-type high concentration impurity region 45 of the source 43s and drain 43d of the N-type TFT 22 and on the P-type TFT 21. Contact holes 10, 10 s and 10 d are formed on the source 43 s and the drain 43 d, on the source 43 s and drain 43 d of the pixel TFT 41 and on the second electrode 6 of the capacitive element 42, and FIG. As shown in FIG. 4A, the semiconductor device of this example was manufactured by filling each contact hole with a conductive material and forming the source electrode 8 and the drain electrode 9.

Thus, since the semiconductor device of this example has a GOLD structure in the N-type TFT 22 of the peripheral driver section 20, it was possible to realize an increase in current driving force and an improvement in carrier deterioration characteristics. Further, in the capacitor element 42, a high dielectric thin film can be employed for the second insulating film 4 that is a dielectric film, and further, a second electrode 6 that is an upper capacitive electrode and a first electrode 5 that is a lower capacitive electrode. Since there is no step in the laminated structure, it is possible to increase the capacity and size of the capacitive element 42 and to reduce defects such as dielectric breakdown and leakage current.

(Example 2)
The semiconductor device of this embodiment will be described with reference to FIG. FIG. 3 is a schematic cross-sectional view showing the configuration of the semiconductor device of this example. As shown in FIG. 3, the semiconductor device of this example is different from Example 1 only in the form of the second insulating film 4 and the gate structure of the N-type TFT 22, and therefore, description of other configurations is omitted below. To do.
In the present embodiment, the second insulating film 4 is formed only on the first electrodes 5 of the N-type TFT 22, the P-type TFT 21, the pixel TFT 41, and the capacitive element 42. Therefore, in the N-type TFT 22, the second electrode 6 disposed on the second insulating film 4 is also disposed on the side surface of the first electrode 5 and is electrically connected by being in contact with the first electrode 5. Yes.

Hereinafter, a method of manufacturing the semiconductor device of this example will be described with reference to FIG. FIGS. 4-1 (a) to (g) and FIGS. 4-2 (h) to (k) are cross-sectional schematic views showing the manufacturing flow of the semiconductor device of this example. Note that this example can be manufactured using the same materials and manufacturing method as those of Example 1.

First, as shown in FIG. 4A, after the underlayer 2 was formed on the surface of the glass substrate 1, an amorphous silicon (a-Si) layer 11 was formed. Subsequently, the a-Si layer 11 was crystallized to form a polysilicon (poly-Si) layer 12. Subsequently, as shown in FIG. 4B, a first photoresist film 13 was patterned on the poly-Si layer 12. Subsequently, as shown in FIG. 4C, the poly-Si layer 12 was patterned by performing dry etching using the first photoresist film 13 as a patterning mask. At this time, the poly-Si layer 12 was left only in the region to be the peripheral driver unit 20 and the pixel TFT 41, and was completely removed by etching in the region to be the capacitive element.

Next, after peeling off the first photoresist film 13, the first insulating film 3, the first electrode layer 17, and the second insulating film 4 covering the poly-Si layer 12 were formed on the entire surface of the glass substrate 1 in this order. . Subsequently, as shown in FIG. 4D, a second photoresist film 14 is formed in a pattern on the second insulating film 4 in the region to be the first electrode 5. Subsequently, dry etching is performed using the second photoresist film 14 as a mask, and the first electrode layer 17 and the second insulating film 4 are patterned to form the first electrode 5 having the second insulating film 4 on the upper surface. Formed. Subsequently, after peeling off the second photoresist film 14, as shown in FIG. 4E, the first electrode 5 and the second insulating film 4 are used as masks to form phosphorus ions that are impurity ions in a self-aligning manner. 30 was ion-implanted at a low concentration to form an N-type low-concentration impurity region 44 in the poly-Si layer 12. At this time, since impurity ions are not implanted below the first electrode 5 of the poly-Si layer 12, a channel 43c is formed.

Next, as shown in FIG. 4F, after the pattern formation of the third photoresist film 15 is performed, the third photoresist film 15 is used as a mask to form phosphorus ions that are impurity ions in a self-aligning manner. 30 was ion-implanted at a high concentration to form an N-type high-concentration impurity region 45 in the poly-Si layer 12. Here, the third photoresist film 15 is formed on the N-type TFT 22 of the peripheral driver unit 20, the first electrode 5 of the pixel TFT 41, a part of the N-type low concentration impurity region 44 next to the channel 43 c, and the peripheral driver unit 20. It was formed on the P-type TFT 21 and the capacitor element 42. The N-type high concentration impurity region 45 is formed in the poly-Si layer 12 of the N-type TFT 22 and the pixel TFT 41.

Next, after the third photoresist film 15 is peeled off, a pattern of the fourth photoresist film 16 is formed in a region other than the P-type TFT 21 of the peripheral driver section 20 as shown in FIG. After that, boron 31 as impurity ions is ion-implanted at a high concentration in a self-aligning manner using the first electrode 5 and the second insulating film 4 of the P-type TFT 21 as a mask, and P is implanted into the poly-Si layer 12 of the P-type TFT 21. A source 43s and a drain 43d made of a high concentration impurity region of the type were formed. Here, the amount of boron 31 implanted is not particularly limited, but in order to give the TFT a P-type conductivity, more boron 31 was implanted than the previously implanted phosphorus 30.

Next, after the fourth photoresist film 16 was peeled off, a second electrode layer 18 covering the first electrode 5 and the second insulating film 4 was formed as shown in FIG. Subsequently, as shown in FIG. 4-2 (i), the second electrode layer 18 is patterned, and the second insulating film 4 of the N-type TFT 22, the side surface of the first electrode 5, and the first of the capacitive element 42. The second electrode 6 was formed on the two insulating film 4. Here, in the N-type TFT 22, the second electrode 6 is patterned at a position facing the first electrode 5 and the N-type low concentration impurity region 44. In the capacitor element 42, the second electrode 6 was patterned so as not to protrude from the first electrode 5 when viewed from the normal direction of the glass substrate 1. Then, as shown in FIG. 5-2 (j), after forming the interlayer insulating film 7 and the contact holes 10, 10s and 10d as in the first embodiment, as shown in FIG. 5-2 (k). By forming the source electrode 8 and the drain electrode 9, the semiconductor device of this example was manufactured.

As described above, in this embodiment, since the first electrode 5 and the second electrode 6 constituting the GOLD structure of the N-type TFT 22 are brought into electrical contact with each other, an extra contact hole forming region is required. The N-type TFT 22 could be made smaller.

(Example 3)
Since the semiconductor device of the present embodiment has the same configuration as the semiconductor device of the first embodiment and only the manufacturing method is different, only the manufacturing method will be described below. FIGS. 5-1 (a) to (g) and FIGS. 5-2 (h) to (k) are cross-sectional schematic views showing the manufacturing flow of the semiconductor device of this example. Note that this example can be manufactured using the same materials and manufacturing method as those of Example 1.

First, as shown in FIG. 5A, after the underlayer 2 was formed on the surface of the glass substrate 1, an amorphous silicon (a-Si) layer 11 was formed. Subsequently, the a-Si layer 11 was crystallized to form a polysilicon (poly-Si) layer 12. Subsequently, as shown in FIG. 5B, a first photoresist film 13 was patterned on the poly-Si layer 12. Subsequently, as shown in FIG. 5C, the poly-Si layer 12 was patterned by dry etching using the first photoresist film 13 as a patterning mask. At this time, the poly-Si layer 12 was left only in the region to be the peripheral driver unit 20 and the pixel TFT 41, and was completely removed by etching in the region to be the capacitive element.

Next, after peeling off the first photoresist film 13, the first insulating film 3 and the first electrode layer 17 covering the poly-Si layer 12 were formed on the entire surface of the glass substrate 1 in this order. Subsequently, as shown in FIG. 5D, the second photoresist film 14 was formed in a pattern on the first electrode layer 17 in the region to be the first electrode 5. Subsequently, dry etching was performed using the second photoresist film 14 as a mask, and the first electrode layer 17 was patterned to form the first electrode 5. Subsequently, after the second photoresist film 14 is peeled off, phosphorus 30 as impurity ions is ionized at a low concentration in a self-aligning manner using the first electrode 5 as a mask as shown in FIG. Implantation was performed to form an N-type low-concentration impurity region 44 in the poly-Si layer 12. At this time, since impurity ions are not implanted below the first electrode 5 of the poly-Si layer 12, a channel 43c is formed.

Next, as shown in FIG. 5A, after patterning the third photoresist film 15 in a region other than the P-type TFT 21 of the peripheral driver unit 20, the first electrode 5 of the P-type TFT 21 is formed. As a mask, boron 31 as impurity ions is ion-implanted in a high concentration in a self-aligned manner, and a source 43 s and a drain 43 d made of a P-type high concentration impurity region are formed in the poly-Si layer 12.

Next, after the third photoresist film 15 is peeled off, the second insulating film 4 and the second electrode layer 18 covering the first electrode 5 are formed on the entire surface of the glass substrate 1 as shown in FIG. Formed. Subsequently, as shown in FIG. 5-2 (h), the second electrode layer 18 is patterned, and the second electrode layer 18 is patterned on the second insulating film 4 of the N-type TFT 22 and on the second insulating film 4 of the capacitive element 42. Two electrodes 6 were formed. Here, in the N-type TFT 22, the second electrode 6 is formed so as to cover a part of the N-type low concentration impurity region 44 on the channel 43 c side. In the capacitor element 42, the second electrode 6 was patterned so as not to protrude from the first electrode 5 when viewed from the normal direction of the glass substrate 1.

Next, after the pattern formation of the fourth photoresist film 15 is performed, as shown in FIG. 5-2 (i), the fourth photoresist film 16 and the second electrode 6 of the N-type TFT 22 are used as a mask. Phosphorus 30 as impurity ions is ion-implanted at a high concentration in a self-aligned manner, and an N-type high-concentration impurity region 45 is formed in the poly-Si layer 12. Here, the fourth photoresist film 15 is formed on the P-type TFT 21 of the peripheral driver unit 20, on the first electrode 5 of the pixel TFT 41 and a part of the N-type low concentration impurity region 44 on the channel 43 c side, and the capacitive element. 42 on top. As a result, the N-type high concentration impurity region 45 is formed in the poly-Si layer 12 of the N-type TFT 22 and the pixel TFT 41. Thereafter, a contact hole (not shown) is formed in the second insulating film 4 of the N-type TFT 22, filled with a conductive material, and the first electrode 5 and the second electrode 6 are connected. Formed.

Then, as shown in FIG. 5-2 (j), after forming the interlayer insulating film 7 and the contact holes 10, 10s and 10d as in the first embodiment, as shown in FIG. 5-2 (k). By forming the source electrode 8 and the drain electrode 9, the semiconductor device of this example was manufactured. As described above, in this embodiment, the GOLD structure is formed in a self-aligning manner using the second electrode 6 as a mask, so that an N-type TFT 22 having no extra load capacitance and load resistance can be formed. It was.

Example 4
An active matrix substrate using the semiconductor device of the present invention will be described with reference to FIG. 6A and 6B are a schematic top view and a schematic cross-sectional view showing the configuration of the active matrix substrate of this example.
As shown in FIG. 6A, in the active matrix substrate of this embodiment, a gate wiring 32, a capacitor wiring 34, and a source wiring 33 are provided on a glass substrate 1 through an interlayer insulating film (not shown). They are arranged in a matrix so as to be orthogonal to each other. In the vicinity of the intersection of the gate line 32 and the source line 33, a pixel TFT 41 having a semiconductor layer 43 is disposed. A part of the capacitive wiring 34 is used as the first electrode 5 which is a lower capacitive electrode of the capacitive element 42, and the second electrode 6 does not protrude from the capacitive wiring 34 via a second insulating film (not shown) thereon. Are arranged as follows. The source wiring 33 is connected to the source (not shown) of the pixel TFT 41 through the contact hole 10s. On the drain (not shown) of the pixel TFT 41, the drain electrode 9 is disposed through a contact hole 10d provided in the interlayer insulating film. The drain electrode 9 is also connected to the second electrode 6 of the capacitive element through the contact hole 10. The drain electrode 9 is further connected to a pixel electrode (not shown) disposed on an insulating film (not shown) via a contact hole 10 ′.
As described above, since the capacitive element of this embodiment has the second insulating film as the dielectric film separately from the first insulating film that is the gate electrode of the TFT, an insulating film having characteristics suitable for the capacitive element is used. be able to. As a result, the capacitance element can be increased in capacity and size, and an active matrix substrate having an excellent aperture ratio can be manufactured.

Next, the active matrix substrate of this embodiment will be further described with reference to FIG. FIG. 6B is a schematic cross-sectional view when the active matrix substrate shown in FIG. 6A is cut along line AA ′. The active matrix substrate of this embodiment has a configuration in which an insulating film 35 and a pixel electrode 36 are newly provided in this order on the semiconductor device of Embodiment 1. The pixel electrode 36 is connected to the drain electrode 9 that connects the pixel TFT 41 and the capacitive element 42 via a contact hole 10 ′.
Thus, in the capacitive element of the present invention, the second electrode 6 that is the upper-layer capacitive electrode is disposed inside the first electrode 5 that is the lower-layer capacitive electrode. It was possible to effectively suppress the occurrence of defects and interelectrode leakage current.

(Comparative Example 1)
The active matrix substrate of Comparative Example 1 will be described with reference to FIG. 7A and 7B are a schematic top view and a schematic cross-sectional view showing the configuration of the active matrix substrate of this comparative example.
As shown in FIG. 7A, the active matrix substrate of this comparative example is the same as that of Example 3 except for the form of the capacitive element 42, and hence the description thereof is omitted below. In this comparative example, a part of the capacitive wiring 34 is used as an upper capacitive electrode of the capacitive element 42, and a lower capacitive electrode composed of the semiconductor layer 43 of the pixel TFT 41 is disposed thereunder via a first insulating film (not shown). Is arranged. Thus, since the dielectric film of the capacitive element 42 is made of the first insulating film that is also the gate insulating film of the pixel TFT 41, the thinning and the adoption of a high dielectric constant film are limited. Therefore, the capacitance per unit area of the dielectric film is small and the capacitance element is large. As a result, the active matrix substrate of this comparative example has a small aperture ratio and lacks fineness. Met.

Next, the active matrix substrate of this embodiment will be further described with reference to FIG. FIG. 7B is a schematic cross-sectional view when the active matrix substrate shown in FIG. 7A is cut along a line segment BB ′. In this comparative example, the configuration of the capacitor 42, the semiconductor layer 43 of the pixel TFT 41, and the drain electrode 9 is the same as that of the fourth embodiment except that the second insulating film is not formed. Is omitted. In the active matrix substrate of this embodiment, the semiconductor layer 43 of the pixel TFT 41 is arranged to extend below the capacitor wiring 34 via the first insulating film 3. Further, the drain electrode 9 is not connected to the capacitor element 42 and is connected only to the pixel electrode 36.
As described above, the capacitive element 42 includes the semiconductor layer 43, the first insulating film 3, and the capacitive wiring 34. Accordingly, since there is a step at the end of the semiconductor layer 43, the coverage of the first insulating film 3 there deteriorates. Further, when the semiconductor layer 43 is made of crystallized silicon crystallized with a laser, many ridges are formed on the surface. For these reasons, the active matrix substrate of this comparative example is prone to defects such as dielectric breakdown and leakage current in the capacitive element 42.

1 is a schematic cross-sectional view showing a configuration of a semiconductor device of Example 1. FIG. FIG. 4 is a schematic cross-sectional view showing a manufacturing flow of the semiconductor device of Example 1, wherein (a) shows a state after the formation of the a-Si layer, and (b) shows a state after the formation of the first photoresist film. (C) shows the state after patterning of the poly-Si layer, (d) shows the state after the formation of the second photoresist film, and (e) shows the state after the low-concentration phosphorus ion implantation. (F) shows the state after high concentration phosphorus ion implantation, and (g) shows the state after high concentration boron ion implantation. It is a cross-sectional schematic diagram which shows the manufacturing flow of the semiconductor device of Example 1, (h) shows the state after formation of the second insulating film and the second electrode layer, and (i) shows the state after formation of the second electrode. (J) shows the state after the interlayer insulating film and contact hole are formed, and (k) shows the state after the source electrode and drain electrode are formed. 6 is a schematic cross-sectional view showing a configuration of a semiconductor device of Example 2. FIG. FIG. 6 is a schematic cross-sectional view showing a manufacturing flow of the semiconductor device of Example 2, wherein (a) shows the state after the formation of the a-Si layer, and (b) shows the state after the formation of the first photoresist film. (C) shows the state after patterning of the poly-Si layer, (d) shows the state after the formation of the second photoresist film, and (e) shows the state after the low-concentration phosphorus ion implantation. (F) shows the state after high concentration phosphorus ion implantation, and (g) shows the state after high concentration boron ion implantation. FIG. 9 is a schematic cross-sectional view showing a manufacturing flow of the semiconductor device of Example 2, wherein (h) shows a state after forming the second electrode layer, (i) shows a state after forming the second electrode, and (j ) Shows a state after the formation of the interlayer insulating film and the contact hole, and (k) shows a state after the formation of the source electrode and the drain electrode. It is a cross-sectional schematic diagram which shows the manufacturing flow of the semiconductor device of Example 3, (a) shows the state after a-Si layer formation, (b) shows the state after 1st photoresist film formation. (C) shows the state after patterning of the poly-Si layer, (d) shows the state after the formation of the second photoresist film, and (e) shows the state after the low-concentration phosphorus ion implantation. (F) shows the state after high concentration boron ion implantation, and (g) shows the state after forming the second insulating film and the second electrode layer. It is a cross-sectional schematic diagram which shows the manufacture flow of the semiconductor device of Example 3, (h) shows the state after 2nd electrode formation, (i) shows the state after high concentration phosphorus ion implantation, (j) Indicates the state after the formation of the interlayer insulating film and contact holes, and (k) indicates the state after the formation of the source electrode and the drain electrode. (A) is an upper surface schematic diagram which shows the structure of the semiconductor device of Example 4, (b) is the cross-sectional schematic diagram. (A) is an upper surface schematic diagram which shows the structure of the semiconductor device of the comparative example 1, (b) is the cross-sectional schematic diagram.

Explanation of symbols

1: glass substrate 2: underlying layer 3: first insulating film 4: second insulating film 5: first electrode 6: second electrode 7: interlayer insulating film 8: source electrode 9: drain electrodes 10, 10 ′, 10s, 10d: contact hole 11: amorphous silicon (a-Si) layer 12: polysilicon (poly-Si) layer 13: first photoresist film 14: second photoresist film 15: third photoresist film 16: Fourth photoresist film 17: first electrode layer 18: second electrode layer 20: peripheral driver portion 21: P-type TFT
22: N-type TFT
30: phosphorus 31: boron 32: gate wiring 33: source wiring 34: capacitance wiring 35: insulating film 36: pixel electrode 40: pixel portion 41: pixel TFT
42: Capacitance element 43: Semiconductor layer 43s: Source 43d: Drain 43c: Channel 44: N-type low concentration impurity region 45: N-type high concentration impurity region

Claims (17)

A semiconductor device including a thin film transistor and a capacitor over an insulating substrate,
The thin film transistor includes a semiconductor layer having a channel and a source and a drain disposed beside the channel, a first insulating film disposed on the channel, and a first layer disposed at a position facing the channel on the first insulating film. Having an electrode,
The capacitive element has a first electrode, a second insulating film, and a second electrode arranged in this order from the insulating substrate side, and the outer edge of the second electrode is located on the inner side or on the outer edge of the outer edge of the first electrode. A featured semiconductor device. At least one of the thin film transistors has a structure in which a low-concentration impurity region and a high-concentration impurity region are provided in order from the channel side in at least a drain, and further, a second insulating film and a second electrode are formed on the first electrode. In this order,
2. The semiconductor device according to claim 1, wherein the second electrode is electrically connected to the first electrode and is disposed so as to cover at least the low-concentration impurity region. 2. The semiconductor device according to claim 1, wherein an electrode connected to a potential different from that of the first electrode of the capacitor element is provided in a region other than a lower portion of the first electrode of the capacitor element. The semiconductor device according to claim 1, wherein a semiconductor layer is provided in a region other than a lower portion of the first electrode of the capacitor element. The semiconductor device according to claim 1, further comprising a capacitor wiring formed of substantially the same material as the first electrode. 2. The semiconductor device according to claim 1, wherein the second insulating film has a larger capacity per unit area than the first insulating film. The semiconductor device according to claim 1, wherein the second insulating film is formed of a material having a dielectric constant larger than that of the material of the first insulating film. The semiconductor device according to claim 1, wherein the second insulating film has a film configuration different from that of the first insulating film. The semiconductor device according to claim 1, wherein the second insulating film is made of an oxide of a first electrode material. The semiconductor device according to claim 1, wherein the second electrode is thinner than the first electrode. A method of manufacturing a semiconductor device according to claim 2,
The method of manufacturing a semiconductor device is characterized in that the second insulating film is formed after patterning the first electrode. A method of manufacturing a semiconductor device according to claim 2,
The manufacturing method is characterized in that the second electrode is formed after patterning the first electrode and the second insulating film with the same mask. A method of manufacturing a semiconductor device according to claim 2,
The manufacturing method includes a step of doping a low concentration impurity using the first electrode as a mask;
And a step of doping a high concentration impurity using the second electrode as a mask. A power supply circuit comprising the semiconductor device according to claim 1. An active matrix substrate comprising the semiconductor device according to claim 1. A display device comprising the active matrix substrate according to claim 15. The display device according to claim 16, wherein the display device is a liquid crystal display device.

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