JP4293412B2 - Method for producing crystalline silicon film - Google Patents

Description

【００４６】
そこで、従来の結晶化法により得られたシリコンを主成分とする結晶質半導体膜（サンプル１）、本発明の結晶化方法により得られたシリコンを主成分とする結晶質半導体膜であって結晶化の際に３ｐｐｍのＮｉ溶液を添加して得られた結晶質半導体膜（サンプル２）、本発明の結晶化方法により得られたシリコンを主成分とする結晶質半導体膜であって結晶化の際に３０ｐｐｍのＮｉ溶液を添加して得られた結晶質半導体膜（サンプル３）をそれぞれＥＢＳＰ法により測定し、式１により求めた各サンプルを構成する特定の指数（｛１００｝、｛１１０｝、｛１１１｝）における配向率（％）を表１に示す。
【００４７】
【表１】

【００４８】
表１において、本発明の結晶化方法を用いて得られた結晶質半導体膜のうち３ｐｐｍのＮｉ溶液を添加して得られた結晶質半導体膜（サンプル２）は、｛１１１｝面における配向率が７４．４％であった。このことは、反射電子回折パターン法で検出される｛１１１｝格子面の前記結晶質半導体膜の表面となす角が、５°以内である割合が７４．４％であることを示している。また、このように高い配向率を示したサンプル２についての逆極点マップを図１６に示す。
【００４９】
なお、このように非常に高い配向率（具体的には６０％以上）が得られることにより、複数の結晶集合において、その配向が異なることにより生じる境界や、結晶集合のサイズの違いにより生じていたＴＦＴ特性に対する影響を低減させ、ＴＦＴ間のバラツキを低減させることが可能となる。
【００５０】
例えば、画素部に配置されるＴＦＴに電気特性のバラツキがあれば、各画素電極に印加する電圧のバラツキが生じ、そのため透過光量のバラツキも生じ、これが表示むらとなって観察者の目に映ることになる。現在の時点では、このバラツキは許容範囲内であり、問題ない程度であるが、今後、画素サイズの微細化がさらに進み、より高精細な画像が求められた場合、このバラツキが非常に重大な問題になってくると考えられる。さらに配線幅の微小化するとともにチャネル形成領域のサイズ（チャネル長、チャネル幅）が微小化するため、どうしても集合と集合との境界をチャネル形成領域に有するＴＦＴも形成され、そのＴＦＴ特性（移動度、Ｓ値、オン電流値、オフ電流値等）は境界のないチャネル形成領域を有するＴＦＴと比べて差が生じ、それが表示のバラツキを招くと考えられることから、本発明の作製方法を用いて作製された結晶質半導体膜を用いてＴＦＴを作製することは非常に有効である。
【００５１】
【実施例】
以下に、本発明の実施例について説明する。
【００５２】
（実施例１）
本実施例では石英基板（厚さ１．１ｍｍ）を用い、本発明を用いて結晶化された結晶質半導体膜を用いてＴＦＴを作製する方法について図３を用いて説明する。
【００５３】
なお、結晶質半導体膜の作製方法については、発明の実施の形態を参照すればよい。はじめに、本実施例では、結晶質半導体膜（発明の実施の形態で得られた第３の結晶質半導体膜１１０）上に新たに絶縁膜（酸化珪素膜）を形成し、熱処理を行うことにより結晶質半導体膜の上部を熱酸化させる。このような熱処理を行うことにより結晶内部の粒内欠陥を減少させることができるので、結晶質半導体膜の結晶性を向上させることができる。そして、絶縁膜および結晶質半導体膜の酸化した部分をエッチングすると共にパターニングを行い半導体層２０１を形成する。
【００５４】
次に、半導体層２０１の表面をフッ酸を含むエッチャントで洗浄した後、ゲート絶縁膜２０２となる珪素を主成分とする絶縁膜を形成する。この表面洗浄とゲート絶縁膜の形成は、大気にふれさせずに連続的に行うことが望ましい（図３（Ａ））。
【００５５】
次に、ゲート絶縁膜２０２表面を洗浄した後、ゲート電極２０３を形成し（図３（Ｂ））、半導体にｎ型を付与する不純物元素（Ｐ、Ａｓ等）、ここではリンを適宜添加して、ソース領域２０４およびドレイン領域２０５を形成する（図３（Ｃ））。そして、不純物元素を添加した後、不純物元素を活性化するために加熱処理、強光の照射、またはレーザー光の照射を行う。このような処理を行うことにより、活性化と同時にゲート絶縁膜２０２へのプラズマダメージやゲート絶縁膜２０２と半導体層２０１との界面へのプラズマダメージを回復することができる。特に、室温〜３００℃の雰囲気中において、表面または裏面からＹＡＧレーザーの第２高調波を照射して不純物元素を活性化させることは非常に有効である。ＹＡＧレーザーはメンテナンスが少ないため好ましい活性化手段である。
【００５６】
次に、層間絶縁膜２０６を形成し、水素化を行って、ソース領域、ドレイン領域に達するコンタクトホールを形成し、ソース電極２０７、ドレイン電極２０８を形成してＴＦＴを完成させる（図３（Ｄ）（Ｅ））。
【００５７】
こうして得られたＴＦＴは、チャネル形成領域２０９を形成する結晶質半導体膜の結晶粒径が大きく、また結晶の配向率も非常に高いことから、膜中の均一性が高く、基板上に形成されたＴＦＴ間のバラツキが小さい。
【００５８】
なお、本発明は図３（Ｄ）の構造に限定されず、必要があればチャネル形成領域とドレイン領域（またはソース領域）との間にＬＤＤ領域を有する低濃度ドレイン（ＬＤＤ：Lightly Doped Drain）構造としてもよい。この構造はチャネル形成領域と、高濃度に不純物元素を添加して形成するソース領域またはドレイン領域との間に低濃度に不純物元素を添加した領域を設けたものであり、この領域をＬＤＤ領域と呼んでいる。さらにゲート絶縁膜を介してＬＤＤ領域をゲート電極と重ねて配置させた、いわゆるＧＯＬＤ（Gate-drain Overlapped LDD）構造としてもよい。
【００５９】
また、ここではｎチャネル型ＴＦＴを用いて説明したが、ｎ型不純物元素に代えてｐ型不純物元素を用いることによってｐチャネル型ＴＦＴを形成することもできる。
【００６０】
（実施例２）
本実施例では、実施の形態および実施例１と異なる方法を用いて非晶質半導体膜を結晶化する方法について図４を用いて説明する。
【００６１】
図４（Ａ）において、３００は、絶縁表面を有する基板であり、本実施例では、ガラス基板を用いる。また、３０１は下地絶縁膜であり、３０２は非晶質構造を有する第１の非晶質半導体膜である。さらに、第１の非晶質半導体膜３０２上には島状の絶縁膜３０３が形成されている。
【００６２】
まず、基板３００上にブロッキング層として酸化シリコン膜、窒化シリコン膜または酸化窒化シリコン膜などの絶縁膜からなる下地絶縁膜３０１を形成する。ここでは下地絶縁膜３０１として２層構造（膜厚５０ｎｍの酸化窒化シリコン膜、膜厚１００ｎｍの酸化窒化シリコン膜）を用いるが、単層膜または２層以上積層させた構造を用いても良い。ただし、ブロッキング層を設ける必要がない場合には下地絶縁膜を形成しなくともよい。
【００６３】
次いで、ＬＰＣＶＤ法を用いて、下地絶縁膜上に非晶質構造を有する第１の非晶質半導体膜３０２を形成する。なお、ここで形成される膜中酸素濃度の低い非晶質半導体膜は、膜中の酸素濃度が１×１０¹⁸ａｔｏｍｓ／ｃｍ³未満である非晶質半導体膜である。また、非晶質半導体膜の材料としては珪素（シリコン）または、珪素ゲルマニウム（ＳｉＧｅ）合金などで形成することができる。
【００６４】
次に、膜中酸素濃度の低い非晶質半導体膜の一部を覆って、絶縁膜を形成する。なお、ここで形成される絶縁膜としては、酸化珪素膜、窒化珪素膜、または酸化窒化珪素膜といった珪素を含む絶縁膜を用いることができる。また、成膜後にフォトリソグラフィーによるパターニングを行い、エッチングすることにより膜中酸素濃度の低い非晶質半導体膜の一部を覆う島状の絶縁膜３０３が形成される。
【００６５】
なお、この状態で水素、窒素、アンモニアおよび希ガス元素から選ばれた一種または複数種を主成分とする気体をプラズマ化させた雰囲気に曝すことで、膜中酸素濃度の低い第１の非晶質半導体膜３０２の表面に形成された自然酸化膜を除去してもよい。
【００６６】
次に、プラズマＣＶＤ法により膜中酸素濃度の高い非晶質半導体膜（第２の非晶質半導体膜）３０４を膜中酸素濃度の低い第１の非晶質半導体膜３０２の一部、および絶縁膜３０３上に形成し、膜中酸素濃度の高い第２の非晶質半導体膜３０４上に結晶化を助長する金属元素３０５を添加する。なお、本実施例では重量換算で１０ｐｐｍのニッケルを含む酢酸ニッケル塩溶液をスピナーで塗布することにより金属元素３０５を添加する（図４（Ｂ））。
【００６７】
次いで、これらを加熱処理することにより結晶化させて結晶構造を有する結晶質半導体膜を形成する。この加熱処理は、電気炉の熱処理または強光の照射を用いればよい。電気炉の熱処理で行う場合は、５００℃〜６５０℃で４〜２４時間処理を行えばよい。なお、本実施例では、結晶化のための熱処理（５５０℃、４時間）を行うことにより非晶質半導体膜（第１の非晶質半導体膜３０２、第２の非晶質半導体膜３０５）の結晶化を行う。
【００６８】
なお、結晶化を助長する金属元素３０５の添加方法としては、金属元素を含む溶液を塗布する方法でも良いし、スパッタ法やＣＶＤ法で薄い膜を形成する方法でも良い。すなわち、結晶化により、第１の非晶質半導体膜３０２は、第１の結晶質半導体膜３０７となり、第２の非晶質半導体膜３０５は、第２の結晶質半導体膜３０８となる（図４（Ｃ））。
【００６９】
次に第１の結晶質半導体膜３０７に存在する金属元素を除去するために不純物を添加してゲッタリングを行う。具体的には、第２の結晶質半導体膜３０８上にリンまたは希ガス（代表的にはアルゴン）を添加する。なお、この時、絶縁膜３０３をマスクとして第１の結晶質半導体膜３０７の一部である領域ｒ（３０９）にもリンまたは希ガス（代表的にはアルゴン）が１×１０¹⁶〜５×１０¹⁷ａｔｏｍｓ/ｃｍ³程度の濃度で添加される。ここで、熱処理を行うことにより第１の結晶質半導体膜３０７中に存在する金属元素（代表的にはＮｉ）３０５が領域ｒ（３０９）に移動するため第１の結晶質半導体膜３０７中に存在する金属元素を除去することができる。
【００７０】
次に、絶縁膜３０３で覆われた部分の第１の結晶質半導体膜３０７を残し、結晶化された結晶質半導体膜をエッチングして除去する。さらに、絶縁膜３０３を除去することにより金属元素を含まない結晶質半導体膜を得ることができる（図４（Ｄ））。
【００７１】
さらに本実施例では、得られた結晶質半導体膜の表面に存在する酸化膜を希フッ酸等で除去した後、結晶化率を高め、結晶粒内に残される欠陥を補修するためのレーザー光（ＸｅＣｌ：波長３０８ｎｍ）の照射を大気中、または酸素雰囲気中で行う。なお、ここで用いるレーザーとしては、連続発振またはパルス発振の固体レーザーまたは気体レーザーまたは金属レーザーが望ましい。なお、前記固体レーザーとしては、連続発振またはパルス発振のＹＡＧレーザー、ＹＶＯ₄レーザー、ＹＬＦレーザー、ＹＡｌＯ₃レーザー、ガラスレーザー、ルビーレーザー、アレキサンドライドレーザー、Ｔｉ：サファイアレーザー等があり、前記気体レーザーとしては、連続発振または、パルス発振のエキシマレーザー、Ａｒレーザー、Ｋｒレーザー、ＣＯ₂レーザー等があり、前記金属レーザーとしては、連続発振またはパルス発振のヘリウムカドミウムレーザー、銅蒸気レーザー、金蒸気レーザーが挙げられる。また、レーザー光を非線形光学素子によって第２高調波、第３高調波に変換して用いてもよい。なお、パルス発振のレーザーを用いる場合には、繰り返し周波数１０Hz〜１０KHz程度のパルスレーザー光を用い、当該レーザー光を光学系にて１００〜１５００ｍＪ／ｃｍ²に集光し、５０〜９８％のオーバーラップ率をもって照射し、シリコン膜表面を走査させればよい。ここでは、繰り返し周波数３０Ｈｚ、エネルギー密度３９３ｍＪ／ｃｍ²でレーザー光の照射を大気中で行う。
【００７２】
また、連続発振のレーザーを用いる場合には、エネルギー密度は０．０１〜１００ＭＷ／ｃｍ²程度（好ましくは、０．１〜１０ＭＷ／ｃｍ²）が必要である。そして、０．５〜２０００ｃｍ／ｓ程度の速度でレーザー光に対して相対的にステージを動かして照射すればよい。
【００７３】
以上により、結晶化率の高い第３の結晶質半導体膜３１０を得ることができる。
【００７４】
次に、第３の結晶質半導体膜３１０をパターニングすることにより半導体層３１１を形成する。
【００７５】
次いで、半導体層３１１の表面をフッ酸を含むエッチャントで洗浄した後、ゲート絶縁膜３１２となる珪素を主成分とする絶縁膜を形成する。この表面洗浄とゲート絶縁膜３１２の形成は、大気にふれさせずに連続的に行うことが望ましい。
【００７６】
次いで、ゲート絶縁膜３１２の表面を洗浄した後、ゲート電極３１３を形成し、半導体にｎ型を付与する不純物元素（Ｐ、Ａｓ等）、ここではリンを適宜添加して、ソース領域３１４及びドレイン領域３１５を形成する。添加した後、不純物元素を活性化するために加熱処理、強光の照射、またはレーザー光の照射を行う。また、活性化と同時にゲート絶縁膜へのプラズマダメージやゲート絶縁膜と半導体層との界面へのプラズマダメージを回復することができる。特に、室温〜３００℃の雰囲気中において、表面または裏面からＹＡＧレーザーの第２高調波を照射して不純物元素を活性化させることは非常に有効である。ＹＡＧレーザーはメンテナンスが少ないため好ましい活性化手段である。
【００７７】
また、活性化の手段として熱処理とした場合、活性化と同時にゲッタリングを行うことができる。ここでのゲッタリングはソース領域またはドレイン領域に添加したリンによるゲッタリングである。また、結晶化の前に添加した結晶成長を助長させる金属元素は、結晶化後にゲッタリングを行い結晶質半導体膜中から除去または低減することが望ましい。
【００７８】
以降の工程は、層間絶縁膜３１６を形成し、水素化を行って、ソース領域、ドレイン領域に達するコンタクトホールを形成し、ソース電極３１７、ドレイン電極３１８を形成してＴＦＴを完成させる（図４（Ｆ））。
【００７９】
こうして得られたＴＦＴは、粒径が大きく、かつ高配向率を有する第３の結晶質半導体膜３１０を用いてチャネル形成領域３１７を形成していることから、均一性が高く、基板上に形成されたＴＦＴ間のバラツキを小さくすることができる。
【００８０】
（実施例３）
ここでは、画素部を有するアクティブマトリクス基板を用いた液晶表示装置を作製する方法について図５〜図１０を用いて説明する。
【００８１】
ＴＦＴをスイッチング素子として用いるアクティブマトリクス型液晶表示装置は、画素電極がマトリクス状に配置された基板（アクティブマトリクス基板）と、対向電極が形成された対向基板とを液晶層を介して対向配置した構造となっている。両基板間はスペーサ等を介して所定の間隔に制御され、画素部の外周部にシール材を用いることで液晶層を封入している。
【００８２】
以下にアクティブマトリクス基板の作製例を示す。
【００８３】
まず、絶縁表面を有する基板４０１上に導電膜を形成し、パターニングを施すことにより走査線４０２を形成する。この走査線４０２は後に形成される活性層を光から保護する遮光層としても機能する。ここでは基板４０１として石英基板を用い、走査線４０２としてポリシリコン膜（膜厚７５ｎｍ）とタングステンシリサイド（Ｗ−Ｓｉ）膜（膜厚１５０ｎｍ）の積層構造を用いる。また、ポリシリコン膜はタングステンシリサイドから基板への汚染を保護するものである。
【００８４】
次に、走査線４０２を覆う絶縁膜４０３ａ、４０３ｂを膜厚１００〜１０００ｎｍ（代表的には３００〜６００ｎｍ）で形成する（図５（Ａ））。ここではプラズマＣＶＤ法を用いた膜厚１００ｎｍの酸化シリコン膜と減圧ＣＶＤ法（ＬＰＣＶＤ法）を用いた膜厚４８０ｎｍの酸化シリコン膜を積層することにより形成する。
【００８５】
また、絶縁膜４０３ｂを形成した後、絶縁膜表面を化学的及び機械的に研磨する処理（代表的にはＣＭＰ技術）等）により平坦化してもよい。例えば、絶縁膜表面の最大高さ（Ｒmax）が０．５μｍ以下、好ましくは０．３μｍ以下となるようにする。
【００８６】
次に、非晶質半導体膜を膜厚１０〜１００ｎｍで形成する。なお、ここで形成される非晶質半導体膜（アモルファスシリコン膜）は、ＬＰＣＶＤ法により形成され、本実施例においては、第１の非晶質半導体膜と呼ぶことにする。また、第１の非晶質半導体膜４０４は膜厚５３ｎｍとして形成する。なお、半導体膜の材料としては珪素または、珪素ゲルマニウム（ＳｉＧｅ）合金などで形成することができる。
【００８７】
さらに、第１の非晶質半導体膜４０４を覆って絶縁膜４０５を形成する。本実施例では、膜厚５０ｎｍの酸化珪素膜を形成し、パターニングを行って所望の形状の絶縁膜４０５を形成する（図５（Ｂ））。なお、絶縁膜４０５を形成した後の画素上面図を図５（Ｂ２）に示す。図５（Ｂ２）において、点線Ａ−Ａ’で切断した断面図が図５（Ｂ１）に相当する。
【００８８】
次に、第１の非晶質半導体膜４０４の露出部分と絶縁膜４０５を覆って第２の非晶質半導体膜４０６を形成する。そして、第１の非晶質半導体膜４０４と第２の非晶質半導体膜４０６を結晶化する。本実施例では、非晶質シリコン膜に対して結晶化を助長する金属元素を全面に添加し、熱結晶化法により非晶質半導体膜を結晶化する。
【００８９】
なお、金属元素としては、Ｎｉ、Ｐｄまたは鉛等の金属元素があり、添加の方法は、プラズマ処理法や、蒸着法、イオン注入法、スパッタ法、溶液塗布法等を用いることができる本実施例では、酢酸ニッケル水溶液を（重量換算濃度３ｐｐｍ、体積１０ｍｌ）第２の非晶質半導体膜４０６表面にスピンコート法にて塗布する。
【００９０】
そして、熱処理を行って非晶質半導体膜の結晶化を行う。この熱処理はファーネスアニール炉を用いる熱アニール法で行う。熱アニール法としては、酸素濃度が１ｐｐｍ以下、好ましくは０．１ｐｐｍ以下の窒素雰囲気中で４００〜７００℃、代表的には５００〜６００℃で、４〜２４時間程度行えばよい。また、熱アニール法の他の熱処理としてラピッドサーマルアニール法（ＲＴＡ法）やＧＲＴＡ法等を用いてもよい。本実施例では、熱処理（５７０℃、２４時間）を行い、結晶質珪素膜を形成する。
【００９１】
なお、本実施例においては、第２の非晶質半導体膜４０６上に結晶化を助長する金属元素が添加され加熱による結晶化を行っているが、第２の非晶質半導体膜４０６と第１の非晶質半導体膜４０４は、図５（Ｃ）の領域ａ（４０７）において、接して形成されているので、結晶化の際に第１の非晶質半導体膜４０４も結晶化されるため、第１の非晶質半導体膜４０４は、第１の結晶質半導体膜４０８となり、第２の非晶質半導体膜４０６は第２の結晶質半導体膜４１０となる。
【００９２】
この後、ＴＦＴの活性層となる第１の結晶質半導体膜４０８から金属元素（Ｎｉ）のゲッタリングを行う。そこで、図６（Ａ）に示すように、第２の結晶質半導体膜４１０上に燐（Ｐ）またはアルゴン（Ａｒ）といった不純物を添加する。なお、この時、先に形成された絶縁膜４０５がマスクとなるため第１の結晶質半導体膜４０８の一部であって、絶縁膜４０５に覆われていない領域ｂ（４０９）にも燐（Ｐ）またはアルゴン（Ａｒ）が添加され、ゲッタリングサイトを形成することができる。不純物を添加した後で、熱処理（窒素雰囲気下で６００℃、１２時間）を行うことにより、結晶質半導体膜中に存在する金属元素（Ｎｉ）をゲッタリングサイトに移動させることができる。
【００９３】
次に、不純物が添加された第１の結晶質半導体膜４０８の一部である領域ｂ（４０９）および第２の結晶質半導体膜４１０をエッチングにより除去する（図６（Ｂ））。さらに、絶縁膜４０５を除去することにより、膜中に存在する結晶化を促進する金属元素を結晶化直後よりも低減させた第１の結晶質半導体膜４１１を得ることができる。
【００９４】
なお、本実施例では、第１の結晶質半導体膜４１１上に新たに絶縁膜を形成し、熱処理を行うことにより第１の結晶質半導体膜４１１の上部を熱酸化させる。このような熱処理を行うことにより結晶内部の粒内欠陥を減少させることができるので、第１の結晶質半導体膜４１１の結晶性を向上させることができる。具体的には、減圧ＣＶＤ装置で２０ｎｍの酸化珪素膜を成膜した後、ファーネスアニール炉で熱処理を行う。この処理により、第１の結晶質半導体膜４１１の上部は酸化される。
【００９５】
そして、酸化珪素膜および第１の結晶質半導体膜４１１の酸化した部分をエッチングすると共にパターニングを行い、第１の結晶質半導体膜４１１の不要な部分を除去することにより、結晶性の向上した半導体層４１２が得られる（図６（Ｃ１））。なお、半導体層４１２を形成した後の画素上面図を図６（Ｃ２）に示す。図６（Ｃ２）において、点線Ａ−Ａ’で切断した断面図が図６（Ｃ１）に相当する。
【００９６】
次に、保持容量を形成するため、マスク４１３を形成して半導体層４１２の一部（保持容量とする領域）４１４にリンをドーピングする（図７（Ａ））。
【００９７】
次に、マスク４１３を除去し、半導体層４１２を覆う絶縁膜を形成した後、マスク４１５を形成して保持容量とする領域４１４上の絶縁膜を除去する（図７（Ｂ））。
【００９８】
次に、マスク４１５を除去し、新たに絶縁膜（ゲート絶縁膜）４１６ａを成膜する。ここで新たな絶縁膜を成膜することにより最終的なゲート絶縁膜の膜厚は８０ｎｍとなった。なお、保持容量とする領域上に他の領域より薄い絶縁膜４１６ｂを形成する（図７（Ｃ１））。ここでの画素上面図を図７（Ｃ２）に示す。図７（Ｃ２）において、点線Ｂ−Ｂ’で切断した断面図が図７（Ｃ１）に相当する。また、図７中の鎖線内で示した領域は、薄い絶縁膜４１６ｂが形成されている部分である。
【００９９】
次に、ＴＦＴのチャネル領域となる領域にｐ型またはｎ型の不純物元素を低濃度に添加するチャネルドープ工程を全面または選択的に行う。このチャネルドープ工程は、ＴＦＴしきい値電圧を制御するための工程である。なお、ここではジボラン（Ｂ₂Ｈ₆）を質量分離しないでプラズマ励起したイオンドープ法でボロンを添加した。もちろん、質量分離を行うイオンインプランテーション法を用いてもよい。
【０１００】
次に、絶縁膜４１６ａ、及び絶縁膜４０３ａ、４０３ｂ上にマスク４１７を形成し、走査線４０２に達するコンタクトホールを形成する（図８（Ａ））。そして、コンタクトホールの形成後、マスクを除去する。
【０１０１】
次に、導電膜を形成し、パターニングを行ってゲート電極４１８および容量配線４１９を形成する。（図８（Ｂ））ここでは、リンがドープされたシリコン膜（膜厚１５０ｎｍ）とタングステンシリサイド（膜厚１５０ｎｍ）との積層構造を用いた。なお、保持容量は、絶縁膜４１６ｂを誘電体とし、容量配線４１９と半導体層４１２の一部とで構成されている。
【０１０２】
次に、ゲート電極４１８および容量配線４１９をマスクとして自己整合的にリンを低濃度に添加する（図８（Ｃ１））。ここでの画素上面図を図８（Ｃ２）に示す。図８（Ｃ２）において、点線Ｃ−Ｃ’で切断した断面図が図８（Ｃ１）に相当する。この低濃度に添加された領域のリンの濃度が、１×１０¹⁶〜５×１０¹⁸ａｔｏｍｓ／ｃｍ³、代表的には３×１０¹⁷〜３×１０¹⁸ａｔｏｍｓ／ｃｍ³となるように調整する。
【０１０３】
さらに、マスク４２０を形成してリンを高濃度に添加し、ソース領域またはドレイン領域となる高濃度不純物領域４２１を形成する。（図９（Ａ））この高濃度不純物領域のリンの濃度が１×１０²⁰〜１×１０²¹ａｔｏｍｓ／ｃｍ³（代表的には２×１０²⁰〜５×１０²⁰ａｔｏｍｓ／ｃｍ³）となるように調整する。なお、半導体層４１２のうち、ゲート電極４１８と重なる領域はチャネル形成領域４２２となり、マスク４２０で覆われた領域は低濃度不純物領域４２３となりＬＤＤ領域として機能する。そして、不純物元素の添加後、マスク４２０を除去する。
【０１０４】
なお、ここでは図示しないが、画素と同一基板上に形成される駆動回路に用いるｐチャネル型ＴＦＴを形成するために、マスクでｎチャネル型ＴＦＴとなる領域を覆い、ボロンを添加してソース領域またはドレイン領域を形成する。
【０１０５】
次に、マスク４２０を除去した後、ゲート電極４１８および容量配線４１９を覆うパッシベーション膜４２４を形成する。このパッシベーション膜４２４は、ゲート電極４１８の酸化を防ぐとともに、後の平坦化の工程でエッチングストッパーとして機能する。ここでは、酸化シリコン膜を７０ｎｍの膜厚で形成した。次いで、半導体層４１２にそれぞれの濃度で添加されたｎ型またはｐ型不純物元素を活性化するための熱処理工程を行う。ここでは９５０℃、３０分の加熱処理を行う。
【０１０６】
そして、有機樹脂材料またはシリコン材料からなる層間絶縁膜４２５を形成する。ここでは膜厚１μｍの酸化窒化珪素膜を用い、エッチバックを行って平坦化を行った。次に、半導体層４１２に達するコンタクトホールを形成した後、電極４２６及びソース配線４２７を形成する。本実施例では電極４２６及びソース配線４２７を、Ｔｉ膜を１００ｎｍ、Ｔｉを含むアルミニウム膜を３００ｎｍ、Ｔｉ膜１５０ｎｍをスパッタ法で連続して形成した３層構造の積層膜とする（図９（Ｂ１））。なお、図９（Ｂ２）において点線Ｄ−Ｄ’で切断した断面図が図９（Ｂ１）に相当する。
【０１０７】
そして、水素化処理を行った後、酸化窒化珪素膜（膜厚５００ｎｍ）とＢＣＢ（ベンゾシクロブテン）（膜厚１μｍ）と（膜厚３００ｎｍ）との積層からなる層間絶縁膜４２８を形成する（図１０（Ａ１））。次に、層間絶縁膜４２８上に遮光性を有する導電膜（膜厚１００ｎｍ）を成膜し、パターニングを行って遮光層４２９を形成する。さらに、膜厚１５０ｎｍの酸化窒化珪素膜からなる層間絶縁膜４３０を形成する。
【０１０８】
次に、電極４２６に達するコンタクトホール形成する。そして、１００ｎｍの透明導電膜（ここでは酸化インジウム・スズ（ＩＴＯ）膜）を形成した後、パターニングして画素電極４３１、４３２を形成する。図１０（Ａ２）において、点線Ｅ−Ｅ’で切断した断面図が図１０（Ａ１）に相当する。
【０１０９】
こうして画素部には、表示領域（画素サイズ２６μｍ×２６μｍ）の面積（開口率７６．５％）を確保しつつ、ｎチャネル型ＴＦＴでなる画素ＴＦＴが形成され、十分な保持容量（５１．５ｆＦ）を得ることができる。
【０１１０】
なお、本実施例は一例であって本実施例の工程に限定されないことはいうまでもない。例えば、各導電膜としては、タンタル（Ｔａ）、チタン（Ｔｉ）、モリブデン（Ｍｏ）、タングステン（Ｗ）、クロム（Ｃｒ）、シリコン（Ｓｉ）から選ばれた元素、または前記元素を組み合わせた合金膜（代表的には、Ｍｏ―Ｗ合金、Ｍｏ―Ｔａ合金）を用いることができる。また、各絶縁膜としては、酸化シリコン膜や窒化シリコン膜や酸化窒化シリコン膜や有機樹脂（ポリイミド、アクリル、ポリアミド、ポリイミドアミド、ＢＣＢ等）膜を用いることができる。
【０１１１】
また、こうして得られたＴＦＴの特性は、良好な電気特性値を示した。なお、図１１には、ｐチャネル型ＴＦＴの電界効果移動度に関する特性を示し、図１２には、ｎチャネル型ＴＦＴの電界効果移動度に関する特性を示す。なお、図１１、図１２において、グラフの横軸に移動度をとり、縦軸には累積度数分布を示している。また、いずれの場合も従来の結晶化方法（従来法）により得られた結晶質半導体膜を活性層に用いたＴＦＴ（チャネル形成領域の長さ（Ｌ）／チャネル形成領域の幅（Ｗ）＝５０μｍ／５０μｍ）と本発明の結晶化方法（本発明）により得られた結晶質半導体膜を活性層に用いたＴＦＴ（Ｌ／Ｗ＝５０μｍ／５０μｍ）との比較を行っている。
【０１１２】
なお、図１１、図１２のいずれの場合においても、本発明を用いて形成されたＴＦＴに関するグラフの分布は、従来法を用いて形成されたＴＦＴに比べてその傾きが大きくなっていると共に、高い移動度において分布している。このことから、本発明を用いて形成されたＴＦＴは、ｐチャネル型ＴＦＴ、およびｎチャネル型ＴＦＴのいずれの場合においても従来法を用いて形成されたＴＦＴよりもバラツキが小さく、かつ移動度が高いという優れた特性を有することが確認された。
【０１１３】
（実施例４）
本実施例では、実施例３のアクティブマトリクス基板から、アクティブマトリクス型液晶表示装置を作製する工程を以下に説明する。説明には図１３を用いる。
【０１１４】
まず、実施例３に従い、図１３の状態のアクティブマトリクス基板を得た後、図１３のアクティブマトリクス基板上に配向膜を形成しラビング処理を行う。なお、本実施例では配向膜を形成する前に、アクリル樹脂膜等の有機樹脂膜をパターニングすることによって基板間隔を保持するための柱状のスペーサを所望の位置に形成する。また、柱状のスペーサに代えて、球状のスペーサを基板全面に散布してもよい。
【０１１５】
次いで、対向基板を用意する。この対向基板には、着色層、遮光層が各画素に対応して配置されたカラーフィルタが設けられている。また、駆動回路の部分にも遮光層を設ける。そして、このカラーフィルタと遮光層とを覆う平坦化膜を設ける。次いで、平坦化膜上に透明導電膜からなる対向電極を画素部に形成し、対向基板の全面に配向膜を形成し、ラビング処理を施す。
【０１１６】
そして、画素部と駆動回路が形成されたアクティブマトリクス基板と対向基板とをシール材で貼り合わせる。シール材にはフィラーが混入されていて、このフィラーと柱状スペーサによって均一な間隔を持って２枚の基板が貼り合わせられる。その後、両基板の間に液晶材料を注入し、封止剤（図示せず）によって完全に封止する。液晶材料には公知の液晶材料を用いれば良い。このようにしてアクティブマトリクス型液晶表示装置が完成する。そして、必要があれば、アクティブマトリクス基板または対向基板を所望の形状に分断する。さらに、公知の技術を用いて偏光板等を適宜設けた後、公知の技術を用いてＦＰＣを貼りつける。
【０１１７】
このようにして得られた液晶モジュールの構成を図１３の上面図を用いて説明する。
【０１１８】
アクティブマトリクス基板１３０１の中央には、画素部１３０４が配置されている。画素部１３０４の上側には、ソース信号線を駆動するためのソース信号線駆動回路１３０２が配置されている。また、画素部１３０４の左右には、ゲート信号線を駆動するためのゲート信号線駆動回路１３０３が配置されている。本実施例に示した例では、ゲート信号線駆動回路１３０３は画素部に対して左右対称配置としているが、これは片側のみの配置でも良く、液晶モジュールの基板サイズ等を考慮して、設計者が適宜選択すれば良い。ただし、回路の動作信頼性や駆動効率等を考えると、図１３に示した左右対称配置が望ましい。
【０１１９】
各駆動回路への信号の入力は、フレキシブルプリント基板（Flexible Print Circuit：ＦＰＣ）１３０５から行われる。ＦＰＣ１３０５は、基板１３０１の所定の場所まで配置された配線に達するように、層間絶縁膜および樹脂膜にコンタクトホールを開口し、接続電極（図示せず）を形成した後、異方性導電膜等を介して圧着される。本実施例においては、接続電極はＩＴＯを用いて形成する。
【０１２０】
駆動回路、画素部の周辺には、基板外周に沿ってシール剤１３０７が塗布され、あらかじめアクティブマトリクス基板上に形成されたスペーサ（図示せず）によって一定のギャップ（基板１３０１と対向基板１３０６との間隔）を保った状態で、対向基板１３０６が貼り付けられる。その後、シール剤１３０７が塗布されていない部分より液晶素子が注入され、封止剤１３０８によって密閉される。以上の工程により、液晶モジュールが完成する。
【０１２１】
また、ここでは全ての駆動回路を基板上に形成した例を示したが、駆動回路の一部に数個のＩＣを用いてもよい。
【０１２２】
（実施例５）
本実施例では、本発明の作製方法を用いて作製された結晶質半導体膜を活性層に用いて形成されたＴＦＴを画素部（スイッチング用ＴＦＴ、電流制御用ＴＦＴ）および駆動回路部（ソース側駆動回路、ゲート側駆動回路）に含むアクティブマトリクス型の発光装置について図１６を用いて説明する。
【０１２３】
図１４（Ａ）は、発光装置を示す上面図、図１４（Ｂ）は図１４（Ａ）をＡ−Ａ’で切断した断面図である。点線で示された１４０１はソース側駆動回路、１４０２は画素部、１４０３はゲート側駆動回路である。また、１４０４は封止基板、１４０５はシール剤であり、シール剤１４０５で囲まれた内側は、空間１４０７になっている。
【０１２４】
なお、１４０８はソース側駆動回路１４０１及びゲート側駆動回路１４０３に入力される信号を伝送するための配線であり、外部入力端子となるＦＰＣ（フレキシブルプリントサーキット）１４０９からビデオ信号やクロック信号を受け取る。なお、ここではＦＰＣしか図示されていないが、このＦＰＣにはプリント配線基盤（ＰＷＢ）が取り付けられていても良い。
【０１２５】
次に、断面構造について図１４（Ｂ）を用いて説明する。基板１４１０上には駆動回路及び画素部が形成されているが、ここでは、駆動回路としてソース側駆動回路１４０１と画素部１４０２が示されている。
【０１２６】
なお、ソース側駆動回路１４０１はｎチャネル型ＴＦＴ１４１３とｐチャネル型ＴＦＴ１４１４とを組み合わせたＣＭＯＳ回路が形成される。また、駆動回路を形成するＴＦＴは、公知のＣＭＯＳ回路、ＰＭＯＳ回路もしくはＮＭＯＳ回路で形成しても良い。また、本実施の形態では、基板上に駆動回路を形成したドライバー一体型を示すが、必ずしもその必要はなく、基板上ではなく外部に形成することもできる。
【０１２７】
また、画素部１４０２は、ソース側駆動回路からの映像信号が入力されるスイッチング用ＴＦＴ１４１１と、スイッチング用ＴＦＴ１４１１と接続され、かつ発光素子の輝度を制御する機能を有する電流制御用ＴＦＴ１４１２と、電流制御用ＴＦＴ１４１１のドレインに電気的に接続された第１の電極（陽極）１４１３を含む複数の画素により形成される。
【０１２８】
また、第１の電極（陽極）１４１３の両端には絶縁層１４１４が形成され、第１の電極（陽極）１４１３上には有機化合物層１４１５が形成される。さらに、有機化合物層１４１５上には第２の電極（陰極）１４１６が形成される。これにより、第１の電極（陽極）１４１３、有機化合物層１４１５、及び第２の電極（陰極）１４１６からなる発光素子１４１８が形成される。
【０１２９】
さらに、第２の電極（陰極）１４１６上に補助配線１４１７が形成される。補助配線１４１７は、接続配線１４１７と電気的に接続されており、ＦＰＣ１４０９を介して外部電源と電気的に接続されている。
【０１３０】
また、基板１４１０上に形成された発光素子１４１８を封止するためにシール剤１４０５により封止基板１４０４を貼り合わせる。なお、封止基板１４０４と発光素子１４１８との間隔を確保するために樹脂膜からなるスペーサを設けても良い。そして、シール剤１４０５の内側の空間１４０７には窒素等の不活性気体が充填されている。なお、シール剤１４０５としてはエポキシ系樹脂を用いるのが好ましい。また、シール剤１４０５はできるだけ水分や酸素を透過しない材料であることが望ましい。さらに、空間１４０７の内部に酸素や水を吸収する効果をもつ物質を含有させても良い。
【０１３１】
また、本実施の形態では封止基板１４０４を構成する材料としてガラス基板や石英基板の他、ＦＲＰ（Fiberglass-Reinforced Plastics）、ＰＶＦ（ポリビニルフロライド）、マイラー、ポリエステルまたはアクリル等からなるプラスチック基板を用いることができる。また、シール剤１４０５を用いて封止基板１４０４を接着した後、さらに側面（露呈面）を覆うようにシール剤で封止することも可能である。
【０１３２】
以上のようにして発光素子を空間１４０７に封入することにより、発光素子を外部から完全に遮断することができ、外部から水分や酸素といった有機化合物層の劣化を促す物質が侵入することを防ぐことができる。従って、信頼性の高い発光装置を得ることができる。
【０１３３】
なお、本実施の形態の構成は、実施例１または実施例２において作製されたＴＦＴを用いて実施することが可能である。
【０１３４】
（実施例６）
本発明を用いて形成されたＴＦＴは、様々なモジュール（アクティブマトリクス型液晶モジュール、アクティブマトリクス型発光モジュール、アクティブマトリクス型ＥＣモジュール）に用いることができる。すなわち、それらを表示部に組み込むことにより電気器具を完成させることができる。
【０１３５】
そのような電気器具として、ビデオカメラ、デジタルカメラ、ゴーグル型ディスプレイ（ヘッドマウントディスプレイ）、ナビゲーションシステム、音響再生装置（カーオーディオ、オーディオコンポ等）、ノート型パーソナルコンピュータ、ゲーム機器、携帯情報端末（モバイルコンピュータ、携帯電話、携帯型ゲーム機または電子書籍等）、記録媒体を備えた画像再生装置（具体的にはデジタルビデオディスク（ＤＶＤ）等の記録媒体を再生し、その画像を表示しうる表示装置を備えた装置）などが挙げられる。特に、斜め方向から画面を見る機会が多い携帯情報端末は、視野角の広さが重要視されるため、発光素子を有する発光装置を用いることが好ましい。それら電気器具の具体例を図１５に示す。
【０１３６】
図１５（Ａ）は表示装置であり、筐体２００１、支持台２００２、表示部２００３、スピーカー部２００４、ビデオ入力端子２００５等を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２００３に用いることにより作製される。なお、表示装置は、パソコン用、ＴＶ放送受信用、広告表示用などの全ての情報表示用表示装置が含まれる。
【０１３７】
図１５（Ｂ）はデジタルスチルカメラであり、本体２１０１、表示部２１０２、受像部２１０３、操作キー２１０４、外部接続ポート２１０５、シャッター２１０６等を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２１０２に用いることにより作製される。
【０１３８】
図１５（Ｃ）はノート型パーソナルコンピュータであり、本体２２０１、筐体２２０２、表示部２２０３、キーボード２２０４、外部接続ポート２２０５、ポインティングマウス２２０６等を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２２０３に用いることにより作製される。
【０１３９】
図１５（Ｄ）はモバイルコンピュータであり、本体２３０１、表示部２３０２、スイッチ２３０３、操作キー２３０４、赤外線ポート２３０５等を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２３０２に用いることにより作製される。
【０１４０】
図１５（Ｅ）は記録媒体を備えた携帯型の画像再生装置（具体的にはＤＶＤ再生装置）であり、本体２４０１、筐体２４０２、表示部Ａ２４０３、表示部Ｂ２４０４、記録媒体（ＤＶＤ等）読み込み部２４０５、操作キー２４０６、スピーカー部２４０７等を含む。表示部Ａ２４０３は主として画像情報を表示し、表示部Ｂ２４０４は主として文字情報を表示するが、本発明により作製したＴＦＴを用いたモジュールをこれら表示部Ａ、Ｂ２４０３、２４０４に用いることにより作製される。なお、記録媒体を備えた画像再生装置には家庭用ゲーム機器なども含まれる。
【０１４１】
図１５（Ｆ）はゴーグル型ディスプレイ（ヘッドマウントディスプレイ）であり、本体２５０１、表示部２５０２、アーム部２５０３を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２５０２に用いることにより作製される。
【０１４２】
図１５（Ｇ）はビデオカメラであり、本体２６０１、表示部２６０２、筐体２６０３、外部接続ポート２６０４、リモコン受信部２６０５、受像部２６０６、バッテリー２６０７、音声入力部２６０８、操作キー２６０９、接眼部２６１０等を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２６０２に用いることにより作製される。
【０１４３】
ここで図１５（Ｈ）は携帯電話であり、本体２７０１、筐体２７０２、表示部２７０３、音声入力部２７０４、音声出力部２７０５、操作キー２７０６、外部接続ポート２７０７、アンテナ２７０８等を含む。本発明により作製したＴＦＴを用いたモジュールをその表示部２７０３に用いることにより作製される。なお、表示部２７０３は黒色の背景に白色の文字を表示することで携帯電話の消費電力を抑えることができる。
【０１４４】
なお、将来的に有機材料の発光輝度が高くなれば、出力した画像情報を含む光をレンズ等で拡大投影してフロント型若しくはリア型のプロジェクターに用いることも可能となる。
【０１４５】
以上の様に、本発明の作製方法を用いて作製されたＴＦＴを用いたモジュールの適用範囲は極めて広く、あらゆる分野の電気器具を作製することが可能である。また、本実施例における電気器具は実施例１〜実施例５のいずれかを自由に組み合わせて実施することが可能である。
【０１４６】
【発明の効果】
本発明の非晶質半導体膜の結晶化において、膜中酸素濃度の高い非晶質半導体膜と膜中酸素濃度の低い非晶質半導体膜を接して形成し、膜中酸素濃度の高い非晶質半導体膜に結晶化を促進するための金属元素を添加して結晶化を行うことにより、結晶核が発生しやすいという特徴を活かして結晶化を促進させ、さらに、膜中酸素濃度の高い非晶質半導体膜と接して形成される膜中酸素濃度の低い非晶質半導体膜を結晶化させることにより、従来の結晶化法に比べて金属元素の添加量を低減させることができる。さらに、金属元素の添加量を低減させたにも拘わらず膜中酸素濃度の低い非晶質半導体膜からなる結晶質半導体膜を得ることができるため結晶粒径が大きい膜を得ることができる。また、この結晶質半導体膜は非常に結晶配向率の高い結晶質半導体膜であった。
【０１４７】
さらに、このような、結晶質半導体膜を活性層に用いて薄膜トランジスタを形成することにより、電気的な特性に優れた薄膜トランジスタ、およびこれらの薄膜トランジスタで構成された回路を有する半導体装置を形成することができる。
【図面の簡単な説明】
【図１】 本発明の結晶化の工程を説明する図。
【図２】 結晶化された結晶質シリコン膜表面の観察写真図。
【図３】 ＴＦＴの作製工程を説明する図。
【図４】 ＴＦＴの作製工程を説明する図。
【図５】 アクティブマトリクス型の液晶表示装置の作製工程を説明する図。
【図６】 アクティブマトリクス型の液晶表示装置の作製工程を説明する図。
【図７】 アクティブマトリクス型の液晶表示装置の作製工程を説明する図。
【図８】 アクティブマトリクス型の液晶表示装置の作製工程を説明する図。
【図９】 アクティブマトリクス型の液晶表示装置の作製工程を説明する図。
【図１０】 アクティブマトリクス型の液晶表示装置の作製工程を説明する図。
【図１１】 ｐチャネル型ＴＦＴ（Ｌ／Ｗ＝５０／５０）の電界効果移動度を示すグラフ。
【図１２】 ｎチャネル型ＴＦＴ（Ｌ／Ｗ＝５０／５０）の電界効果移動度を示すグラフ。
【図１３】 液晶表示装置の外観を説明する図。
【図１４】 発光装置の外観を説明する図。
【図１５】 電気器具の一例を示す図。
【図１６】 ＥＢＳＰ法により測定された逆極点図を示す図。
【符号の説明】
１００ 基板
１０１ 第１の非晶質半導体膜
１０２、１０３ 絶縁膜
１０４ 第２の非晶質半導体膜
１０５ 金属元素
１０７ 第１の結晶質半導体膜
１０８ 第２の結晶質半導体膜
１１０ 第３の結晶質半導体膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for crystallizing an amorphous semiconductor film to produce a crystalline semiconductor film having a high orientation rate. Further, a thin film transistor manufactured using the crystalline semiconductor film and a semiconductor device including a circuit including the thin film transistor are included in the category.
[0002]
[Prior art]
In recent years, a thin film transistor (TFT) is formed using a semiconductor thin film (thickness of about several to several hundred nm) formed on a substrate having an insulating surface, and a semiconductor device having a large-area integrated circuit formed using this TFT is developed. Is progressing. As typical examples of semiconductor devices, liquid crystal display devices and light emitting devices are known.
[0003]
As a semiconductor thin film forming an active layer of a TFT, an amorphous silicon film (typically an amorphous silicon film) has been widely used so far. However, a demand for a TFT having a higher operation speed is increased, and a crystalline silicon film (typically In particular, a polysilicon film) is becoming mainstream. As a technique for obtaining this crystalline silicon film, a method in which an amorphous silicon film is formed and then crystallized by heat treatment or laser light irradiation is often used.
[0004]
In addition, after forming an amorphous silicon film, a catalyst element (for example, nickel) for promoting crystallization of the amorphous silicon film is introduced, and heat treatment is performed to obtain a crystalline silicon film (special feature). Kaihei 6-232059 and JP-A-7-321339) are disclosed. The crystal structure obtained by this technique (exactly the structure of the crystal grain boundary) is such that two different crystal grains are joined in a highly consistent manner at the crystal grain boundary, so that the crystal lattice is continuously connected, resulting in crystal defects and the like. It has a structure that makes it very difficult to create the trap level. That is, a crystalline silicon film substantially free of crystal grain boundaries can be formed.
[0005]
Further, in a TFT formed by using the crystalline silicon film as an active layer, Japanese Patent Application No. 2000-332249 discloses (1) a subthreshold coefficient which is an index of switching performance (on / off operation switching agility). Both N-channel TFT and P-channel TFT are small. (2) Field-effect mobility (μ _FE ) Is large for both N-channel TFTs and P-channel TFTs. (3) Threshold voltage (V _th However, both the N-channel TFT and the P-channel TFT are small. Such excellent electrical characteristics are obtained.
[0006]
However, in carrying out the above technique, the metal element for promoting crystallization added to the amorphous silicon film has a problem that a complete crystalline silicon film cannot be obtained unless a minimum necessary amount is added. On the other hand, if it is added excessively, removal after crystallization is difficult, and even if the region where the metal element that promotes crystallization is present at a high concentration is removed by etching or the like, it can be completely removed. However, the metal element that promotes crystallization remaining in the crystalline silicon film has a conflicting problem that the characteristics of the TFT are deteriorated.
[0007]
[Problems to be solved by the invention]
Therefore, in order to solve the above-described problems, the present invention provides a method for obtaining sufficient crystallization even when a metal element that promotes crystallization is added at a lower concentration than in the past in crystallization of an amorphous semiconductor film. The purpose is to provide.
[0008]
Furthermore, it is an object of the present invention to provide a crystalline semiconductor film obtained by the crystallization method of the present invention having excellent electrical characteristics as compared with a crystalline semiconductor film obtained by a conventional crystallization method.
[0009]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present inventor is an amorphous semiconductor film for promoting crystallization, in a film known to easily generate crystal nuclei (that is, high nucleation density). An amorphous semiconductor film having a high oxygen concentration is used, and an amorphous semiconductor film that becomes a crystalline semiconductor film that is finally used for an active layer of a TFT by crystallization has a crystal grain size formed at the time of crystallization. It is characterized by using an amorphous semiconductor film having a low oxygen concentration in the film, which is known to have a large value.
[0010]
In the present invention, the oxygen concentration in the film is 1 × 10 5. ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three The amorphous semiconductor film is a film having a high oxygen concentration in the film, and the oxygen concentration in the film is 1 × 10 ¹⁸ atoms / cm ^Three The amorphous semiconductor film that is less than this is distinguished as a film having a low oxygen concentration in the film.
[0011]
In the present invention, a film having a high oxygen concentration in the film and a film having a low oxygen concentration are formed in contact with each other, and a metal element for promoting crystallization is added to the amorphous semiconductor film having a high oxygen concentration in the film. As a result, the amorphous semiconductor film having a high oxygen concentration in the film is first crystallized. Note that in the case of crystallization, a heat treatment is performed after a metal element that promotes crystallization is added. In addition, an amorphous semiconductor film having a high oxygen concentration in the film has a high oxygen concentration in the film. Low Since it is formed in contact with the amorphous semiconductor film, it is crystallized together with the crystallization of the amorphous semiconductor film having a high oxygen concentration in the film.
[0012]
Furthermore, in the present invention, an amorphous semiconductor film having a high oxygen concentration in the film and an amorphous semiconductor film having a low oxygen concentration in the film are not formed in full contact with each other, but have a structure in which they are in contact with each other. Have. That is, after an amorphous semiconductor film having a low oxygen concentration in the film is first formed, an insulating film is formed so as to cover a part thereof. Next, an amorphous semiconductor film having a high oxygen concentration in the film is formed over the insulating film and the amorphous semiconductor film having a low oxygen concentration in the film which is not covered therewith. Then, as described above, the amorphous semiconductor film having a high oxygen concentration in the film and the amorphous semiconductor film having a low oxygen concentration in the film are crystallized.
[0013]
Note that the insulating film formed here forms a gettering region when removing a metal element present in a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film having a low oxygen concentration in the film. It has a function as a mask at the time of addition of impurities. Further, after crystallization and gettering, it functions as an etching stopper when etching is performed while leaving only the crystalline semiconductor film from which the metal element has been removed.
[0014]
That is, when crystallization is completed, impurities are doped from above the amorphous semiconductor film having a high oxygen concentration in the film, using the previously formed insulating film as a mask. Thus, impurities can be added to part of the crystalline semiconductor film formed of an amorphous semiconductor film having a low oxygen concentration in the film.
[0015]
After the impurity is added, heat treatment is performed, so that the metal element that promotes crystallization included in the crystalline semiconductor film covered with the insulating film can be moved to the impurity-added region.
[0016]
Thereafter, in the etching of the crystallized crystalline semiconductor film, the region doped with impurities, the insulating film and other than the crystalline semiconductor film covered with the insulating film can be selectively removed. The desired crystalline semiconductor film can be obtained by etching the insulating film.
[0017]
Note that in the invention relating to the manufacturing method disclosed in the present invention, the oxygen concentration in the film is 1 × 10 6 on the insulating surface. ¹⁸ atoms / cm ^Three A first amorphous semiconductor film is formed, an insulating film is formed on the first amorphous semiconductor film, and a part of the insulating film is removed to remove the first amorphous semiconductor film. A portion of the semiconductor film is exposed, and the oxygen concentration in the film is 1 × 10 3 over the insulating film and the exposed first amorphous semiconductor film. ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three The second amorphous semiconductor film is formed by adding a metal element that promotes crystallization to the second amorphous semiconductor film and heating the second amorphous semiconductor film. Generating crystal nuclei therein and growing the crystal nuclei to crystallize the first amorphous semiconductor film and the second amorphous semiconductor film, respectively. Forming a second crystalline semiconductor film and adding an impurity on the second crystalline semiconductor film, thereby adding the impurity to a part of the first crystalline film using the insulating film as a mask. The metal element contained in the first crystalline semiconductor film is removed by moving the metal element to the impurity-added region by heating after adding the impurity and removing the impurity-added region. A method for producing a crystalline semiconductor film
[0018]
Note that in the above structure, an amorphous semiconductor film with a high oxygen concentration in the film can be formed by a plasma CVD method, and an amorphous semiconductor film with a low oxygen concentration in the film can be formed by a low pressure CVD (LPCVD) method.
[0019]
In the above structure, after forming an amorphous semiconductor film having a low oxygen concentration in the film and forming an insulating film covering a part of the amorphous semiconductor film, one kind selected from hydrogen, nitrogen, ammonia, and a rare gas element or Removing a natural oxide film formed on the surface of an amorphous semiconductor film having a low oxygen concentration in the film by exposing it to an atmosphere in which a gas containing a plurality of species as a main component is turned into a plasma This is a preferable means for further promoting crystallization of a low amorphous semiconductor film.
[0020]
Further, in each of the above structures, the metal element that promotes crystallization is one or more selected from Fe, Cu, Co, Ni, Pd, Pt, and Au.
[0021]
By using the method described above, it is possible to form a crystalline semiconductor film made of an amorphous semiconductor film having a low oxygen concentration in the film, which has excellent film characteristics when forming a crystalline semiconductor film, and is crystallized. In, since the crystallization is promoted by using an amorphous semiconductor film having excellent crystallinity and high oxygen concentration in the film, the concentration of the metal element that promotes crystallization added during crystallization is reduced. It becomes possible.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
An embodiment of the present invention will be described with reference to FIG.
[0023]
In the present invention, an amorphous semiconductor film (first amorphous semiconductor film) 101 having a low oxygen concentration in the film is formed over the substrate 100 having an insulating surface by an LPCVD method. During film formation, SiH _Four , Si ₂ H ₆ , SiF _Four Or SiH _Four And H ₂ And GeH _Four A reaction gas comprising the above is added and introduced into the reaction chamber, and if necessary, the reaction gas is diluted with He and an amorphous semiconductor film is deposited on the substrate at a temperature of 400 to 580 ° C. to form. Thereby, the oxygen concentration in the film is 1 × 10. ¹⁸ atoms / cm ^Three The first amorphous semiconductor film 101 that is less than the thickness can be formed. Specifically, in the reaction chamber, the temperature is set to 465 ° C., the film forming pressure is set to 0.5 Torr, and the reaction gas (Si ₂ H ₆ : 250 sccm) and a dilution gas (He: 300 sccm) are introduced so that the distance between the substrates having the film formation surfaces becomes 25.4 mm, whereby the film formation rate is 7 nm / min. Oxygen concentration is 2 × 10 ¹⁷ atoms / cm ^Three As a result, an amorphous semiconductor film was obtained. The conditions shown here are examples of the embodiment of the present invention, and do not limit the present invention. Therefore, the oxygen concentration in the film is 1 × 10 ¹⁸ atoms / cm ^Three If it is possible to make it less than the above, the above conditions can be changed, or other known methods can be used.
[0024]
Note that as the gas used here, a gas purified to a high purity in order to reduce the concentration of an impurity element such as oxygen, nitrogen, or carbon taken into the deposited amorphous semiconductor film is used. The thickness of the deposited amorphous semiconductor film is in the range of 20 to 100 nm.
[0025]
As the substrate material, a quartz substrate, a glass substrate, or the like can be used. The amorphous semiconductor film having a low oxygen concentration in the film formed here has an oxygen concentration of 1 × 10 5 in the film. ¹⁸ atoms / cm ^Three It is an amorphous semiconductor film that is less than.
[0026]
Next, the insulating film 102 is formed so as to cover part of the amorphous semiconductor film having a low oxygen concentration in the film. Note that as the insulating film 102 formed here, an insulating film containing silicon such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film formed by a plasma CVD method or an LPCVD method can be used. Further, after the film formation, patterning by photolithography is performed and etching is performed to form an island-shaped insulating film 103 that covers a part of the amorphous semiconductor film having a low oxygen concentration in the film.
[0027]
In this state, the first amorphous material having a low oxygen concentration in the film is obtained by exposing a gas mainly composed of one or more kinds selected from hydrogen, nitrogen, ammonia, and a rare gas element to a plasma atmosphere. The natural oxide film formed on the surface of the crystalline semiconductor film 101 may be removed.
[0028]
Next, an amorphous semiconductor film (second amorphous semiconductor film) 104 with a high oxygen concentration in the film is formed by plasma CVD, and a part of the first amorphous semiconductor film 101 with a low oxygen concentration in the film is formed. It is formed on the insulating film 103. During film formation, SiH _Four , Si ₂ H ₆ , SiF _Four Or SiH _Four And H ₂ And GeH _Four A reaction gas consisting of the following is added to the reaction chamber and decomposed by high-frequency discharge of 1 to 200 MHz to deposit and form an amorphous semiconductor film on the substrate. Thus, the oxygen concentration in the film is 1 × 10. ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three The second amorphous semiconductor film 104 can be formed. Specifically, in the reaction chamber, the upper heater is 300 ° C., the lower heater is 365 ° C., the film forming pressure is 0.25 Torr, and the reaction gas (SiH _Four : 100 sccm), RF power is 170 W (frequency: 10 KHz, pulse: duty ratio 30%), and Gap is 25 mm, so that the film formation rate is 50 nm / min. Oxygen concentration is 4 × 10 ¹⁸ atoms / cm ^Three As a result, an amorphous semiconductor film was obtained. The conditions shown here are examples of the embodiment of the present invention, and do not limit the present invention. Therefore, the oxygen concentration in the film is 1 × 10 ¹⁸ ~ 1x10 ²⁰ atoms / cm ^Three If the above conditions can be changed, oxygen or a gas containing oxygen as a component (O2, N ₂ O) may be introduced into the reaction chamber together with the reaction gas in a small amount.
[0029]
Note that the deposited amorphous semiconductor film has a thickness in the range of 20 to 100 nm.
[0030]
Next, a metal element 105 that promotes crystallization is added over the second amorphous semiconductor film 104 having a high oxygen concentration in the film. As the metal element 105, Fe, Cu, Co, Ni, Pd, Pt, Au, or the like can be used. In this embodiment, the metal element 306 is added by applying a nickel acetate salt solution containing 5 ppm of nickel in terms of weight with a spinner. However, instead of coating, a method of spraying nickel element over the entire surface by sputtering is used. It may be used.
[0031]
Next, these are crystallized by heat treatment to form a crystalline semiconductor film having a crystal structure. For this heat treatment, heat treatment in an electric furnace or irradiation with strong light may be used. When the heat treatment is performed in an electric furnace, the treatment may be performed at 500 ° C. to 650 ° C. for 4 to 24 hours. Note that in this embodiment, an amorphous semiconductor film (the first amorphous semiconductor film 101 and the second amorphous semiconductor film 104) is formed by performing heat treatment for crystallization (570 ° C., 24 hours). Is crystallized.
[0032]
Note that as a method of adding the metal element 105 that promotes crystallization, a method of applying a solution containing the metal element may be used, or a method of forming a thin film by a sputtering method or a CVD method may be used. In addition, since the first amorphous semiconductor film 101 is formed in contact with the second amorphous semiconductor film 104 to which the metal element is directly added in the region p (106), the first amorphous semiconductor film 101 can be crystallized. it can. That is, by crystallization, the first amorphous semiconductor film 101 becomes the first crystalline semiconductor film 107 and the second amorphous semiconductor film 104 becomes the second crystalline semiconductor film 108.
[0033]
Note that the crystalline semiconductor film finally required in the present invention is the first crystalline semiconductor film 107. Therefore, it is desirable to remove the metal element 105 that promotes crystallization added during crystallization after crystallization. Therefore, in the present invention, gettering is performed by adding an impurity in order to remove the metal element present in the first crystalline semiconductor film 107.
[0034]
Specifically, phosphorus or a rare gas (typically argon) is added over the second crystalline semiconductor film 108. At this time, phosphorus or a rare gas (typically argon) is also 1 × 10 6 in the region q (109) which is a part of the first crystalline semiconductor film 107 using the insulating film 103 as a mask. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three It is added at a concentration of about. Here, the metal element (typically Ni) present in the first crystalline semiconductor film 107 is moved to the region q (109) by performing heat treatment, and thus exists in the first crystalline semiconductor film 107. The metal element to be removed can be removed.
[0035]
Next, the portion of the first crystalline semiconductor film 107 covered with the insulating film 103 is left, and the crystallized crystalline semiconductor film is removed by etching. Further, by removing the insulating film 103, the third crystalline semiconductor film 110 containing no metal element can be obtained. Note that the third crystalline semiconductor film 110 obtained here is present in the film before gettering because the metal element used for crystallization can be performed at a lower concentration than the conventional crystalline semiconductor film. Since the amount of metal element to be performed is small, removal of the metal element by gettering is easier than in the case of conventional crystallization.
[0036]
Note that a feature of the present invention is that crystallization is performed using two types of amorphous semiconductor films to obtain a crystalline semiconductor film having a low oxygen concentration and a large grain size as the first amorphous semiconductor film. As the second amorphous semiconductor film, an amorphous semiconductor film having a high oxygen concentration in the film and easily generating crystal nuclei (high nucleation density) is used as the first amorphous semiconductor film. By being formed in contact with the semiconductor film, the second amorphous semiconductor film functions to promote crystallization, and the first amorphous semiconductor film is crystallized.
[0037]
Here, FIG. 2 shows a state of the crystalline semiconductor film when an amorphous semiconductor film mainly composed of silicon having different oxygen concentrations in the film is crystallized. In FIG. 2A, the oxygen concentration in the film is 3 × 10. ¹⁷ atoms / cm ^Three A crystalline semiconductor film obtained by crystallizing the amorphous semiconductor film, FIG. 2B shows an oxygen concentration in the film of 9 × 10 ¹⁷ atoms / cm ^Three An optical micrograph of a crystalline semiconductor film obtained by crystallizing the amorphous semiconductor film is shown. Note that the film obtained by crystallizing an amorphous semiconductor film having a low oxygen concentration in the film has a crystal grain size larger than that of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film having a high oxygen concentration in the film. It can be seen that is increasing. Note that the most abundant hydrogen contained in the film has the same concentration (5 × 10 5) in any film. ²⁰ atoms / cm ^Three ) Was included.
[0038]
Usually, at the crystal grain interface (grain boundary), the current transport characteristics of the carrier deteriorate due to the influence of the recombination center, trap center, and potential level at the grain boundary due to the amorphous structure and crystal defects. For this reason, it is known that the presence of crystal grain boundaries in the channel formation region limits the characteristics of TFTs, and there is a method for increasing the crystal grain size as one of means for solving this. It can be said that the crystalline semiconductor film in the present invention is a very excellent film in improving the TFT characteristics.
[0039]
Furthermore, the present invention is characterized in that the metal element that promotes crystallization added during crystallization is reduced as compared with the prior art. Specifically, when an amorphous semiconductor film formed by the LPCVD method is crystallized (conventional method), it is included in the crystalline semiconductor film obtained by crystallization by adding a 10 ppm Ni solution. Ni concentration is 5.56 × 10 ¹⁸ atoms / cm ^Three On the other hand, in the case of the present invention, a 10 ppm Ni solution is added to the amorphous semiconductor film formed by the plasma CVD method to promote crystallization, and further, the film is formed by the LPCVD method. In order to crystallize the amorphous semiconductor film, the concentration of Ni contained in the obtained crystalline semiconductor film is 2.66 × 10 6. ¹⁸ atoms / cm ^Three As a result, a very low concentration (about half of the conventional one) was obtained.
[0040]
Further, the crystal orientation of the surface of the crystalline semiconductor film containing silicon as a main component obtained in the present invention was measured by an EBSP (Electron BackScatter Diffraction Pattern) method.
[0041]
The EBSP method is a technique in which a scanning electron microscope (SEM: Scanning Electron Microscopy) is provided with a dedicated detector, and crystal orientation is analyzed from backscattering of primary electrons (hereinafter, this technique is referred to as an EBSP method for convenience). ). Specifically, when an electron beam is incident on a sample having a crystal structure, inelastic scattering occurs backwards, and a linear pattern (generally a Kikuchi image, which is specific to the crystal orientation by Bragg diffraction in the sample). It is a technique to determine the crystal orientation of the sample by analyzing this Kikuchi image.
[0042]
In addition, in the case of a polycrystalline structure in which each crystal grain has a different crystal orientation, the orientation analysis is repeated while moving the position of the electron beam applied to the sample (mapping measurement). Orientation or orientation information can be obtained.
[0043]
When all the crystal orientations of each crystal grain are obtained by mapping measurement, the state of crystal orientation with respect to the film can be statistically displayed. A reverse pole figure is often used to display the orientation distribution of a crystal having a polycrystalline structure. From the reverse pole figure, a specific plane of the sample (for example, the film surface) is preferentially oriented to which lattice plane. You can get information on whether you are doing.
[0044]
By mapping measurement and inverse pole figure, for a specific index ({100}, {110}, {111}) on each lattice plane, the ratio of how many crystal grains are gathered in the vicinity of the index is quantified. This makes it easier to image the existence ratio of each orientation. Therefore, in the inverse pole figure, each ratio with respect to the total number of points existing in the range (allowable value) where the deviation angle from the specific index of each lattice plane is 5 ° can be obtained by the following formula as each orientation ratio. .
[0045]
[Formula 1]

[0046]
Therefore, a crystalline semiconductor film (sample 1) containing silicon as a main component obtained by a conventional crystallization method and a crystalline semiconductor film containing silicon as a main component obtained by the crystallization method of the present invention. A crystalline semiconductor film (sample 2) obtained by adding a 3 ppm Ni solution at the time of crystallization, a crystalline semiconductor film containing silicon as a main component obtained by the crystallization method of the present invention. At this time, the crystalline semiconductor film (sample 3) obtained by adding a 30 ppm Ni solution was measured by the EBSP method, and specific indexes ({100}, {110} constituting each sample obtained by the equation 1) , {111}) is shown in Table 1.
[0047]
[Table 1]

[0048]
In Table 1, among the crystalline semiconductor films obtained by using the crystallization method of the present invention, the crystalline semiconductor film (sample 2) obtained by adding 3 ppm of Ni solution has an orientation ratio in the {111} plane. Was 74.4%. This indicates that the ratio of the angle between the {111} lattice plane detected by the backscattered electron diffraction pattern method and the surface of the crystalline semiconductor film is within 5 ° is 74.4%. In addition, FIG. 16 shows a reverse pole map for Sample 2 that showed such a high orientation ratio.
[0049]
In addition, by obtaining such a very high orientation rate (specifically, 60% or more), a plurality of crystal aggregates are caused by a boundary caused by different orientations or a difference in crystal aggregate size. Therefore, it is possible to reduce the influence on the TFT characteristics and reduce the variation between TFTs.
[0050]
For example, if the TFTs arranged in the pixel portion have variations in electrical characteristics, variations in the voltage applied to each pixel electrode will occur, resulting in variations in the amount of transmitted light, which will cause display unevenness and appear to the viewer's eyes. It will be. At present, this variation is within an acceptable range and is not a problem. However, if the pixel size is further miniaturized and higher definition images are required in the future, this variation will be very serious. It seems to be a problem. Further, since the wiring width is reduced and the size of the channel formation region (channel length, channel width) is also reduced, a TFT having a boundary between the sets in the channel formation region is inevitably formed, and the TFT characteristics (mobility) , S value, on-current value, off-current value, etc.) are different from those of a TFT having a channel formation region without a boundary, and this is considered to cause variation in display. Therefore, the manufacturing method of the present invention is used. It is very effective to produce a TFT using the crystalline semiconductor film produced in this way.
[0051]
【Example】
Examples of the present invention will be described below.
[0052]
Example 1
In this embodiment, a method for manufacturing a TFT using a crystalline semiconductor film crystallized by using the present invention using a quartz substrate (thickness: 1.1 mm) will be described with reference to FIGS.
[0053]
Note that the embodiment mode of the invention may be referred to for a method for manufacturing a crystalline semiconductor film. First, in this example, a new insulating film (silicon oxide film) is formed over the crystalline semiconductor film (third crystalline semiconductor film 110 obtained in the embodiment mode of the invention), and heat treatment is performed. The upper part of the crystalline semiconductor film is thermally oxidized. By performing such a heat treatment, intragranular defects inside the crystal can be reduced, so that the crystallinity of the crystalline semiconductor film can be improved. Then, the oxidized portions of the insulating film and the crystalline semiconductor film are etched and patterned to form the semiconductor layer 201.
[0054]
Next, after cleaning the surface of the semiconductor layer 201 with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component and serving as the gate insulating film 202 is formed. It is desirable that the surface cleaning and the formation of the gate insulating film are continuously performed without being exposed to the atmosphere (FIG. 3A).
[0055]
Next, after cleaning the surface of the gate insulating film 202, a gate electrode 203 is formed (FIG. 3B), and an impurity element imparting n-type conductivity to the semiconductor (P, As, etc.), here phosphorus is appropriately added. Thus, the source region 204 and the drain region 205 are formed (FIG. 3C). After the impurity element is added, heat treatment, intense light irradiation, or laser light irradiation is performed to activate the impurity element. By performing such treatment, plasma damage to the gate insulating film 202 and plasma damage to the interface between the gate insulating film 202 and the semiconductor layer 201 can be recovered simultaneously with activation. In particular, in an atmosphere of room temperature to 300 ° C., it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface. A YAG laser is a preferred activation means because it requires less maintenance.
[0056]
Next, an interlayer insulating film 206 is formed, hydrogenated, contact holes reaching the source region and the drain region are formed, and the source electrode 207 and the drain electrode 208 are formed to complete the TFT (FIG. 3D (E)).
[0057]
The TFT obtained in this way has a high crystal grain size of the crystalline semiconductor film forming the channel formation region 209 and a very high crystal orientation ratio, so that the uniformity in the film is high and it is formed on the substrate. There is little variation between TFTs.
[0058]
Note that the present invention is not limited to the structure of FIG. 3D, and if necessary, a lightly doped drain (LDD) having an LDD region between a channel formation region and a drain region (or source region). It is good also as a structure. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Further, a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film may be employed.
[0059]
Although an n-channel TFT has been described here, a p-channel TFT can be formed by using a p-type impurity element instead of an n-type impurity element.
[0060]
(Example 2)
In this example, a method for crystallizing an amorphous semiconductor film using a method different from that in Embodiment Mode and Example 1 will be described with reference to FIGS.
[0061]
In FIG. 4A, reference numeral 300 denotes a substrate having an insulating surface. In this embodiment, a glass substrate is used. Reference numeral 301 denotes a base insulating film, and 302 denotes a first amorphous semiconductor film having an amorphous structure. Further, an island-shaped insulating film 303 is formed over the first amorphous semiconductor film 302.
[0062]
First, a base insulating film 301 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed over the substrate 300 as a blocking layer. Here, a two-layer structure (a 50-nm-thick silicon oxynitride film and a 100-nm-thick silicon oxynitride film) is used as the base insulating film 301; however, a single-layer film or a structure in which two or more layers are stacked may be used. However, when it is not necessary to provide a blocking layer, the base insulating film is not necessarily formed.
[0063]
Next, a first amorphous semiconductor film 302 having an amorphous structure is formed over the base insulating film by LPCVD. Note that the amorphous semiconductor film having a low oxygen concentration in the film formed here has an oxygen concentration of 1 × 10 5 in the film. ¹⁸ atoms / cm ^Three It is an amorphous semiconductor film that is less than. The material of the amorphous semiconductor film can be formed of silicon (silicon) or a silicon germanium (SiGe) alloy.
[0064]
Next, an insulating film is formed so as to cover part of the amorphous semiconductor film having a low oxygen concentration in the film. Note that as the insulating film formed here, an insulating film containing silicon such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film can be used. Further, after the film formation, patterning by photolithography is performed, and etching is performed, so that an island-shaped insulating film 303 covering a part of the amorphous semiconductor film having a low oxygen concentration in the film is formed.
[0065]
In this state, the first amorphous material having a low oxygen concentration in the film is obtained by exposing a gas mainly composed of one or more kinds selected from hydrogen, nitrogen, ammonia, and a rare gas element to a plasma atmosphere. The natural oxide film formed on the surface of the crystalline semiconductor film 302 may be removed.
[0066]
Next, an amorphous semiconductor film (second amorphous semiconductor film) 304 having a high oxygen concentration in the film is changed to a part of the first amorphous semiconductor film 302 having a low oxygen concentration in the film by plasma CVD, and A metal element 305 which promotes crystallization is added over the second amorphous semiconductor film 304 which is formed over the insulating film 303 and has a high oxygen concentration in the film. In this embodiment, the metal element 305 is added by applying a nickel acetate salt solution containing 10 ppm of nickel by weight with a spinner (FIG. 4B).
[0067]
Next, these are crystallized by heat treatment to form a crystalline semiconductor film having a crystal structure. For this heat treatment, heat treatment in an electric furnace or irradiation with strong light may be used. When the heat treatment is performed in an electric furnace, the treatment may be performed at 500 ° C. to 650 ° C. for 4 to 24 hours. Note that in this embodiment, an amorphous semiconductor film (a first amorphous semiconductor film 302 and a second amorphous semiconductor film 305) is formed by performing heat treatment for crystallization (550 ° C., 4 hours). Is crystallized.
[0068]
Note that as a method for adding the metal element 305 that promotes crystallization, a method of applying a solution containing the metal element may be used, or a method of forming a thin film by a sputtering method or a CVD method may be used. That is, by crystallization, the first amorphous semiconductor film 302 becomes the first crystalline semiconductor film 307, and the second amorphous semiconductor film 305 becomes the second crystalline semiconductor film 308 (FIG. 4 (C)).
[0069]
Next, in order to remove the metal element present in the first crystalline semiconductor film 307, an impurity is added and gettering is performed. Specifically, phosphorus or a rare gas (typically argon) is added over the second crystalline semiconductor film 308. Note that at this time, phosphorus or a rare gas (typically argon) is also contained in the region r (309) which is a part of the first crystalline semiconductor film 307 by using the insulating film 303 as a mask. ¹⁶ ~ 5x10 ¹⁷ atoms / cm ^Three It is added at a concentration of about. Here, the metal element (typically Ni) 305 existing in the first crystalline semiconductor film 307 is moved to the region r (309) by performing heat treatment. The existing metal element can be removed.
[0070]
Next, the portion of the first crystalline semiconductor film 307 covered with the insulating film 303 is left, and the crystallized crystalline semiconductor film is removed by etching. Further, by removing the insulating film 303, a crystalline semiconductor film containing no metal element can be obtained (FIG. 4D).
[0071]
Furthermore, in this embodiment, after removing the oxide film present on the surface of the obtained crystalline semiconductor film with dilute hydrofluoric acid or the like, the laser light for increasing the crystallization rate and repairing the defects left in the crystal grains Irradiation with (XeCl: wavelength 308 nm) is performed in air or in an oxygen atmosphere. The laser used here is preferably a continuous wave or pulsed solid laser, a gas laser, or a metal laser. The solid-state laser may be a continuous wave or pulsed YAG laser, YVO _Four Laser, YLF laser, YAlO _Three There are lasers, glass lasers, ruby lasers, alexandride lasers, Ti: sapphire lasers, etc., and the gas lasers include continuous wave or pulsed excimer lasers, Ar lasers, Kr lasers, CO ₂ Examples of the metal laser include a continuous wave or pulsed helium cadmium laser, a copper vapor laser, and a gold vapor laser. Further, the laser beam may be converted into a second harmonic and a third harmonic using a nonlinear optical element. When a pulsed laser is used, pulse laser light having a repetition frequency of about 10 Hz to 10 KHz is used, and the laser light is 100 to 1500 mJ / cm in an optical system. ² And the surface of the silicon film may be scanned by irradiating with an overlap rate of 50 to 98%. Here, a repetition frequency of 30 Hz and an energy density of 393 mJ / cm ² Irradiate laser light in the atmosphere.
[0072]
When a continuous wave laser is used, the energy density is 0.01 to 100 MW / cm. ² Degree (preferably 0.1 to 10 MW / cm ² )is required. Then, irradiation may be performed by moving the stage relative to the laser light at a speed of about 0.5 to 2000 cm / s.
[0073]
Thus, the third crystalline semiconductor film 310 with a high crystallization rate can be obtained.
[0074]
Next, a semiconductor layer 311 is formed by patterning the third crystalline semiconductor film 310.
[0075]
Next, after cleaning the surface of the semiconductor layer 311 with an etchant containing hydrofluoric acid, an insulating film containing silicon as a main component and serving as the gate insulating film 312 is formed. The surface cleaning and the formation of the gate insulating film 312 are desirably performed continuously without being exposed to the atmosphere.
[0076]
Next, after cleaning the surface of the gate insulating film 312, a gate electrode 313 is formed, and an impurity element imparting n-type conductivity (P, As, or the like), here phosphorus, is added as appropriate to the source region 314 and the drain. Region 315 is formed. After the addition, heat treatment, intense light irradiation, or laser light irradiation is performed to activate the impurity element. Simultaneously with activation, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered. In particular, in an atmosphere of room temperature to 300 ° C., it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface. A YAG laser is a preferred activation means because it requires less maintenance.
[0077]
Further, when heat treatment is used as an activation means, gettering can be performed simultaneously with activation. The gettering here is gettering by phosphorus added to the source region or the drain region. In addition, it is desirable to remove or reduce the metal element that promotes crystal growth added before crystallization from the crystalline semiconductor film by performing gettering after crystallization.
[0078]
In the subsequent steps, an interlayer insulating film 316 is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, and a source electrode 317 and a drain electrode 318 are formed to complete the TFT (FIG. 4). (F)).
[0079]
The TFT obtained in this manner has high uniformity and is formed on the substrate because the channel formation region 317 is formed using the third crystalline semiconductor film 310 having a large grain size and a high orientation ratio. The variation between the TFTs thus formed can be reduced.
[0080]
(Example 3)
Here, a method for manufacturing a liquid crystal display device using an active matrix substrate having a pixel portion will be described with reference to FIGS.
[0081]
An active matrix liquid crystal display device using TFT as a switching element has a structure in which a substrate (active matrix substrate) in which pixel electrodes are arranged in a matrix and an opposite substrate on which a counter electrode is formed are opposed to each other with a liquid crystal layer interposed therebetween. It has become. The distance between the two substrates is controlled to a predetermined interval via a spacer or the like, and a liquid crystal layer is sealed by using a sealing material on the outer periphery of the pixel portion.
[0082]
An example of manufacturing an active matrix substrate is shown below.
[0083]
First, a conductive film is formed over the substrate 401 having an insulating surface, and the scanning lines 402 are formed by patterning. The scanning line 402 also functions as a light shielding layer that protects an active layer formed later from light. Here, a quartz substrate is used as the substrate 401, and a stacked structure of a polysilicon film (film thickness: 75 nm) and a tungsten silicide (W-Si) film (film thickness: 150 nm) is used as the scanning line 402. The polysilicon film protects the contamination from the tungsten silicide to the substrate.
[0084]
Next, insulating films 403a and 403b covering the scan line 402 are formed to a thickness of 100 to 1000 nm (typically 300 to 600 nm) (FIG. 5A). Here, a silicon oxide film having a thickness of 100 nm using a plasma CVD method and a silicon oxide film having a thickness of 480 nm using a low pressure CVD method (LPCVD method) are stacked.
[0085]
Alternatively, after the insulating film 403b is formed, the surface of the insulating film may be planarized by a chemical and mechanical polishing process (typically, CMP technique). For example, the maximum height (Rmax) of the insulating film surface is set to 0.5 μm or less, preferably 0.3 μm or less.
[0086]
Next, an amorphous semiconductor film is formed with a thickness of 10 to 100 nm. Note that the amorphous semiconductor film (amorphous silicon film) formed here is formed by the LPCVD method, and is referred to as a first amorphous semiconductor film in this embodiment. The first amorphous semiconductor film 404 is formed with a thickness of 53 nm. Note that the semiconductor film can be formed using silicon, a silicon germanium (SiGe) alloy, or the like.
[0087]
Further, an insulating film 405 is formed so as to cover the first amorphous semiconductor film 404. In this embodiment, a silicon oxide film with a thickness of 50 nm is formed and patterned to form an insulating film 405 having a desired shape (FIG. 5B). Note that FIG. 5B2 illustrates a top view of the pixel after the insulating film 405 is formed. In FIG. 5B2, a cross-sectional view taken along dotted line AA ′ corresponds to FIG.
[0088]
Next, a second amorphous semiconductor film 406 is formed so as to cover the exposed portion of the first amorphous semiconductor film 404 and the insulating film 405. Then, the first amorphous semiconductor film 404 and the second amorphous semiconductor film 406 are crystallized. In this embodiment, a metal element for promoting crystallization is added to the entire surface of the amorphous silicon film, and the amorphous semiconductor film is crystallized by a thermal crystallization method.
[0089]
The metal element includes a metal element such as Ni, Pd, or lead, and a plasma treatment method, a vapor deposition method, an ion implantation method, a sputtering method, a solution coating method, or the like can be used as an addition method. In the example, a nickel acetate aqueous solution (weight conversion concentration 3 ppm, volume 10 ml) is applied to the surface of the second amorphous semiconductor film 406 by spin coating.
[0090]
Then, heat treatment is performed to crystallize the amorphous semiconductor film. This heat treatment is performed by a thermal annealing method using a furnace annealing furnace. The thermal annealing may be performed at 400 to 700 ° C., typically 500 to 600 ° C. for about 4 to 24 hours in a nitrogen atmosphere having an oxygen concentration of 1 ppm or less, preferably 0.1 ppm or less. Further, as a heat treatment other than the thermal annealing method, a rapid thermal annealing method (RTA method), a GRTA method, or the like may be used. In this embodiment, heat treatment (570 ° C., 24 hours) is performed to form a crystalline silicon film.
[0091]
Note that in this example, a metal element that promotes crystallization is added to the second amorphous semiconductor film 406 and crystallization is performed by heating. However, the second amorphous semiconductor film 406 and the second amorphous semiconductor film 406 Since the first amorphous semiconductor film 404 is formed in contact with the region a (407) in FIG. 5C, the first amorphous semiconductor film 404 is also crystallized at the time of crystallization. Therefore, the first amorphous semiconductor film 404 becomes the first crystalline semiconductor film 408, and the second amorphous semiconductor film 406 becomes the second crystalline semiconductor film 410.
[0092]
Thereafter, gettering of a metal element (Ni) is performed from the first crystalline semiconductor film 408 which becomes an active layer of the TFT. Therefore, as shown in FIG. 6A, an impurity such as phosphorus (P) or argon (Ar) is added over the second crystalline semiconductor film 410. At this time, since the previously formed insulating film 405 serves as a mask, the region b (409) which is part of the first crystalline semiconductor film 408 and is not covered with the insulating film 405 is also phosphorus ( P) or argon (Ar) can be added to form gettering sites. By performing heat treatment (at 600 ° C. for 12 hours in a nitrogen atmosphere) after adding the impurities, the metal element (Ni) present in the crystalline semiconductor film can be moved to the gettering site.
[0093]
Next, the region b (409) and the second crystalline semiconductor film 410 which are part of the first crystalline semiconductor film 408 to which the impurity is added are removed by etching (FIG. 6B). Further, by removing the insulating film 405, the first crystalline semiconductor film 411 in which the metal element that promotes crystallization existing in the film is reduced more than immediately after crystallization can be obtained.
[0094]
In this embodiment, an insulating film is newly formed on the first crystalline semiconductor film 411, and the upper portion of the first crystalline semiconductor film 411 is thermally oxidized by performing heat treatment. By performing such heat treatment, intragranular defects in the crystal can be reduced, so that the crystallinity of the first crystalline semiconductor film 411 can be improved. Specifically, after forming a 20 nm silicon oxide film with a low pressure CVD apparatus, heat treatment is performed in a furnace annealing furnace. By this treatment, the upper part of the first crystalline semiconductor film 411 is oxidized.
[0095]
Then, the oxidized portion of the silicon oxide film and the first crystalline semiconductor film 411 is etched and patterned, and unnecessary portions of the first crystalline semiconductor film 411 are removed, thereby improving the crystallinity of the semiconductor. The layer 412 is obtained (FIG. 6C1). Note that FIG. 6C2 illustrates a top view of the pixel after the semiconductor layer 412 is formed. In FIG. 6C2, a cross-sectional view taken along dotted line AA ′ corresponds to FIG.
[0096]
Next, in order to form a storage capacitor, a mask 413 is formed, and part of the semiconductor layer 412 (a region to be a storage capacitor) 414 is doped with phosphorus (FIG. 7A).
[0097]
Next, after the mask 413 is removed and an insulating film covering the semiconductor layer 412 is formed, the mask 415 is formed, and the insulating film over the region 414 serving as a storage capacitor is removed (FIG. 7B).
[0098]
Next, the mask 415 is removed, and an insulating film (gate insulating film) 416a is newly formed. Here, by forming a new insulating film, the final thickness of the gate insulating film became 80 nm. Note that an insulating film 416b thinner than other regions is formed over the region to be a storage capacitor (FIG. 7C1). A top view of the pixel here is shown in FIG. In FIG. 7C2, a cross-sectional view taken along dotted line BB ′ corresponds to FIG. In addition, a region indicated by a chain line in FIG. 7 is a portion where a thin insulating film 416b is formed.
[0099]
Next, a channel doping process for adding a p-type or n-type impurity element at a low concentration to a region to be a channel region of the TFT is performed entirely or selectively. This channel doping process is a process for controlling the TFT threshold voltage. Here, diborane (B ₂ H ₆ Boron was added by ion doping with plasma excitation without mass separation. Of course, an ion implantation method that performs mass separation may be used.
[0100]
Next, a mask 417 is formed over the insulating film 416a and the insulating films 403a and 403b, and a contact hole reaching the scanning line 402 is formed (FIG. 8A). Then, after the contact hole is formed, the mask is removed.
[0101]
Next, a conductive film is formed and patterned to form the gate electrode 418 and the capacitor wiring 419. Here, a stacked structure of a phosphorus-doped silicon film (thickness 150 nm) and tungsten silicide (thickness 150 nm) was used. Note that the storage capacitor includes a capacitor wiring 419 and a part of the semiconductor layer 412 using the insulating film 416b as a dielectric.
[0102]
Next, phosphorus is added at a low concentration in a self-aligning manner using the gate electrode 418 and the capacitor wiring 419 as a mask (FIG. 8C1). A top view of the pixel here is shown in FIG. In FIG. 8C2, a cross-sectional view taken along dotted line CC ′ corresponds to FIG. The concentration of phosphorus in this low concentration region is 1 × 10 ¹⁶ ~ 5x10 ¹⁸ atoms / cm ^Three , Typically 3 × 10 ¹⁷ ~ 3x10 ¹⁸ atoms / cm ^Three Adjust so that
[0103]
Further, a mask 420 is formed, phosphorus is added at a high concentration, and a high concentration impurity region 421 to be a source region or a drain region is formed. (FIG. 9A) The phosphorus concentration in this high-concentration impurity region is 1 × 10 ²⁰ ~ 1x10 ^{twenty one} atoms / cm ^Three (Typically 2 × 10 ²⁰ ~ 5x10 ²⁰ atoms / cm ^Three ). Note that in the semiconductor layer 412, a region overlapping with the gate electrode 418 serves as a channel formation region 422, and a region covered with the mask 420 serves as a low concentration impurity region 423 and functions as an LDD region. Then, after the impurity element is added, the mask 420 is removed.
[0104]
Although not shown here, in order to form a p-channel TFT used for a driver circuit formed over the same substrate as the pixel, a region that becomes an n-channel TFT is covered with a mask, and boron is added to form a source region. Alternatively, a drain region is formed.
[0105]
Next, after the mask 420 is removed, a passivation film 424 that covers the gate electrode 418 and the capacitor wiring 419 is formed. The passivation film 424 prevents oxidation of the gate electrode 418 and functions as an etching stopper in a later planarization process. Here, a silicon oxide film was formed with a thickness of 70 nm. Next, a heat treatment process for activating the n-type or p-type impurity element added to the semiconductor layer 412 at each concentration is performed. Here, heat treatment is performed at 950 ° C. for 30 minutes.
[0106]
Then, an interlayer insulating film 425 made of an organic resin material or a silicon material is formed. Here, a silicon oxynitride film having a thickness of 1 μm was used, and planarization was performed by performing etch back. Next, after a contact hole reaching the semiconductor layer 412 is formed, an electrode 426 and a source wiring 427 are formed. In this embodiment, the electrode 426 and the source wiring 427 are each a laminated film having a three-layer structure in which a Ti film is 100 nm, an aluminum film containing Ti is 300 nm, and a Ti film 150 nm is continuously formed by sputtering (FIG. 9B1). )). Note that a cross-sectional view taken along dotted line DD ′ in FIG. 9B2 corresponds to FIG. 9B1.
[0107]
Then, after performing a hydrogenation treatment, an interlayer insulating film 428 formed of a stack of a silicon oxynitride film (film thickness 500 nm), BCB (benzocyclobutene) (film thickness 1 μm), and (film thickness 300 nm) is formed ( FIG. 10 (A1)). Next, a light-shielding conductive film (with a thickness of 100 nm) is formed over the interlayer insulating film 428 and patterned to form the light-shielding layer 429. Further, an interlayer insulating film 430 made of a silicon oxynitride film with a thickness of 150 nm is formed.
[0108]
Next, a contact hole reaching the electrode 426 is formed. Then, after forming a 100 nm transparent conductive film (here, indium tin oxide (ITO) film), the pixel electrodes 431 and 432 are formed by patterning. In FIG. 10A2, a cross-sectional view taken along dotted line EE ′ corresponds to FIG.
[0109]
Thus, in the pixel portion, a pixel TFT composed of an n-channel TFT is formed while ensuring an area (aperture ratio 76.5%) of a display region (pixel size 26 μm × 26 μm), and a sufficient storage capacitor (51.5 fF) is formed. ) Can be obtained.
[0110]
Needless to say, the present embodiment is an example and is not limited to the steps of the present embodiment. For example, as each conductive film, an element selected from tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), chromium (Cr), silicon (Si), or an alloy in which the elements are combined A film (typically, a Mo—W alloy or a Mo—Ta alloy) can be used. As each insulating film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or an organic resin (polyimide, acrylic, polyamide, polyimide amide, BCB, or the like) film can be used.
[0111]
The characteristics of the TFT thus obtained showed good electrical characteristic values. FIG. 11 shows characteristics relating to the field effect mobility of the p-channel TFT, and FIG. 12 shows characteristics relating to the field effect mobility of the n-channel TFT. 11 and 12, the horizontal axis of the graph represents the mobility, and the vertical axis represents the cumulative frequency distribution. In any case, a TFT using a crystalline semiconductor film obtained by a conventional crystallization method (conventional method) as an active layer (length of channel formation region (L) / width of channel formation region (W)) = 50 μm / 50 μm) and a TFT (L / W = 50 μm / 50 μm) using a crystalline semiconductor film obtained by the crystallization method of the present invention (the present invention) as an active layer.
[0112]
In both cases of FIG. 11 and FIG. 12, the distribution of the graph relating to the TFT formed using the present invention has a larger slope than the TFT formed using the conventional method. Distributed at high mobility. Therefore, the TFT formed using the present invention has less variation and mobility than the TFT formed using the conventional method in both cases of the p-channel TFT and the n-channel TFT. It was confirmed to have excellent properties of high.
[0113]
(Example 4)
In this example, a process of manufacturing an active matrix liquid crystal display device from the active matrix substrate of Example 3 will be described below. FIG. 13 is used for the description.
[0114]
First, after obtaining the active matrix substrate in the state of FIG. 13 according to Example 3, an alignment film is formed on the active matrix substrate of FIG. 13 and a rubbing process is performed. In this embodiment, before the alignment film is formed, a columnar spacer for maintaining the substrate interval is formed at a desired position by patterning an organic resin film such as an acrylic resin film. Further, instead of the columnar spacers, spherical spacers may be scattered over the entire surface of the substrate.
[0115]
Next, a counter substrate is prepared. The counter substrate is provided with a color filter in which a colored layer and a light shielding layer are arranged corresponding to each pixel. Further, a light shielding layer is also provided in the drive circuit portion. Then, a planarizing film is provided to cover the color filter and the light shielding layer. Next, a counter electrode made of a transparent conductive film is formed on the planarizing film in the pixel portion, an alignment film is formed on the entire surface of the counter substrate, and a rubbing process is performed.
[0116]
Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the counter substrate are bonded together with a sealant. A filler is mixed in the sealing material, and two substrates are bonded to each other with a uniform interval by the filler and the columnar spacer. Thereafter, a liquid crystal material is injected between both substrates and completely sealed with a sealant (not shown). A known liquid crystal material may be used as the liquid crystal material. In this way, an active matrix liquid crystal display device is completed. If necessary, the active matrix substrate or the counter substrate is divided into a desired shape. Furthermore, after appropriately providing a polarizing plate or the like using a known technique, an FPC is attached using a known technique.
[0117]
The structure of the liquid crystal module thus obtained will be described with reference to the top view of FIG.
[0118]
A pixel portion 1304 is arranged at the center of the active matrix substrate 1301. A source signal line driver circuit 1302 for driving the source signal line is disposed above the pixel portion 1304. In addition, gate signal line driving circuits 1303 for driving the gate signal lines are arranged on the left and right sides of the pixel portion 1304. In the example shown in this embodiment, the gate signal line driver circuit 1303 is arranged symmetrically with respect to the pixel portion. However, this may be arranged only on one side, and the designer may consider the substrate size of the liquid crystal module. May be appropriately selected. However, considering the operation reliability and driving efficiency of the circuit, the symmetrical arrangement shown in FIG. 13 is desirable.
[0119]
Input of signals to each drive circuit is performed from a flexible printed circuit (FPC) 1305. The FPC 1305 opens a contact hole in the interlayer insulating film and the resin film so as to reach the wiring arranged up to a predetermined place on the substrate 1301, and after forming a connection electrode (not shown), an anisotropic conductive film or the like It is crimped through. In this embodiment, the connection electrode is formed using ITO.
[0120]
A sealant 1307 is applied to the periphery of the driving circuit and the pixel portion along the outer periphery of the substrate, and a predetermined gap (a gap between the substrate 1301 and the counter substrate 1306 is formed by a spacer (not shown) formed on the active matrix substrate in advance. The counter substrate 1306 is attached in a state where the interval is maintained. After that, a liquid crystal element is injected from a portion where the sealant 1307 is not applied and sealed with the sealant 1308. The liquid crystal module is completed through the above steps.
[0121]
Although an example in which all the drive circuits are formed on the substrate is shown here, several ICs may be used as part of the drive circuit.
[0122]
(Example 5)
In this embodiment, a TFT formed by using a crystalline semiconductor film manufactured by the manufacturing method of the present invention as an active layer is used as a pixel portion (switching TFT, current control TFT) and a driver circuit portion (source side). An active matrix light-emitting device included in a driver circuit and a gate-side driver circuit is described with reference to FIGS.
[0123]
14A is a top view illustrating the light-emitting device, and FIG. 14B is a cross-sectional view taken along line AA ′ in FIG. 14A. Reference numeral 1401 indicated by a dotted line denotes a source side driver circuit, 1402 denotes a pixel portion, and 1403 denotes a gate side driver circuit. Further, 1404 is a sealing substrate, 1405 is a sealing agent, and the inside surrounded by the sealing agent 1405 is a space 1407.
[0124]
Reference numeral 1408 denotes a wiring for transmitting signals input to the source side driver circuit 1401 and the gate side driver circuit 1403, and receives a video signal and a clock signal from an FPC (flexible printed circuit) 1409 as an external input terminal. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC.
[0125]
Next, a cross-sectional structure is described with reference to FIG. A driver circuit and a pixel portion are formed over the substrate 1410. Here, a source side driver circuit 1401 and a pixel portion 1402 are shown as driver circuits.
[0126]
Note that the source side driver circuit 1401 is formed with a CMOS circuit in which an n-channel TFT 1413 and a p-channel TFT 1414 are combined. The TFT forming the driving circuit may be formed by a known CMOS circuit, PMOS circuit or NMOS circuit. In this embodiment mode, a driver integrated type in which a driver circuit is formed over a substrate is shown; however, this is not always necessary, and the driver circuit may be formed outside the substrate.
[0127]
In addition, the pixel portion 1402 includes a switching TFT 1411 to which a video signal from the source side driver circuit is input, a current control TFT 1412 connected to the switching TFT 1411 and having a function of controlling the luminance of the light emitting element, and a current control. The pixel is formed by a plurality of pixels including a first electrode (anode) 1413 electrically connected to the drain of the TFT 1411 for use.
[0128]
An insulating layer 1414 is formed on both ends of the first electrode (anode) 1413, and an organic compound layer 1415 is formed on the first electrode (anode) 1413. Further, a second electrode (cathode) 1416 is formed on the organic compound layer 1415. Thus, a light-emitting element 1418 including the first electrode (anode) 1413, the organic compound layer 1415, and the second electrode (cathode) 1416 is formed.
[0129]
Further, an auxiliary wiring 1417 is formed over the second electrode (cathode) 1416. The auxiliary wiring 1417 is electrically connected to the connection wiring 1417 and is electrically connected to an external power supply via the FPC 1409.
[0130]
In addition, in order to seal the light-emitting element 1418 formed over the substrate 1410, a sealing substrate 1404 is attached with a sealant 1405. Note that a spacer made of a resin film may be provided in order to secure a space between the sealing substrate 1404 and the light-emitting element 1418. A space 1407 inside the sealing agent 1405 is filled with an inert gas such as nitrogen. Note that an epoxy resin is preferably used as the sealant 1405. In addition, the sealant 1405 is desirably a material that does not transmit moisture and oxygen as much as possible. Further, the space 1407 may contain a substance having an effect of absorbing oxygen and water.
[0131]
In this embodiment mode, a plastic substrate made of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like is used as a material constituting the sealing substrate 1404 in addition to a glass substrate or a quartz substrate. Can be used. Further, after the sealing substrate 1404 is bonded using the sealing agent 1405, the sealing substrate 1404 can be further sealed with a sealing agent so as to cover the side surface (exposed surface).
[0132]
By encapsulating the light emitting element in the space 1407 as described above, the light emitting element can be completely blocked from the outside, and a substance that promotes deterioration of the organic compound layer such as moisture and oxygen can be prevented from entering from the outside. Can do. Therefore, a highly reliable light-emitting device can be obtained.
[0133]
Note that the structure of this embodiment mode can be implemented using the TFT manufactured in Example 1 or Example 2.
[0134]
(Example 6)
The TFT formed using the present invention can be used for various modules (active matrix liquid crystal module, active matrix light emitting module, active matrix EC module). That is, an electric appliance can be completed by incorporating them into the display portion.
[0135]
Such electric appliances include video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound playback devices (car audio, audio components, etc.), notebook-type personal computers, game machines, portable information terminals (mobiles) Computer, mobile phone, portable game machine, electronic book, or the like), image reproducing device provided with a recording medium (specifically, a display device capable of reproducing a recording medium such as a digital video disc (DVD) and displaying the image) And the like). In particular, a portable information terminal that frequently sees a screen from an oblique direction emphasizes the wide viewing angle, and thus a light emitting device having a light emitting element is preferably used. Specific examples of these electric appliances are shown in FIG.
[0136]
FIG. 15A illustrates a display device, which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. It is manufactured by using a module using a TFT manufactured according to the present invention for the display portion 2003. The display devices include all information display devices for personal computers, for receiving TV broadcasts, for displaying advertisements, and the like.
[0137]
FIG. 15B illustrates a digital still camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. It is manufactured by using a module using a TFT manufactured according to the present invention for the display portion 2102.
[0138]
FIG. 15C illustrates a laptop personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. A module using a TFT manufactured according to the present invention is used for the display portion 2203.
[0139]
FIG. 15D illustrates a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. It is manufactured by using a module using a TFT manufactured according to the present invention for the display portion 2302.
[0140]
FIG. 15E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. The display portion A 2403 mainly displays image information and the display portion B 2404 mainly displays character information. The display portion A 2403 is manufactured by using a module using a TFT manufactured according to the present invention for the display portions A, B 2403 and 2404. Note that an image reproducing device provided with a recording medium includes a home game machine and the like.
[0141]
FIG. 15F illustrates a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, and an arm portion 2503. It is manufactured by using a module using a TFT manufactured according to the present invention for the display portion 2502.
[0142]
FIG. 15G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control reception portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, operation keys 2609, and an eyepiece. Part 2610 and the like. A module using a TFT manufactured according to the present invention is used for the display portion 2602.
[0143]
Here, FIG. 15H shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. It is manufactured by using a module using a TFT manufactured according to the present invention for the display portion 2703. Note that the display portion 2703 can reduce power consumption of the mobile phone by displaying white characters on a black background.
[0144]
If the emission luminance of the organic material is increased in the future, the light including the output image information can be enlarged and projected by a lens or the like and used for a front type or rear type projector.
[0145]
As described above, the application range of a module using a TFT manufactured using the manufacturing method of the present invention is extremely wide, and electric appliances in various fields can be manufactured. Moreover, the electric appliance in a present Example can be implemented combining any of Example 1- Example 5 freely.
[0146]
【The invention's effect】
In crystallization of an amorphous semiconductor film of the present invention, an amorphous semiconductor film having a high oxygen concentration in the film and an amorphous semiconductor film having a low oxygen concentration in the film are formed in contact with each other, and an amorphous semiconductor having a high oxygen concentration in the film is formed. Crystallization is performed by adding a metal element for promoting crystallization to the crystalline semiconductor film, taking advantage of the fact that crystal nuclei are likely to be generated, and further, non-high concentration of oxygen in the film. By crystallizing an amorphous semiconductor film having a low oxygen concentration in the film formed in contact with the crystalline semiconductor film, the amount of metal element added can be reduced as compared with the conventional crystallization method. Further, a crystalline semiconductor film made of an amorphous semiconductor film having a low oxygen concentration in the film can be obtained in spite of reducing the amount of metal element added, so that a film having a large crystal grain size can be obtained. Further, this crystalline semiconductor film was a crystalline semiconductor film having a very high crystal orientation rate.
[0147]
Furthermore, by forming a thin film transistor using such a crystalline semiconductor film as an active layer, it is possible to form a thin film transistor having excellent electrical characteristics and a semiconductor device having a circuit composed of these thin film transistors. it can.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a crystallization process of the present invention.
FIG. 2 is an observation photograph of the crystallized crystalline silicon film surface.
3A and 3B illustrate a manufacturing process of a TFT.
4A and 4B illustrate a manufacturing process of a TFT.
FIGS. 5A and 5B illustrate a manufacturing process of an active matrix liquid crystal display device. FIGS.
6A and 6B illustrate a manufacturing process of an active matrix liquid crystal display device.
7A to 7C illustrate a manufacturing process of an active matrix liquid crystal display device.
FIGS. 8A and 8B illustrate a manufacturing process of an active matrix liquid crystal display device. FIGS.
9A and 9B illustrate a manufacturing process of an active matrix liquid crystal display device.
10A and 10B illustrate a manufacturing process of an active matrix liquid crystal display device.
FIG. 11 is a graph showing field effect mobility of a p-channel TFT (L / W = 50/50).
FIG. 12 is a graph showing field effect mobility of an n-channel TFT (L / W = 50/50).
FIG. 13 illustrates an appearance of a liquid crystal display device.
FIG. 14 illustrates an appearance of a light-emitting device.
FIG. 15 is a diagram showing an example of an electric appliance.
FIG. 16 is a diagram showing an inverted pole figure measured by an EBSP method.
[Explanation of symbols]
100 substrates
101 First amorphous semiconductor film
102, 103 Insulating film
104 Second amorphous semiconductor film
105 Metal elements
107 first crystalline semiconductor film
108 Second crystalline semiconductor film
110 Third crystalline semiconductor film

Claims (5)

Forming a first amorphous silicon film having an oxygen concentration of less than 1 × 10 ¹⁸ atoms / cm ³ on the insulating surface;
Forming an insulating film on the first amorphous silicon film;
After exposing a part of the first amorphous silicon film by removing a part of the insulating film, on the insulating film and the exposed first amorphous silicon film , oxygen concentration to form a second amorphous silicon film is ^{1 × 10 18 ~1 × 10 20} atoms / cm 3,
By adding nickel to the second amorphous silicon film and heating, crystal nuclei are generated in the second amorphous silicon film,
By growing the crystal nucleus, the first amorphous silicon film and the second amorphous silicon film are crystallized to form a first crystalline silicon film and a second crystalline silicon film, respectively. And
By adding an impurity to the second crystalline silicon film, the impurity is added to a part of the first crystalline silicon film using the insulating film as a mask,
The nickel contained in the first crystalline silicon film is moved by heating to the region to which the impurities are added,
A method for manufacturing a crystalline silicon film, wherein the region to which the impurity is added is removed. Forming a first amorphous silicon film having an oxygen concentration of less than 1 × 10 ¹⁸ atoms / cm ³ on the insulating surface;
Forming an insulating film on the first amorphous silicon film;
After exposing a part of the first amorphous silicon film by removing a part of the insulating film, the first amorphous silicon film is selected from hydrogen, nitrogen, ammonia and a rare gas element. Exposing one or more kinds of gases as a main component to a plasma atmosphere,
A second amorphous silicon film having an oxygen concentration of 1 × 10 ¹⁸ to 1 × 10 ²⁰ atoms / cm ³ is formed on the insulating film and the exposed first amorphous silicon film. ,
By adding nickel to the second amorphous silicon film and heating, crystal nuclei are generated in the second amorphous silicon film,
By growing the crystal nucleus, the first amorphous silicon film and the second amorphous silicon film are crystallized to form a first crystalline silicon film and a second crystalline silicon film, respectively. And
By adding an impurity to the second crystalline silicon film, the impurity is added to a part of the first crystalline silicon film using the insulating film as a mask,
The nickel contained in the first crystalline silicon film is moved by heating to the region to which the impurities are added,
A method for manufacturing a crystalline silicon film, wherein the region to which the impurity is added is removed. In claim 1 or claim 2,
Forming the first amorphous silicon film by a low pressure CVD method;
A method for producing a crystalline silicon film, wherein the second amorphous silicon film is formed by a plasma CVD method. In any one of Claims 1 to 3 ,
The first crystalline silicon film in which the impurities have been removed regions are added, the crystalline silicon, wherein the concentration of the nickel contained in the film is 2 × 10 18 ^atoms / cm ³ or less A method for producing a film. In any one of Claims 1 thru | or 4 ,
The first crystalline silicon film in which the impurities have been removed regions are added, surface angle of the silicon film that is the {111} lattice plane detected by the reflected electron diffraction pattern method is within 5 ° proportions The manufacturing method of the crystalline silicon film | membrane characterized by the above-mentioned.

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