JP4884735B2 - Method for manufacturing semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) and a manufacturing method thereof. For example, the present invention relates to an electronic apparatus in which an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element is mounted as a component.

  Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

  In recent years, a technique for forming a thin film transistor (TFT) using a semiconductor thin film (having a thickness of about several to several hundred nm) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and development of switching devices for image display devices is urgently required.

  A TFT using a semiconductor film having a crystalline structure (typically polysilicon) as a semiconductor layer has higher field effect mobility than a semiconductor film having an amorphous structure (typically amorphous silicon). , Has been actively used.

  However, TFTs using polysilicon as the semiconductor layer have many advantages over TFTs using amorphous silicon as the semiconductor layer. However, impurities and defects present in the channel formation region cause the electrical characteristics of the TFT. In particular, there is a problem that the threshold characteristic is greatly affected.

  For example, when the threshold value of the TFT is on the minus side from 0 V, the n-channel TFT is normally on, so that a normal switching operation is difficult. In view of this problem, there is known a threshold control method in which boron ions or the like are added to the channel formation region using an ion doping apparatus or an ion implantation apparatus so that the TFT threshold approaches 0V. ing.

  The ion implantation apparatus is an apparatus that selectively implants only the target ion species by accelerating the electric field of impurity ions and further performing mass separation, and is characterized by high accuracy. However, the ion implantation apparatus has a low throughput and is a very expensive manufacturing apparatus. In particular, when processing a large substrate, an ion implantation apparatus is disadvantageous. On the other hand, an ion doping apparatus can add impurity ions to a semiconductor thin film having a large area at a time and is suitable for mass production. In this ion doping apparatus, a source gas is flowed into a chamber, the source gas is turned into plasma by a known method, and impurity ions contained therein are ionized and added to a semiconductor film. Since mass separation is not performed unlike an ion implantation apparatus, ions other than the target ion species are added, but the throughput is excellent.

Further, the present applicant has disclosed a technique in which a semiconductor film is doped with a compound containing a halogen element (CF ₄ , NF ₃ , SF ₆ , BF ₃ , SiF _4, etc.) and the semiconductor film is used as a gettering site. Proposed in
JP2004-22900

  In the above-described method for controlling the threshold value, it is necessary that the amount of boron ions added to the portion to be a channel formation region be a very small amount. However, when an ion doping apparatus is used, it is difficult to control the threshold value by using diborane as a doping gas and adding a minute amount of boron ions accurately and uniformly.

In the present invention, after obtaining a semiconductor film having a crystal structure, a material layer is formed thereon, and boron ions are added using BF ₃ (boron trifluoride gas) as a doping gas by using an ion doping apparatus. This is characterized in that the threshold value is controlled by adding a trace amount of boron ions accurately and uniformly to the semiconductor film having a crystal structure. When boron and fluorine are added using BF ₃ as a doping gas using an ion doping apparatus, the depth at which the fluorine element reaches the maximum concentration differs from the depth at which the boron element reaches the maximum concentration.

FIG. 1 shows the result of adding B ⁺ , BF ⁺ and BF ₂ ⁺ to a semiconductor silicon wafer by using an ion implantation apparatus and adjusting the acceleration voltage so that the respective concentration profiles approach each other. FIG. 1 shows a concentration profile of B ⁺ doped with an acceleration voltage of 30 keV, a concentration profile of BF ⁺ doped with an acceleration voltage of 70 keV, and a BF doped with an acceleration voltage of 105 keV. It shows the ₂ ⁺ concentration profile. If adding boron and fluorine BF ₃ as a doping gas using an ion doping apparatus, since the acceleration voltage is common, for example, the acceleration voltage is 30 keV, as compared to the depth reaching the maximum concentration of B ⁺ BF ⁺ The depth to reach the maximum concentration of BF ₂ ⁺ is about half as shallow, and the depth to reach the maximum concentration of BF ₂ ⁺ is about one-third shallower than the depth to reach the maximum concentration of B ⁺ . By utilizing the difference in depth, a very small amount of boron ions is accurately and uniformly added to the semiconductor film having a crystal structure by adjusting the thickness of the material layer.

In the structure of the invention disclosed in this specification, a semiconductor layer having a crystal structure is formed over a substrate having an insulating surface, a material layer is formed over the semiconductor layer having the crystal structure, and the semiconductor layer having the crystal structure is formed. And B and F are added to the material layer using BF ₃ as a doping gas,
In the method for manufacturing a semiconductor device in which the material layer is removed, when the BF ₃ is added as a doping gas, more boron is added than fluorine to the semiconductor layer having the crystal structure, and boron is added to the material layer. Is a method for manufacturing a semiconductor device, characterized in that a large amount of fluorine is added.

In the above structure, the threshold value of the TFT is controlled by setting the boron concentration contained in the semiconductor layer having the crystal structure to 1 × 10 ¹⁵ or more and 5 × 10 ¹⁷ or less.

  In addition, a semiconductor film having a crystal structure is manufactured by heat treatment or laser annealing (a technique for crystallizing a semiconductor film by laser irradiation) from an amorphous semiconductor film deposited by plasma CVD or low pressure CVD. ing.

The semiconductor film having a crystal structure manufactured in this way is an aggregate of a large number of crystal grains, and the crystal orientation is oriented in an arbitrary direction and cannot be controlled, which is a factor that limits the characteristics of the TFT. In order to solve such problems, the technique disclosed in Japanese Patent Laid-Open No. 7-183540 is to add a metal element that promotes crystallization of a semiconductor film such as nickel to produce a semiconductor film having a crystal structure. In addition to the effect of lowering the heating temperature required for crystallization, it is possible to increase the orientation of crystal orientation in a single direction. When a TFT is formed using a semiconductor film having such a crystal structure, not only the field-effect mobility is improved, but also the subthreshold coefficient (S value) is reduced, and the electrical characteristics can be dramatically improved. ing.

  By using a metal element that promotes crystallization, nucleation in crystallization can be controlled, so the film quality obtained is uniform compared to other crystallization methods in which nucleation is random, ideally. It is desirable to completely remove metal elements or reduce them to an acceptable range. However, since a metal element that promotes crystallization is added, the metal element remains in the film of the semiconductor film having a crystal structure or on the film surface, and there is a problem in that the characteristics of the obtained element are varied. . As an example, there is a problem that an off current increases in a TFT and varies between individual elements. That is, the metal element that promotes crystallization becomes unnecessary once a semiconductor film having a crystal structure is formed.

Further, when heat treatment is performed before the material layer is removed, impurities mixed in a portion to be a channel formation region can be moved to the material layer. By using a semiconductor film having a crystal structure from which impurities are reduced or removed as a channel formation region, electrical characteristics, in particular, off current can be reduced. By adding BF ⁺ or BF ₂ ⁺ instead of adding a single element to the material layer, more dangling bonds can be formed and function as a gettering site for trapping impurities.

The gettering technique is positioned as a main technique in the manufacturing technique of an integrated circuit using a single crystal silicon wafer. Gettering is known as a technique for reducing the impurity concentration of an active region of an element by segregating metal impurities taken into a semiconductor to gettering sites with some energy. This technology is roughly divided into two types: extrinsic gettering and intrinsic gettering. The extrinsic gettering provides a gettering effect by applying a strain field and chemical action from the outside. Intrinsic gettering is known as utilizing a strain field of lattice defects involving oxygen generated inside a single crystal silicon wafer.

  The present invention employs the following means for applying to a semiconductor film having a crystal structure of about 10 to 200 nm in thickness using a gettering mechanism different from the above-described extrinsic gettering and intrinsic gettering. To do.

In another aspect of the invention, a semiconductor layer having an amorphous structure is formed on a substrate having an insulating surface, and a metal element for promoting crystallization is added to the semiconductor film having an amorphous structure. The semiconductor layer having a crystal structure is formed by crystallization by performing the heat treatment, a material layer is formed on the semiconductor layer having the crystal structure, and the semiconductor layer having the crystal structure and the material layer are doped with BF ₃ A method for manufacturing a semiconductor device in which B and F are added as gases, a second heat treatment is performed, the metal element contained in a semiconductor layer having a crystal structure is moved to the material layer, and the material layer is removed. , When adding BF ₃ as a doping gas, the semiconductor layer having the crystal structure contains more boron than fluorine, and the material layer contains more fluorine than boron. This is a manufacturing method.

In another aspect of the invention, a semiconductor layer having an amorphous structure is formed on a substrate having an insulating surface, and a metal element for promoting crystallization is added to the semiconductor film having an amorphous structure. The semiconductor layer having a crystal structure is formed by crystallization by performing the heat treatment, an insulating layer (gate insulating film) is formed on the semiconductor layer having the crystal structure, and BF ₃ is formed on the semiconductor layer having the crystal structure. selectively forming a region added as doping gas, performing a second heat treatment, a method for manufacturing a semiconductor device for moving the metal element contained in the semiconductor layer having a crystal structure in the region, the BF ₃ In the method for manufacturing a semiconductor device, the region added with doping gas contains the metal element, boron, and fluorine.

  In the above structure, the metal element is one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au.

  In each of the above structures, an oxide film or a nitride film may be formed over the semiconductor layer having the crystal structure between the formation of the semiconductor layer having the crystal structure and the formation of the material layer. Since the material layer is removed later, a material different from that of the semiconductor film having a crystal structure is preferable as the material of the material layer. For example, a silicon nitride film or a silicon oxide film is used as the material of the material layer. Alternatively, a semiconductor film having the same material, for example, an amorphous structure or a crystal structure, may be used as the material layer. In that case, a film serving as an etching stopper between the material layer and the semiconductor film having a crystal structure. Is preferably provided.

  According to the present invention, a small amount of boron ions is accurately and uniformly added to a portion that becomes a channel formation region of a thin film transistor to control a threshold value of the thin film transistor, thereby reducing variation between individual thin film transistors. A semiconductor device having uniform electrical characteristics can be realized.

  Embodiments of the present invention will be described below.

(Embodiment 1)
A procedure for manufacturing a typical TFT using the present invention will be briefly described below with reference to FIGS. Here, an example in which a semiconductor film and a material film are formed on the semiconductor film by a plasma CVD apparatus and then B and F are added using BF ₃ as a doping gas is shown.

  In FIG. 2A, 100 is a substrate having an insulating surface, 101 is an insulating film serving as a blocking layer, and 102 is a semiconductor film having an amorphous structure.

  As the substrate 100, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. Alternatively, a silicon substrate, a metal substrate, or a stainless steel substrate with an insulating film formed thereon may be used. Alternatively, a plastic substrate having heat resistance that can withstand the processing temperature in this step may be used.

First, a base insulating film 101 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is formed over the substrate 100. As a typical example, the base insulating film 101 has a two-layer structure, and a silicon nitride oxide film formed by using SiH ₄ , NH ₃ , and N ₂ O as a reaction gas is 50 to 100 nm, SiH ₄ , and N ₂ O. A structure is employed in which a silicon oxynitride film is deposited to a thickness of 100 to 150 nm formed using a reactive gas as a reactive gas. In addition, a silicon nitride film (SiN film) or a silicon oxynitride film (SiN _x O _y film (X) Y)) having a thickness of 10 nm or less is preferably used as one layer of the base insulating film 101. Since nickel tends to move to a region having a high oxygen concentration during gettering, it is extremely effective to use a silicon nitride film as the base insulating film in contact with the semiconductor film. Alternatively, a three-layer structure in which a silicon nitride oxide film, a silicon oxynitride film, and a silicon nitride film are sequentially stacked may be used.

  Next, as illustrated in FIG. 2A, the semiconductor film 102 is formed over the base insulating film. As the semiconductor film 102, an amorphous semiconductor film, a semiconductor film including a crystal structure, a compound semiconductor film including an amorphous structure, or the like can be used. Specifically, amorphous silicon, microcrystalline silicon, Polycrystalline silicon or the like can be used. The semiconductor film including a crystal structure is formed by forming a semiconductor film having an amorphous structure by a known means (sputtering method, LPCVD method, plasma CVD method, or the like), and then performing a known crystallization process (laser crystallization method, A thermal crystallization method or a thermal crystallization method using a catalyst such as nickel). The semiconductor film 102 is formed with a thickness of 25 to 80 nm (preferably 30 to 60 nm). There is no limitation on the material of the crystalline semiconductor film, but it is preferably formed of silicon or a silicon germanium alloy.

Next, as illustrated in FIG. 2B, the material film 103 is formed over the semiconductor film 102. The material of the material film 103 is not particularly limited; however, since the material film 103 is removed in a later step, it is preferable to select a material having a high selectivity with respect to the semiconductor film 102 under etching conditions for removal. In the case where the same material as the semiconductor film 102 is used as the material of the material film 103, a film serving as an etching stopper may be formed between the semiconductor film 102 and the material film 103. The film thickness of the material film 103 may be determined based on doping conditions using BF ₃ gas to be performed later. The thickness of the material film 103 is adjusted so that the concentration of B added to the semiconductor film is in a concentration range of 1 × 10 ¹⁵ atoms / cm ³ or more and 5 × 10 ¹⁷ atoms / cm ³ or less.

Next, as shown in FIG. 2C, doping treatment using BF ₃ gas is performed using an ion doping apparatus. The ion species to be added are B ⁺ ions, BF ⁺ ions, and BF ₂ ⁺ ions, and the depth at which each ion reaches the maximum concentration is different. BF ⁺ ions and BF ₂ ⁺ ions are added shallower than B ⁺ ions. The purpose of performing the doping process using BF ₃ gas is to add a small amount of boron to the semiconductor film 102 through the material film 103 to control the threshold value of a TFT formed later. Depending on the doping conditions, fluorine may be added to the semiconductor film, but it does not particularly affect the electrical characteristics of the TFT.

Next, heat treatment is performed as illustrated in FIG. When heat treatment is performed in a furnace, heat treatment may be performed in an inert atmosphere, typically in a nitrogen atmosphere at 450 to 800 ° C. for 1 to 24 hours, for example, at 550 ° C. for 4 hours. In addition, when the substrate is introduced into a furnace heated to 450 to 800 ° C. in advance, the heat treatment may be performed by placing the substrate in a furnace heated to 700 ° C. for 3 minutes, for example. Moreover, you may irradiate strong light in addition to heat processing. In the case of irradiating intense light as the heat treatment, the substrate may be irradiated as long as the substrate can withstand, for example, a lamp light source for heating is turned on for about 3 minutes, and the semiconductor film is instantaneously heated to 700 ° C. To. Alternatively, the lamp light source for heating is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to 600 to 1000 ° C., preferably about 700 to 750 ° C.

  By this heat treatment, impurities in the semiconductor film 102 can be moved to the material film 103 in a direction indicated by an arrow in FIG. Reduction of impurities in the semiconductor film 102 by this heat treatment is also effective in controlling the threshold value of the TFT. However, when the heat treatment here is not necessary, the heat treatment may be omitted.

  Further, when a semiconductor film having a crystal structure crystallized using the technique described in Japanese Patent Laid-Open No. 8-78329 is used as the semiconductor film 102, the metal element contained in the semiconductor film is removed by the heat treatment, or the metal The concentration of the element can be reduced. Note that the technique described in Japanese Patent Application Laid-Open No. 8-78329 discloses that a metal element having a catalytic action for promoting crystallization (here, nickel) is 1 to 100 ppm in terms of weight on the surface of a semiconductor film having an amorphous structure. In this technique, a nickel acetate solution is applied by a spinner to form a nickel-containing layer, and heat treatment is performed for crystallization.

Next, only the material film 103 is selectively removed. Next, a semiconductor layer 105 having a desired shape is formed using a known patterning technique for the semiconductor film. (Figure 2 (E))

  After the step of forming the semiconductor layer 105 having a desired shape is completed, the surface of the semiconductor layer is washed with an etchant containing hydrofluoric acid, and an insulating film containing silicon as a main component and serving as the gate insulating film 106 is formed. The surface cleaning and the formation of the gate insulating film are desirably performed continuously without exposure to the atmosphere.

  Next, after cleaning the surface of the gate insulating film 106, the gate electrode 107 is formed. Next, an impurity element (P, As, or the like) imparting n-type conductivity to the semiconductor, here phosphorus, is added as appropriate, so that the source region 108 and the drain region 109 are formed. After the addition, heat treatment, intense light irradiation, or laser light irradiation is performed to activate the impurity element. Simultaneously with activation, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered. In particular, in an atmosphere of room temperature to 300 ° C., it is very effective to activate the impurity element by irradiating the second harmonic of the YAG laser from the front surface or the back surface. A YAG laser is a preferred activation means because it requires less maintenance.

  In addition, a channel formation region 110 which overlaps with the gate electrode 107 is provided between the source region 108 and the drain region 109 with the gate insulating film 106 interposed therebetween.

  In the subsequent steps, an interlayer insulating film 111 is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, a source electrode 112 and a drain electrode 113 are formed, and a TFT (n-channel TFT) is formed. To complete. (Fig. 2 (F))

  The present invention is not limited to the TFT structure of FIG. 2F, and if necessary, a lightly doped drain (LDD) having an LDD region between a channel formation region and a drain region (or source region). ) Structure may be used. In this structure, a region to which an impurity element is added at a low concentration is provided between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration, and this region is referred to as an LDD region. I'm calling. Further, a so-called GOLD (Gate-drain Overlapped LDD) structure in which an LDD region is disposed so as to overlap with a gate electrode through a gate insulating film may be employed.

  Although an n-channel TFT has been described here, it goes without saying that a p-channel TFT can be formed by using a p-type impurity element instead of an n-type impurity element.

  Although the top gate type TFT has been described as an example here, the present invention can be applied regardless of the TFT structure. For example, it can be applied to a bottom gate type (reverse stagger type) TFT or a forward stagger type TFT. Is possible.

(Embodiment 2)
Here, a manufacturing procedure of a p-channel TFT using the present invention will be briefly described with reference to FIGS.

  In FIG. 3A, 10 is a substrate having an insulating surface, 11 is an insulating film to be a blocking layer, and 12 is a semiconductor film having an amorphous structure.

First, as shown in FIG. 2A, a base insulating film 11 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film (SiO _x N _y ) is formed on a substrate 10.

Next, the semiconductor film 12 having an amorphous structure is formed over the base insulating film. For the semiconductor film 12, a semiconductor material containing silicon as a main component is used. Typically, an amorphous silicon film, an amorphous silicon germanium film, or the like is applied, and the film is formed to a thickness of 10 to 100 nm by a plasma CVD method, a low pressure CVD method, or a sputtering method. In order to obtain a semiconductor film having a good crystal structure by subsequent crystallization, the concentration of impurities such as oxygen and nitrogen contained in the semiconductor film 12 having an amorphous structure is set to 5 × 10 ¹⁸ / cm ³ ( It is good to reduce it below the atomic concentration measured by secondary ion mass spectrometry (SIMS). These impurities interfere with subsequent crystallization, and also increase the density of capture centers and recombination centers even after crystallization. Therefore, it is desirable not only to use a high-purity material gas but also to use an ultrahigh vacuum-compatible CVD apparatus equipped with a mirror surface treatment (electropolishing treatment) in the reaction chamber and an oil-free vacuum exhaust system.

  Next, as a technique for crystallizing the semiconductor film 12 having an amorphous structure, here, the technique described in Japanese Patent Laid-Open No. 8-78329 is used for crystallization. The technology described in this publication is based on a crystal structure in which an amorphous silicon film (also referred to as an amorphous silicon film) is selectively added with a metal element that promotes crystallization, and heat treatment is performed to expand the added region as a starting point. The semiconductor film which has this is formed. First, a nickel acetate salt solution containing 1 to 100 ppm by weight of a metal element (here, nickel) having a catalytic action for promoting crystallization is applied to the surface of the semiconductor film 12 having an amorphous structure with a spinner. A nickel-containing layer 13 is formed. (FIG. 3B) As a means other than the method for forming the nickel-containing layer 13 by coating, a means for forming an extremely thin film by sputtering, vapor deposition, or plasma treatment may be used. Although an example in which the coating is performed on the entire surface is shown here, a nickel-containing layer may be selectively formed by forming a mask.

Next, heat treatment is performed to perform crystallization. In this case, in crystallization, silicide is formed in a portion of the semiconductor film in contact with a metal element that promotes crystallization of the semiconductor, and crystallization proceeds using the silicide as a nucleus. Thus, the semiconductor film 14 having the crystal structure shown in FIG. 3C is formed. Note that the concentration of oxygen contained in the semiconductor film 14 after crystallization is desirably 5 × 10 ¹⁸ / cm ³ or less. Here, after heat treatment for dehydrogenation (450 ° C., 1 hour), heat treatment for crystallization (550 to 650 ° C. for 4 to 24 hours) is performed. When crystallization is performed by irradiation with strong light, any one of infrared light, visible light, ultraviolet light, or a combination thereof can be used. Typically, a halogen lamp, a metal halide, or the like is used. Light emitted from a lamp, xenon arc lamp, carbon arc lamp, high pressure sodium lamp, or high pressure mercury lamp is used. The lamp light source may be turned on and heated for a necessary time, or turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated once to 10 times, and the semiconductor film instantaneously has a temperature of 600 to 1000 ° C. What is necessary is just to heat to a grade. Note that if necessary, heat treatment for releasing hydrogen contained in the semiconductor film 14 having an amorphous structure may be performed before irradiation with strong light. In addition, crystallization may be performed by simultaneously performing heat treatment and irradiation with strong light. In consideration of productivity, it is desirable to perform crystallization by irradiation with strong light.

A metal element (in this case, nickel) remains in the semiconductor film 14 having a crystal structure obtained in this way. Although it is not uniformly distributed in the film, it remains at a concentration exceeding 1 × 10 ¹⁹ / cm ³ if it is an average concentration. Of course, various semiconductor elements including TFT can be formed even in such a state, but the element is removed by the gettering method of the present invention described below.

Next, it is preferable to irradiate the semiconductor film 14 having a crystal structure with laser light in order to increase the crystallization rate (the ratio of the crystal component in the total volume of the film) and repair defects remaining in the crystal grains. . When laser light is irradiated, a thin oxide film (not shown) is formed on the surface. As this laser light, an excimer laser light having a wavelength of 400 nm or less emitted from a pulsed laser light source, or a second harmonic or a third harmonic of a YAG laser may be used. Further, a solid-state laser capable of continuous oscillation may be used as the laser light, and the second to fourth harmonics of the fundamental wave may be used. Typically, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) may be applied.

  Next, a semiconductor layer 17 having a desired shape is formed on the semiconductor film by using a known patterning technique. Next, the surface of the semiconductor layer is washed with an etchant containing hydrofluoric acid to form an insulating film containing silicon as a main component and serving as the gate insulating film 18. The surface cleaning and the formation of the gate insulating film are desirably performed continuously without exposure to the atmosphere.

Next, as shown in FIG. 3E, after the surface of the gate insulating film 18 is cleaned, a gate electrode 19 is formed.

Next, as shown in FIG. 3F, a doping process using a BF ₃ gas is selectively performed using an ion doping apparatus. Note that a region where an n-channel TFT is formed may be covered with a mask and not added. In the doping process using BF ₃ gas, more boron can be added to the semiconductor layer 17 than in the doping process using diborane, and crystal breakdown can be induced. Ion species added to the semiconductor layer are B ⁺ ions, BF ⁺ ions, and BF ₂ ⁺ ions. However, if the acceleration voltage is the same, BF ⁺ ions B ⁺ ions as compared with the or BF ₂ ⁺ ions, because deep depth reaching the maximum concentration, BF ⁺ ions mainly for the semiconductor layer or BF ₂ ⁺ ions, It is preferable that the doping condition is such that is added. There are two purposes for performing the doping process using BF ₃ gas in this step. One is to form a high concentration impurity region that functions as a source region or a drain region, and the other is to form a region that functions as a gettering site.

  Here, the source region 20 and the drain region 21 are formed by adding in a self-aligning manner using the gate electrode 19 as a mask.

  Next, heat treatment, intense light irradiation, or laser light irradiation is performed to activate the impurity element, here, a boron element. Simultaneously with activation, plasma damage to the gate insulating film and plasma damage to the interface between the gate insulating film and the semiconductor layer can be recovered. In order to activate, simultaneously with the heat treatment, the metal element in the region to be the channel formation region 22, here nickel, is moved to the source region 20 and the drain region 21 in the direction of the arrow in FIG. Can do.

  Further, depending on the conditions of the heat treatment, defects remaining in the crystal grains can be repaired simultaneously with gettering, that is, crystallinity can be improved.

  In this specification, gettering means that a metal element in a gettering region (here, the first semiconductor film) is released by thermal energy and moves to a gettering site by diffusion.

  Further, a protective film such as a silicon oxide film or a silicon oxynitride film with a thickness of about 50 nm is preferably formed before the heat treatment. When heat treatment is performed after the protective film is formed, reduction in the thickness of the semiconductor film due to oxidation can be suppressed.

  In the subsequent steps, an interlayer insulating film 23 is formed, hydrogenation is performed, contact holes reaching the source region and the drain region are formed, a source electrode 24 and a drain electrode 25 are formed, and a TFT (n-channel TFT) To complete. (Fig. 3 (H))

The concentration of the metal element contained in the channel formation region 22 of the TFT thus obtained can be less than 1 × 10 ¹⁷ / cm ³ .

  Through the above-described steps, a semiconductor film having a crystal structure in which a metal element that sufficiently promotes crystallization is reduced or removed can be obtained. In the TFT using the semiconductor film as an active layer, the electrical characteristics can be improved. Variations between elements can be reduced. In particular, in a liquid crystal display device, display unevenness due to variations in TFT characteristics can be reduced.

In addition, in a semiconductor device having an OLED, an on-current (I _on ) of a TFT (TFT that supplies current to an OLED arranged in a driving circuit or a pixel) arranged so that a constant current flows through the pixel electrode. Variations can be reduced, and variations in luminance can be reduced.

In addition to the metal element that promotes crystallization, other metal elements (such as Fe and Cu) that become impurities can be removed or reduced by the above-described steps.

  Further, this embodiment mode can be freely combined with Embodiment Mode 1.

  The present invention having the above-described configuration will be described in more detail with the following examples.

  In this embodiment, an example of a light-emitting device in which a pixel portion, a driver circuit, and a terminal portion are formed over the same substrate and light can be extracted from both substrates is shown in FIG.

  After a base insulating film is formed over the substrate 610, each semiconductor layer is formed. In addition, these semiconductor layers may be manufactured according to Embodiment Mode 1 or Embodiment Mode 2, and include a desired boron concentration in a place to be a channel formation region. Next, after forming a gate insulating film covering the semiconductor layer, each gate electrode and terminal electrode are formed. Next, an impurity element imparting n-type conductivity (typically phosphorus or As) is doped into the semiconductor in order to form an n-channel TFT 636, and p-type is imparted to the semiconductor in order to form a p-channel TFT 637. A source region and a drain region, and if necessary, an LDD region are appropriately formed by doping with an impurity element (typically boron). Next, after forming a silicon nitride oxide film (SiNO film) containing hydrogen obtained by a PCVD method, the impurity element added to the semiconductor layer is activated and hydrogenated.

  Next, a planarization insulating film 616 to be an interlayer insulating film is formed. As the planarization insulating film 616, an insulating film having a skeleton structure formed of a bond of silicon (Si) and oxygen (O) obtained by a coating method is used.

Next, a contact hole is formed in the planarization insulating film using a mask, and at the same time, the planarization insulating film at the peripheral portion is removed.

Next, etching is performed using the planarization insulating film 616 as a mask to selectively remove the exposed SiNO film or gate insulating film containing hydrogen.

Next, after forming a conductive film, etching is performed using a mask to form drain wirings and source wirings.

  Next, the first electrode 623, that is, the anode (or cathode) of the organic light emitting element is formed.

Next, an SOG film obtained by a coating method (for example, an SiOx film containing an alkyl group) is patterned to form an insulator 629 (referred to as a bank, a partition, a barrier, a bank, or the like) that covers an end portion of the first electrode 623. Form.

  Next, a layer 624 containing an organic compound is formed by an evaporation method or a coating method. Next, a second electrode 625 made of a transparent conductive film, that is, a cathode (or an anode) of the organic light emitting element is formed. Next, a transparent protective layer 626 is formed by vapor deposition or sputtering. The transparent protective layer 626 protects the second electrode 625.

  Next, a transparent sealing substrate 633 is attached with a sealant 628 to seal the light emitting element. That is, the light emitting display device is sealed with a pair of substrates by surrounding the outer periphery of the display region with a sealant. Since the interlayer insulating film of the TFT is provided on the entire surface of the substrate, when the sealing material pattern is drawn on the inner side of the outer peripheral edge of the interlayer insulating film, one of the interlayer insulating films located outside the sealing material pattern. There is a risk of moisture and impurities entering from the part. Accordingly, the outer periphery of the planarization insulating film used as the interlayer insulating film of the TFT is overlapped with the inside of the sealing material pattern, preferably, the sealing material pattern so that the end of the planarizing insulating film covers the sealing material. . Note that a region surrounded by the sealant 628 is filled with a transparent filler 627.

  Finally, the FPC 632 is attached to the terminal electrode by an anisotropic conductive film 631 by a known method. The terminal electrode is preferably made of a transparent conductive film, and is formed on the terminal electrode formed simultaneously with the gate wiring. (Fig. 4)

  In addition, light from the light-emitting element passes through the substrate 610 and the sealing substrate 633 and is extracted to both sides. The structure shown in FIG. 4 is a light-emitting device having a structure in which light is extracted through both the substrate and the sealing substrate.

Through the above steps, the pixel portion, the driver circuit, and the terminal portion can be formed over the same substrate.

  Further, this embodiment can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

In this embodiment, an example of a liquid crystal display device in which a pixel portion, a driver circuit, and a terminal portion are formed over the same substrate is shown in FIG. FIG. 5 shows a cross-sectional view of a liquid crystal panel that does not use a color filter.

A field-sequential driving method is used in which a liquid crystal panel that does not use a color filter functions as an optical shutter and the RGB three-color backlight light sources blink at high speed. The field sequential method uses the limit of the temporal resolution capability of the human eye and realizes color display by continuous color additive color mixing.

Over the first substrate 701, a base insulating film 702 and three TFTs 703 are provided over the base insulating film. These TFTs have a channel formation region 720, low-concentration impurity regions 725 and 726, and source or drain regions 721 and 722 as active layers, a gate insulating film 705, gate electrodes 723a and 723b, and an interlayer insulating film. N-channel TFT having 706. These TFTs may be manufactured according to Embodiment Mode 1 or Embodiment Mode 2, and include a desired boron concentration in a channel formation region. Further, the gate electrode has two layers, and is composed of a lower layer 723a having a tapered shape and an upper layer 723b.

  The planarization insulating film 707 is a flat interlayer insulating film formed by a coating method.

Further, the drain wiring or source wirings 724a, 724b, and 724c of the TFT have a three-layer structure. Here, a laminated film of a Ti film, a single Al film, and an Al (C + Ni) alloy film is used. The drain wiring or source wiring of the TFT is preferably tapered in consideration of the coverage of the interlayer insulating film.

  The pixel electrode 708 includes ITO (indium tin oxide), ITSO (indium tin oxide containing silicon oxide obtained by a sputtering method using a target in which silicon oxide is contained in ITO by 2 to 10 wt%), and silicon oxide. A transparent conductive film such as a light-transmitting oxide conductive film (IZO) in which 2-20 atoms% of zinc oxide (ZnO) is mixed with indium oxide and ATO (antimony tin oxide) containing silicon oxide can be used. .

The columnar spacers 714 are made of resin and serve to keep the substrate interval constant. Accordingly, the columnar spacers 714 are arranged at equal intervals. Further, in order to make a high-speed response, the substrate interval is preferably 2 μm or less, and the height of the columnar spacer 714 is adjusted as appropriate. Further, in the case of a small screen size of 2 inches square or less, the columnar spacer is not necessarily provided, and the substrate interval may be adjusted only by a gap material such as a filler included in the sealing material.

  An alignment film 710 that covers the columnar spacers 714 and the pixel electrodes 708 is also provided. An alignment film 712 is also provided over the second substrate 716 which is a counter substrate, and the first substrate 701 and the second substrate 716 are bonded to each other with a sealant (not illustrated).

  A space between the first substrate 701 and the second substrate 716 is filled with a liquid crystal material 711. The liquid crystal material 711 may be a method in which liquid crystal is dropped under reduced pressure so that bubbles do not enter with a sealing material as a closed pattern, and both substrates are bonded together, or a sealing pattern having an opening is provided, and a TFT A dip type (pumping type) in which liquid crystals are injected using a capillary phenomenon after the substrates are bonded together may be used.

  The liquid crystal panel of this embodiment has a so-called π cell structure, and uses a display mode called an OCB (Optically Compensated Bend) mode. The π cell structure is a structure in which the pretilt angles of liquid crystal molecules are aligned in a plane-symmetric relationship with respect to the center plane between the active matrix substrate and the counter substrate. The alignment state of the π cell structure is splay alignment when no voltage is applied between the substrates, and shifts to bend alignment when a voltage is applied. When a voltage is further applied, the bend-aligned liquid crystal molecules are aligned perpendicularly to the substrates and light is transmitted. In the OCB mode, high-speed response that is about 10 times faster than the conventional TN mode can be realized.

  The liquid crystal panel is sandwiched between a pair of optical films (polarizing plate, retardation plate, etc.) 731 and 732. In addition, in the display in the OCB mode, it is preferable to use a biaxial retardation plate in order to compensate the viewing angle dependency of retardation three-dimensionally.

  As the backlight of the liquid crystal panel shown in FIG. The light from the LED 735 is led out by the light guide plate 734. In the field sequential driving method, R, G, and B LEDs are sequentially lit in the LED lighting period TR period, TG period, and TB period, respectively. During the lighting period (TR) of the red LED, a video signal (R1) corresponding to red is supplied to the liquid crystal panel, and one red image is written on the liquid crystal panel. Also, during the green LED lighting period (TG), video data (G1) corresponding to green is supplied to the liquid crystal panel, and one green image is written on the liquid crystal panel. Further, during the lighting period (TB) of the blue LED, video data (B1) corresponding to blue is supplied to the liquid crystal display device, and one screen image of blue is written on the liquid crystal display device. One frame is formed by writing these three images.

  Further, this embodiment can be freely combined with Embodiment Mode 1 or Embodiment Mode 2.

  Various electronic devices can be manufactured by incorporating an EL panel or a liquid crystal panel obtained by implementing the present invention. Electronic devices include video cameras, digital cameras, goggles-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), personal computers, game devices, portable information terminals (mobile computers, mobile phones, portable game machines) Or an electronic book or the like), an image reproducing device provided with a recording medium (specifically, a device equipped with a display capable of reproducing a recording medium such as Digital Versatile Disc (DVD) and displaying the image), and the like. . Specific examples of these electronic devices are shown in FIGS.

  FIG. 6A illustrates a television which includes a housing 2001, a support base 2002, a display portion 2003, a speaker portion 2004, a video input terminal 2005, and the like. The present invention can be applied to a semiconductor integrated circuit incorporated in a television and the display portion 2003 to realize a television with reduced power consumption. Note that all information display televisions such as personal computers, TV broadcast reception, and advertisement display are included.

  FIG. 6B illustrates a digital camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external connection port 2105, a shutter 2106, and the like. The present invention can be applied to a semiconductor integrated circuit (a memory, a CPU, and the like) incorporated in the digital camera and the display portion 2102 and can be a digital camera with little variation in electrical characteristics.

  FIG. 6C illustrates a personal computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external connection port 2205, a pointing mouse 2206, and the like. The present invention is applied to a semiconductor integrated circuit (memory, CPU, etc.) built in a personal computer and a display portion 2203, and wirings used for TFTs arranged in the display portion and a CMOS circuit constituting the CPU Contact resistance can be reduced, and a personal computer with less variation in electrical characteristics can be realized.

  FIG. 6D illustrates an electronic book which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared port 2305, and the like. The present invention can be applied to a semiconductor integrated circuit (such as a memory or a CPU) incorporated in an electronic book and a display portion 2302, and an electronic book with little variation in electric characteristics can be realized.

  FIG. 6E illustrates a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 2401, a housing 2402, a display portion A2403, a display portion B2404, and a recording medium (DVD or the like). A reading unit 2405, operation keys 2406, a speaker unit 2407, and the like are included. A display portion A2403 mainly displays image information, and a display portion B2404 mainly displays character information. The present invention can be applied to a semiconductor integrated circuit (memory, CPU, etc.) and display portions A, B 2403, and 2404 built in the image reproducing device, and an image reproducing device with little variation in electrical characteristics can be realized.

  FIG. 6F illustrates a portable game machine, which includes a main body 2501, a display portion 2505, operation switches 2504, and the like. When applied to a semiconductor integrated circuit (such as a memory or a CPU) incorporated in a game device and the display portion 2505, a portable game device with little variation in electrical characteristics can be realized.

  FIG. 6G illustrates a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external connection port 2604, a remote control reception portion 2605, an image receiving portion 2606, a battery 2607, an audio input portion 2608, an eyepiece portion 2609, and the like. Including. The present invention can be applied to a semiconductor integrated circuit (a memory, a CPU, and the like) incorporated in the video camera and the display portion 2602, and a video camera with little variation in electrical characteristics can be realized.

  FIG. 6H illustrates a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external connection port 2707, an antenna 2708, and the like. The present invention can be applied to a semiconductor integrated circuit (a memory, a CPU, a high-frequency circuit, or the like) incorporated in a mobile phone and a display portion 2703, and a mobile phone with little variation in electrical characteristics can be realized.

In addition to the thin film integrated circuit having a TFT obtained in the present invention, an antenna or the like is formed, so that a non-contact thin film integrated circuit device (also referred to as a wireless IC tag, RFID (radio frequency identification)) is obtained. It can also be used. A non-contact thin film integrated circuit device with little variation in individual electrical characteristics can be realized. In addition, by attaching the IC tag to various electronic devices, the distribution route of the electronic devices can be clarified.

  In addition, this embodiment can be freely combined with Embodiment Mode 1, Embodiment Mode 2, Embodiment Mode 1, or Example 2.

The graph which shows a density | concentration profile. 10A and 10B illustrate a manufacturing process of a thin film transistor. (Embodiment 1) 10A and 10B illustrate a manufacturing process of a thin film transistor. (Embodiment 2) FIG. 11 is a cross-sectional structure diagram of an active matrix EL display device. Example 1 FIG. 6 is a cross-sectional structure diagram of an active matrix liquid crystal display device. (Example 2) FIG. 14 illustrates an example of an electronic device. (Example 3)

Explanation of symbols

10 substrate 11 insulating film 12 semiconductor film 13 nickel-containing layer 14 semiconductor film 17 semiconductor layer 18 gate insulating film 19 gate electrode 20 source region 21 drain region 22 channel formation region 23 interlayer insulating film 24 source electrode 25 drain electrode 100 substrate 101 insulating film 102 Semiconductor film 103 Material film 105 Semiconductor layer 106 Gate insulating film 107 Gate electrode 108 Source region 109 Drain region 110 Channel forming region 111 Interlayer insulating film 112 Source electrode 113 Drain electrode

Claims (4)

Forming a semiconductor layer having an amorphous structure over a substrate having an insulating surface;
A metal element for promoting crystallization is added to the semiconductor layer having an amorphous structure;
Forming a semiconductor layer having a crystalline structure by crystallizing the semiconductor layer having an amorphous structure by a first heat treatment;
Forming a material layer on the semiconductor layer having the crystal structure;
Added non pure element content in the semiconductor layer and the material layer having a crystal structure,
Moving the metal element contained in the semiconductor layer having the crystal structure to the material layer by a second heat treatment;
A method for manufacturing a semiconductor device for removing the material layer,
The impurity element is added through the material layer at an accelerating voltage at which a small amount of boron ions is added to the semiconductor layer having the crystal structure using an ion doping apparatus using BF ₃ as a doping gas. The method for manufacturing a semiconductor device is performed in a direction in which the semiconductor layer is added to the semiconductor layer having the crystal structure . In claim 1,
A method for manufacturing a semiconductor device, wherein an oxide film or a nitride film is formed over the semiconductor layer having the crystal structure between the formation of the semiconductor layer having the crystal structure and the formation of the material layer. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the material layer is a semiconductor layer having an amorphous structure or a crystal structure. In any one of Claim 1 thru | or 3 ,
The method of manufacturing a semiconductor device, wherein the metal element is one or more selected from Fe, Ni, Co, Ru, Rh, Pd, Os, Ir, Pt, Cu, and Au.