JP4123360B2 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Semiconductor light emitting device and manufacturing method thereof Download PDF

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JP4123360B2
JP4123360B2 JP2002353527A JP2002353527A JP4123360B2 JP 4123360 B2 JP4123360 B2 JP 4123360B2 JP 2002353527 A JP2002353527 A JP 2002353527A JP 2002353527 A JP2002353527 A JP 2002353527A JP 4123360 B2 JP4123360 B2 JP 4123360B2
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layer
surface electrode
transparent conductive
light emitting
conductive layer
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JP2004186543A (en
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泰一郎 今野
恒弘 海野
憲治 柴田
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Hitachi Cable Ltd
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Description

【０００１】
【発明の属する技術分野】
本発明は電極接合性及びワイヤボンダビリティに優れ、順方向電圧の低い高輝度半導体発光素子及びその製造方法に関する。
【０００２】
【従来の技術】
従来発光ダイオード（LED）としては、GaP系の緑色発光ダイオードやAlGaAs系の赤色発光ダイオードがほとんどであった。しかし、最近GaN系やAlGaInP系の結晶層を有機金属気相成長法(MOVPE)により成長させる技術が開発され、橙色、黄色、緑色、青色の高輝度発光ダイオードが製造できるようになった。またMOVPE法により形成したエピタキシャルウエハを用いて、これまで不可能であった短波長の発光や、高輝度が得られるLEDが作製できるようになった。
【０００３】
LEDにおける表面電極直下の層としては、表面電極から注入された電流を効率よく分散し、発光波長に対する吸収が少ないものが要求される。このような透明導電層を作製するのに好適な材料として、酸化インジウムスズ（ITO）のような金属酸化物が知られている。ITO膜を透明導電層として用いると、従来の厚い電流分散層が不要になるので、低コストで高輝度のLEDが得られるようになる［例えば米国特許5,481,122号（特許文献１）、特開平11-4020号（特許文献２）］。
【０００４】
しかしエピタキシャルウエハ上にITO膜等の金属酸化物層を介して表面電極が形成されたLEDでは、ダイシングやワイヤボンディング等の工程で、表面電極が剥離してしまうという問題が生じることが分かった。また透明導電層と金属電極間に接触抵抗が発生し、順方向動作電圧が高くなるという問題もある。そのため、エピタキシャルウエハ上にITO膜を介して表面電極を形成したLEDの実用化は困難である。
【０００５】
上記問題に鑑み本出願人は先に、透明導電膜層に開口部を設けることにより、表面電極の耐剥離性を向上させ、かつ順方向動作電圧を低下させることを提案した（特願2001-173110 号）。図５に示すように、この半導体発光素子は、ｎ型GaAs基板１の第一の主面上に、ｎ型AlGaInPクラッド層２／アンドープAlGaInP活性層３／ｐ型AlGaInPクラッド層４からなるダブルヘテロ構造の発光部層12を有する。さらにｐ型クラッド層４上にはｐ型GaP等からなる電流分散層５が形成され、その上に開口部11を有する透明導電層７が形成されている。Au等からなる表面電極９（光取り出し側）は開口部11及び電流分散層５に接するように形成され、基板１の第二の主面（裏面）には、全体的にAuGe合金等からなる電極10（裏面電極）が形成されている。
【０００６】
この半導体発光素子では、表面電極９が開口部11を介して電流分散層５に接しているため、ダイシングやワイヤボンディング等による表面電極９の剥離は効果的に防止される。しかしながらこの半導体発光素子では、開口部11を有する透明導電層７上に蒸着法により表面電極９を形成するため、表面電極９のうち開口部11上の部分が透明導電層７上の部分より凹んでいる。このように中央部が凹んだ表面電極９では、ワイヤボンディング不良が起こり易いことが分かった。
【０００７】
開口部11上のみに透明導電層７より厚い表面電極９を形成すれば、表面電極９の表面凹みはなくなるが、表面電極９と透明導電層７との接触面積が小さくなり、順方向電圧が高くなるという問題がある。
【０００８】
従って本発明の目的は、電極接合性及びワイヤボンダビリティに優れ、順方向電圧の低い高輝度半導体発光素子及びその製造方法を提供することである。
【０００９】
【特許文献１】
米国特許5,481,122号明細書
【特許文献２】
特開平11-4020号公報
【００１０】
【課題を解決するための手段】
上記目的に鑑み鋭意研究の結果、本発明者等は、発光部層上（電流分散層及び／又は剥離防止層が設けられている場合にはその上）に形成された透明導電層に開口部を形成し、露出した発光部層、電流分散層又は剥離防止層に接触するとともに、透明導電層の開口部上の部分が透明導電層上の部分より厚くなるように表面電極を形成することにより、既存のワイヤボンダーでも表面電極の剥離やワイヤボンディング不良を防止しつつ容易にボンディングできることを発見し、本発明に想到した。
【００１１】
すなわち、本発明の半導体発光素子は、金属酸化物からなり、開口部を有してエピタキシャルウエハの上に設けられる透明導電層と、前記開口部を介して前記エピタキシャルウエハに接すると共に前記透明導電層より厚い第一の表面電極と、前記第一の表面電極を覆うと共に前記第一の表面電極の周囲の前記透明導電層の表面と接する第二の表面電極とを備える。
【００１２】
上記半導体発光素子において、前記エピタキシャルウエハは、電流分散層を有し、前記第一の表面電極は、前記電流分散層に接して設けられてもよく、また、前記透明導電層の下に剥離防止層を更に備え、前記第一の表面電極は、前記剥離防止層と接して設けられてもよい。
【００１３】
本発明の半導体発光素子の透明導電層を形成する金属酸化物はSnO2、In2O3、ITO及びGa含有ZnOからなる群から選ばれた少なくとも１種であるのが好ましい。また基板はGaAsからなり、発光部層はAlGaInP又はGaInPからなるのが好ましい。さらに電流分散層はGaP、GaAlP、AlGaInP、AlGaAs及びGaAsPからなる群から選ばれた少なくとも１種の化合物半導体からなるのが好ましい。
【００１４】
本発明の半導体発光素子に使用する剥離防止層は、(1) InP又はInAsの二元系化合物半導体、(2) AlInAs又はAlInPの三元系化合物半導体、(3) AlGaAs、AlGaP、GaInAs及びGaInPからなる群から選ばれた少なくとも１種の三元系化合物半導体（Gaのモル比：0.2以下）、(4) AlInAsPの四元系化合物半導体、(5) AlGaInP、AlGaInAs、AlGaAsP及びGaInAsPからなる群から選ばれた少なくとも１種の四元系化合物半導体（Gaのモル比：0.2以下）、又は(6) AlGaInAsPからなる五元系化合物半導体（Gaのモル比：0.2以下）のいずれかからなるのが好ましい。
【００１５】
本発明の半導体発光素子の製造方法は、前記透明導電層の前記開口部に前記透明導電層より厚い第一の表面電極を形成する工程と、前記第一の表面電極を覆うとともに前記表面電極の周囲の前記透明導電層の表面に接する第二の表面電極を形成する工程とを備える。
【００１６】
【発明の実施の形態】
[1] 半導体発光素子
(A) 構造
本発明の半導体発光素子（例えば発光ダイオード）は、エピタキシャルウエハの上に形成した透明導電層に開口部を形成し、露出した発光部層、電流分散層又は剥離防止層に直接接するとともに、透明導電層の開口部上の部分が透明導電層上の部分より厚くなるように表面電極が設けられていることを特徴とする。
【００１７】
以下、本発明の半導体発光素子の具体的な構造を添付図面を参照して詳細に説明するが、本発明はこれらに限定されず、本発明の趣旨を変更しない限り種々の変更を加えることができる。
【００１８】
(1) 第１の形態
図１は本発明の第１の形態による半導体発光素子の縦断面図であり、図２はその平面図である。図１は図２のＡ−Ａ縦断面図に相当する。ｎ型GaAs基板１の第一主面上に順にｎ型AlGaInPクラッド層２、アンドープAlGaInP活性層３及びｐ型AlGaInPクラッド層４が形成されており、ｎ型クラッド層２、活性層３及びｐ型クラッド層４によりダブルへテロ構造の発光部層12が構成されている。ｎ型GaAs基板１とｎ型AlGaInPクラッド層２の間に、バッファ層（図示せず）及び分布ブラッグ反射層（DBR層、図示せず）を形成しても良い。
【００１９】
ｐ型クラッド層４の表面上にｐ型電流分散層５が形成され、ｐ型電流分散層５の表面上に透明導電層７が形成されている。透明導電層７には開口部11（図２に破線で示す）が形成されている。透明導電層７の開口部11上に開口部11と同形で透明導電層７より厚い第一の表面電極91が形成されており、さらに第一の表面電極91を被覆するとともに第一の表面電極91の周囲の透明導電層７の表面に接する第二の表面電極92（図２に実線で示す）が形成されている。このため、第一の表面電極91は透明導電層７とその下のｐ型電流分散層５の両方に接している。ダイシング等により透明導電膜層７がエピタキシャル層から剥離するのを防止するために、ｐ型電流分散層５の上に透明導電膜層７の下地として剥離防止層（図示せず）が形成されている場合には、第一の表面電極91は剥離防止層と接する。なおｎ型GaAs基板１の裏面全面には裏面電極10が形成されている。
【００２０】
(2) 第２の形態
図３は本発明の第２の形態による半導体発光素子の縦端面図であり、図４はその平面図である。図３は図４のＢ−Ｂ縦端面図に相当する。この形態の半導体発光素子では、透明導電層７に複数の開口部11（図４の破線で示す）が形成されており、各開口部11には第一の表面電極91が同形に形成されている。第二の表面電極92（図４に実線で示す）は第一の表面電極91の包絡線より僅かに大きな領域に形成されている。その他の構造については第１の形態と同じであるので、説明を省略する。第２の形態でも、各第一の表面電極91は透明導電層７と電流分散層５の両方に接している。
【００２１】
いずれの形態においても、第一の表面電極91と下の層との十分な接合強度を得るために、開口部11の面積（複数の開口部11を有する場合には合計面積）は、第二の表面電極92の面積の１％以上であるのが好ましく、３〜50％であるのがより好ましい。開口部11の面積が１％未満では表面電極９の耐剥離性の向上が得られない。一方、開口部11の面積が95％超であると、透明導電層７の電流分散効果が不十分になり、発色出力が低くなる。
【００２２】
(B) 各層
(1) 基板
基板の材質はエピタキシャル層を構成する結晶層と熱膨張係数、格子定数等の特性が一致するものが好ましく、具体的にはGaAs、GaP、InP等が好ましく、特にGaAsが好ましい。
【００２３】
(2) 発光部層
発光部層12は、p-n接合型のダブルへテロ接合構造からなるのが好ましく、第一導電型のクラッド層（ｎ型クラッド層２）、活性層３及び第二導電型のクラッド層（ｐ型クラッド層４）からなるのが好ましい。また発光部層12は、混晶系の化合物半導体により構成するのが好ましい。具体的にはAlGaInP、GaInP、GaInAsP、AlGaInAs等の混晶が好ましく、AlGaInP及びGaInPがより好ましい。特にインジウム組成比を約0.5とする(AlxGa1-x)0.5In0.5P（0≦ｘ≦1）は、GaAs単結晶基板と格子整合するため好ましい。
【００２４】
(3) 電流分散層
ｐ型電流分散層５は、発光波長の吸収が少なく、かつ比抵抗が低い材料の中から選ばれる。具体的にはGaP、GaAlP、AlGaInP、GaAsP、AlGaAs等の化合物半導体が好ましい。電流分散層５はできるだけ薄い方が好ましい。
【００２５】
(4) 剥離防止層
剥離防止層は、(1) InP又はInAsの二元系化合物半導体、(2) AlInAs又はAlInPの三元系化合物半導体、(3) AlGaAs、AlGaP、GaInAs及びGaInPからなる群から選ばれた少なくとも１種の三元系化合物半導体（Gaのモル比：0.2以下）、(4) AlInAsPの四元系化合物半導体、(5) AlGaInP、AlGaInAs、AlGaAsP及びGaInAsPからなる群から選ばれた少なくとも１種の四元系化合物半導体（Gaのモル比：0.2以下）、又は(6) AlGaInAsPからなる五元系化合物半導体（Gaのモル比：0.2以下）のいずれかであるのが好ましい。
【００２６】
(5) 透明導電層
透明導電層７の比抵抗は電流分散層５の比抵抗より大幅に低い。例えばITO層の比抵抗は一般に約3×10-6Ωmであり、ITOの比抵抗はp形GaP層の比抵抗の約百分の一である。そのため透明導電層７を用いることにより、エピタキシャル半導体層の厚さを大幅に減少させることができる。透明導電層７は、酸化錫（SnO2）、酸化亜鉛（ZnO）、酸化インジウム（In2O3）、酸化インジウム錫（ITO）、酸化マグネシウム（MgO）等の酸化物からなるのが好ましく、特に酸化インジウム錫（ITO）からなるのが好ましい。ITOの比抵抗は約3×10-6Ωmで、ｐ型GaPの比抵抗の約百分の一であるので、透明導電層７をITOで形成することにより、透明導電層７の厚さを大幅に減少することができる。
【００２７】
(6) 電極
(a)表面電極
表面電極９は第一の表面電極91及び第二の表面電極92からなり、第一の表面電極91は下部層との良好なオーミック特性及び密着性を有し、第二の表面電極92は良好なボンディング特性を有するのが好ましい。また各表面電極91, 92は、金属（Au、Zn、Ni、Al等）、金属合金（Au-Zn、Au-Be等）等の複数の層からなる重層電極であってもよい。第二の表面電極92はAu、Al等のボンディング特性の良い金属からなるのが好ましい。各表面電極91, 92の重層電極は酸化ニッケル（NiO）、酸化チタン（TiO2）等の金属酸化物からなる層を含んでいても良い。
【００２８】
(b) 裏面電極
裏面電極10は、表面電極９と同様に良好なオーミック特性および密着性が要求されるため、金属（Au、Ni等）、金属合金（Au-Ge等）等の複数の層からなる重層電極であるのが好ましい。例えば、Au-Ge合金、Ni及びAuが順次積層された電極等が好ましい。裏面電極10は基板裏面の全面又は一部に形成され、最上層はAu、Alなどのボンディング特性の良い金属からなるのが好ましい。
【００２９】
[2] 半導体発光素子の製造方法
(1) エピタキシャル層の形成
エピタキシャル層を形成させる好ましい方法として、固相エピタキシャル成長法、液相エピタキシャル成長法又は気相エピタキシャル成長法が挙げられるが、エピタキシャル層の品質及び均一性の観点から気相エピタキシャル成長法がより好ましい。具体的には有機金属気相エピタキシャル成長法（MOVPE法）、分子線エピタキシャル成長法（MBE法）等が好ましい。
【００３０】
(2) 開口部を有する透明導電層の形成
開口部11を有する透明導電層７は、発光部層上（電流分散層及び／又は剥離防止層が設けられている場合にはその上）に公知の方法で作製することができる。例えば▲１▼ 塗布法（スピン式、ディップ式、ローラ式、スプレー式等）等により透明導電層７を形成し、さらにレジストマスクをしてから露光した後、エッチングにより開口部11を形成する方法、▲２▼ マスクを使用した蒸着法により所望の開口部11を有する透明導電層７を直接形成する方法、▲３▼ 塗布法（スピン式、ディップ式、ローラ式、スプレー式等）等により透明導電層７を形成した後、イオンミリング等の膜除去方法によって透明導電層７の一部を除去して開口部11を形成する方法、▲４▼ これら公知の方法の任意の組合せによる方法等が挙げられる。
【００３１】
開口部11の形状は特に制限はなく、円形、角形（四角、菱形、多角形等）、円形や角形に突起を付けた形状、リング状等任意の形状を設けることが可能である。また開口部11の数は１つである必要はなく、図３及び４に示すように複数でも良い。
【００３２】
(3) 電極の形成
図１及び３に示すように、透明導電層７の開口部11いっぱいに透明導電層７より厚い第一の表面電極91を蒸着し、次に第一の表面電極91を覆うとともに周囲の透明導電層７の表面と接するように、第二の表面電極92を蒸着する。このため表面電極９は、透明導電層７の開口部11上の部分が透明導電層７上の部分より厚くなる。裏面電極10は基板１の裏面に同様の導電性金属又はその合金を蒸着することにより形成する。蒸着方法として、高周波スパッタリング法、イオンプレーティング法、電子ビーム（EB）蒸着法、真空蒸着法等が挙げられる。
【００３３】
均一な電流分散性の観点から、例えば第１の形態のように１つの開口部11に第一の表面電極91を形成する場合、第一の表面電極91の中心と、開口部11の中心と、第二の表面電極92の中心とは実質的に一致するのが好ましい。また第２の形態のように複数の開口部11の各々に第一の表面電極91を形成する場合、全ての第一の表面電極91により包囲される領域の中心と、全ての開口部11により包囲される領域の中心と、第二の表面電極92の中心とは実質的に一致するのが好ましい。
【００３４】
電極にオーミック性を付与するために、例えば窒素ガス、アルゴンガス等の不活性雰囲気中で熱処理（アロイング）を施しても良い。
【００３５】
【実施例】
本発明を以下の実施例によりさらに詳細に説明するが、本発明はそれらに限定されるものではない。
【００３６】
実施例１
図１及び図２に示す構造の赤色発光ダイオード（発光波長630 nm付近）をMOVPE法により作製した。
【００３７】
(1) エピタキシャルウエハの作製
まず700℃に加熱したn型GaAs基板１上に、厚さ500 nmのn型（Seドープ）GaAsバッファ層、厚さ500 nmのn型（Seドープ）(Al0.7Ga0.3)0.5In0.5Pクラッド層２（Seドープ量：1.0×1018cm-3）、厚さ600 nmのアンドープ(Al0.15Ga0.85)0.5In0.5P活性層３、厚さ500 nmのp型（亜鉛ドープ）(Al0.7Ga0.3)0.5In0.5Pクラッド層４（亜鉛ドープ量：５×1017cm-3）、及び厚さ２μmのp型（亜鉛ドープ）GaP電流分散層５（亜鉛ドープ量：5×1018cm-3）を、MOVPE法により順にエピタキシャル成長させた。発光部層12（クラッド層２、発光層３、クラッド層４）のMOVPE成長は、700℃の温度及び50 Torr（66.7 hPa）の圧力で、0.3〜1.0 nm／秒の成長速度で行ない、供給したV族元素とIII族元素の比（V／III比）は300〜600の範囲であった。またGaP電流分散層５は、成長速度１nm／秒、V／III比100の条件で形成した。
【００３８】
キャリアガスに水素を使用し、それぞれAl供給源としてトリメチルアルミニウム（TMA）、Ga供給源としてトリメチルガリウム（TMG）、In供給源としてトリメチルインジウム（TMI）、As供給源としてアルシン（AsH3）、P供給源としてホスフィン（PH3）、Zn供給源としてジエチル亜鉛（DEZ）、及びSe供給源としてH2Seを使用した。
【００３９】
(2) 透明導電層の作製
上記のようにして作製したエピタキシャルウエハの表面に、塗布法によりITO膜を形成した。ITO膜を形成したエピタキシャルウェハを２×10-6 Torr（2.7×10-4Pa）の真空中で500℃で１時間焼成し、厚さ300 nmのITO透明導電層７を形成した。
【００４０】
(3) 表面電極の作製
ITO透明導電層７にフォトリソグラフィ法により開口部11を作製した。具体的には、ITO透明導電層７上に２次元的に一定間隔で直径75μmの円形開口部を有するレジストマスクを形成し、露光後に塩酸／硝酸／純水からなるエッチング液を用いて、レジストマスクの円形開口部に露出したITO膜を除去し、開口部11を作製した。レジストマスクの円形開口部11に、厚さ60 nmの金−亜鉛合金、厚さ10 nmのニッケル、及び厚さ1000 nmの金を順に蒸着した後、レジストマスクを除去することにより、直径75μmの円形の第一の表面電極91を形成した。次いで、開口部11と中心が一致する直径135μmの円形開口部を有するレジストマスクをITO膜上に形成した。レジストマスクの円形開口部に、厚さ500 nmの金を第一の表面電極91を覆うように蒸着した後、レジストマスクを除去することにより、直径135μmの円形の第二の表面電極92を形成した。得られた表面電極のうち開口部11上の部分の厚さは1570 nmであり、その周囲の透明導電層７上の部分の厚さは500 nmであった。
【００４１】
(4) 裏面電極の形成
基板１の裏面全体に、厚さ60 nmの金−ゲルマニウム合金、厚さ10 nmのニッケル及び厚さ500 nmの金を順に蒸着し、n型の裏面電極10を形成した。
【００４２】
第一及び第二の表面電極91, 92及び裏面電極10にオーミック性を付与するために、窒素ガス雰囲気中、400℃で5分間の熱処理（アロイング）を行なった。
【００４３】
(5) 半導体発光素子の作製及び評価
上記のようにして第一及び第二の表面電極91, 92からなる表面電極９及び裏面電極10まで形成したエピタキシャルウェハを、表面電極９を１つずつ含む300μm角のサイズでダイシングした。各半導体発光素子をフレームに固定し、第二の表面電極92にワイヤボンディングを、裏面電極10にダイボンディングを行なって、発光ダイオードチップを作製した。得られた発光ダイオードチップの順方向動作電圧（20 mA通電時）及び発光出力（20 mA通電時）を調べたところ、それぞれ1.90 V、2.2 mWであった。また発光ダイオードチップのワイヤボンディングの不良率はゼロであった。
【００４４】
比較例１
ITO透明導電層７に直径75μmの開口部11を形成した後、開口部11と中心が一致するように直径135μmの円形開口部を有するレジストマスクを形成し、厚さ60 nmの金−亜鉛合金、厚さ10 nmのニッケル、及び厚さ1000 nmの金を順に蒸着した以外実施例１と同様にして、図５に示す発光ダイオードチップを作製した。得られた発光ダイオードチップの順方向動作電圧（20 mA通電時）及び発光出力（20 mA通電時）を調べたところ、それぞれ1.90 V、2.2 mWであった。また発光ダイオードチップのワイヤボンディングの不良率は５〜10％であった。
【００４５】
以上の通り、透明導電層の開口部上の部分が透明導電層上の部分より厚くなるように表面電極９が形成された本発明の半導体発光素子では、ワイヤボンディング不良が効果的に防止される。
【００４６】
本発明は上記実施例に限定されず、本発明の技術的思想の範囲内で種々の変更を施すことができる。例えば、透明導電層に設ける開口部の形状及び数は図示の例に限定されず、透明導電層の下の層（クラッド層、電流分散層又は剥離防止層）と接するとともに、透明導電層の開口部上の部分が透明導電層上の部分より厚くなるように表面電極が形成されていればいかなるものでも良い。
【００４７】
【発明の効果】
上記の通り、本発明の半導体発光素子では、表面電極は透明導電層の開口部上の部分が透明導電層上の部分より厚いので、表面電極の剥離やワイヤボンディング不良が効果的に防止され、さらに順方向動作電圧を低く抑えることができる。従ってエピタキシャルウエハの膜厚を薄くすることが可能であり、コストの削減及び製造時の歩留まりの向上が可能である。
【図面の簡単な説明】
【図１】 本発明の一実施例による半導体発光素子を示す縦断面図であり、図２のＡ−Ａ縦断面図に相当する。
【図２】 本発明の一実施例による半導体発光素子を示す平面図である。
【図３】 本発明の別の実施例による半導体発光素子を示す縦端面図であり、図４のＢ−Ｂ縦端面図に相当する。
【図４】 本発明の別の実施例による半導体発光素子を示す平面図である。
【図５】 従来の半導体発光素子を示す縦断面図である。
【符号の説明】
１・・・基板
２・・・第１クラッド層
３・・・活性層
４・・・第２クラッド層
５・・・電流分散層
７・・・透明導電層
９・・・表面電極
91・・・第一の表面電極
92・・・第二の表面電極
10・・・裏面電極
11・・・開口部
12・・・発光部層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a high-intensity semiconductor light-emitting device that has excellent electrode bondability and wire bondability and a low forward voltage, and a method for manufacturing the same.
[0002]
[Prior art]
Conventional light emitting diodes (LEDs) are mostly GaP green light emitting diodes and AlGaAs red light emitting diodes. Recently, however, a technology for growing GaN-based and AlGaInP-based crystal layers by metal organic vapor phase epitaxy (MOVPE) has been developed, and high-intensity light-emitting diodes of orange, yellow, green, and blue can be manufactured. In addition, using an epitaxial wafer formed by the MOVPE method, it has become possible to produce LEDs that can emit light with a short wavelength and high brightness, which were impossible until now.
[0003]
As a layer directly under the surface electrode in the LED, a layer that efficiently disperses the current injected from the surface electrode and has little absorption with respect to the emission wavelength is required. A metal oxide such as indium tin oxide (ITO) is known as a suitable material for producing such a transparent conductive layer. When an ITO film is used as a transparent conductive layer, a conventional thick current spreading layer is not required, and a high-brightness LED can be obtained at a low cost [eg, US Pat. No. 5,481,122 (Patent Document 1) -4020 (Patent Document 2)].
[0004]
However, it has been found that in an LED in which a surface electrode is formed on an epitaxial wafer through a metal oxide layer such as an ITO film, the surface electrode peels off during processes such as dicing and wire bonding. There is also a problem that a contact resistance is generated between the transparent conductive layer and the metal electrode, and the forward operation voltage becomes high. For this reason, it is difficult to put into practical use an LED in which a surface electrode is formed on an epitaxial wafer via an ITO film.
[0005]
In view of the above problems, the present applicant has previously proposed to improve the peel resistance of the surface electrode and lower the forward operating voltage by providing an opening in the transparent conductive film layer (Japanese Patent Application 2001- 173110). As shown in FIG. 5, this semiconductor light emitting device has a double heterostructure comprising an n-type AlGaInP clad layer 2 / an undoped AlGaInP active layer 3 / p-type AlGaInP clad layer 4 on the first main surface of an n-type GaAs substrate 1. It has a light emitting part layer 12 having a structure. Further, a current spreading layer 5 made of p-type GaP or the like is formed on the p-type cladding layer 4, and a transparent conductive layer 7 having an opening 11 is formed thereon. The surface electrode 9 (light extraction side) made of Au or the like is formed so as to be in contact with the opening 11 and the current spreading layer 5, and the second main surface (back surface) of the substrate 1 is entirely made of AuGe alloy or the like. An electrode 10 (back surface electrode) is formed.
[0006]
In this semiconductor light emitting device, since the surface electrode 9 is in contact with the current spreading layer 5 through the opening 11, peeling of the surface electrode 9 due to dicing, wire bonding or the like is effectively prevented. However, in this semiconductor light emitting device, the surface electrode 9 is formed by vapor deposition on the transparent conductive layer 7 having the opening 11, so that the portion of the surface electrode 9 on the opening 11 is recessed from the portion on the transparent conductive layer 7. It is out. In this way, it was found that the surface electrode 9 having a recessed central portion is likely to cause wire bonding failure.
[0007]
If the surface electrode 9 thicker than the transparent conductive layer 7 is formed only on the opening 11, the surface electrode 9 has no surface dent, but the contact area between the surface electrode 9 and the transparent conductive layer 7 is reduced, and the forward voltage is reduced. There is a problem of becoming higher.
[0008]
Accordingly, an object of the present invention is to provide a high-intensity semiconductor light-emitting device having excellent electrode bondability and wire bondability and a low forward voltage, and a method for manufacturing the same.
[0009]
[Patent Document 1]
US Pat. No. 5,481,122 [Patent Document 2]
Japanese Patent Laid-Open No. 11-4020
[Means for Solving the Problems]
As a result of diligent research in view of the above object, the present inventors have found that an opening is formed in the transparent conductive layer formed on the light emitting part layer (on the case where a current dispersion layer and / or a peeling prevention layer is provided). And forming a surface electrode so that the portion on the opening of the transparent conductive layer is thicker than the portion on the transparent conductive layer, while being in contact with the exposed light emitting portion layer, current spreading layer or peeling prevention layer The present inventors have found that even an existing wire bonder can be easily bonded while preventing surface electrode peeling and wire bonding failure, and has arrived at the present invention.
[0011]
That is, the semiconductor light-emitting device of the present invention comprises a metallic oxide, the transparent conductive with a transparent conductive layer provided on the epitaxial wafer has an opening, through said opening in contact with the epitaxial wafer A first surface electrode that is thicker than the layer; and a second surface electrode that covers the first surface electrode and contacts the surface of the transparent conductive layer around the first surface electrode.
[0012]
In the semiconductor light emitting device, the epitaxial wafer may have a current spreading layer, and the first surface electrode may be provided in contact with the current spreading layer, and may prevent peeling under the transparent conductive layer. A layer may be further provided, and the first surface electrode may be provided in contact with the peeling prevention layer.
[0013]
The metal oxide forming the transparent conductive layer of the semiconductor light emitting device of the present invention is preferably at least one selected from the group consisting of SnO 2 , In 2 O 3 , ITO and Ga-containing ZnO. The substrate is preferably made of GaAs, and the light emitting portion layer is preferably made of AlGaInP or GaInP. Further, the current spreading layer is preferably made of at least one compound semiconductor selected from the group consisting of GaP, GaAlP, AlGaInP, AlGaAs and GaAsP.
[0014]
The peeling prevention layer used in the semiconductor light emitting device of the present invention includes (1) a binary compound semiconductor of InP or InAs, (2) a ternary compound semiconductor of AlInAs or AlInP, (3) AlGaAs, AlGaP, GaInAs, and GaInP. At least one ternary compound semiconductor selected from the group consisting of: (4) AlInAsP quaternary compound semiconductor, (5) AlGaInP, AlGaInAs, AlGaAsP and GaInAsP Or at least one quaternary compound semiconductor selected from (Ga molar ratio: 0.2 or less) or (6) a quaternary compound semiconductor composed of AlGaInAsP (Ga molar ratio: 0.2 or less) Is preferred.
[0015]
The surface electrode with a method of manufacturing a semiconductor light-emitting device of the present invention includes the steps of forming a thick first surface electrode than the transparent conductive layer in the opening of the front Symbol transparent conductive layer, covering the first surface electrode Forming a second surface electrode in contact with the surface of the transparent conductive layer around the substrate.
[0016]
DETAILED DESCRIPTION OF THE INVENTION
[1] semiconductor light emitting devices
(A) Structure The semiconductor light emitting device of the present invention (for example, a light emitting diode) has an opening formed in a transparent conductive layer formed on an epitaxial wafer, and is in direct contact with the exposed light emitting portion layer, current spreading layer or peeling prevention layer. In addition, the surface electrode is provided so that the portion on the opening of the transparent conductive layer is thicker than the portion on the transparent conductive layer.
[0017]
Hereinafter, the specific structure of the semiconductor light emitting device of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited thereto, and various modifications can be made without changing the gist of the present invention. it can.
[0018]
(1) First Embodiment FIG. 1 is a longitudinal sectional view of a semiconductor light emitting device according to a first embodiment of the present invention, and FIG. 2 is a plan view thereof. FIG. 1 corresponds to the AA longitudinal sectional view of FIG. An n-type AlGaInP cladding layer 2, an undoped AlGaInP active layer 3, and a p-type AlGaInP cladding layer 4 are formed in this order on the first main surface of the n-type GaAs substrate 1, and the n-type cladding layer 2, the active layer 3 and the p-type are formed. The clad layer 4 constitutes a light emitting layer 12 having a double hetero structure. A buffer layer (not shown) and a distributed Bragg reflection layer (DBR layer, not shown) may be formed between the n-type GaAs substrate 1 and the n-type AlGaInP cladding layer 2.
[0019]
A p-type current spreading layer 5 is formed on the surface of the p-type cladding layer 4, and a transparent conductive layer 7 is formed on the surface of the p-type current spreading layer 5. Openings 11 (shown by broken lines in FIG. 2) are formed in the transparent conductive layer 7. A first surface electrode 91 having the same shape as the opening 11 and thicker than the transparent conductive layer 7 is formed on the opening 11 of the transparent conductive layer 7, and further covers the first surface electrode 91 and the first surface electrode. A second surface electrode 92 (shown by a solid line in FIG. 2) in contact with the surface of the transparent conductive layer 7 around 91 is formed. For this reason, the first surface electrode 91 is in contact with both the transparent conductive layer 7 and the p-type current spreading layer 5 therebelow. In order to prevent the transparent conductive film layer 7 from being peeled off from the epitaxial layer by dicing or the like, a peeling prevention layer (not shown) is formed on the p-type current spreading layer 5 as a base of the transparent conductive film layer 7. If so, the first surface electrode 91 is in contact with the peeling prevention layer. A back electrode 10 is formed on the entire back surface of the n-type GaAs substrate 1.
[0020]
(2) Second Embodiment FIG. 3 is a vertical end view of a semiconductor light emitting device according to a second embodiment of the present invention, and FIG. 4 is a plan view thereof. FIG. 3 corresponds to the BB vertical end view of FIG. In the semiconductor light emitting device of this embodiment, a plurality of openings 11 (shown by broken lines in FIG. 4) are formed in the transparent conductive layer 7, and the first surface electrode 91 is formed in the same shape in each opening 11. Yes. The second surface electrode 92 (shown by a solid line in FIG. 4) is formed in a region slightly larger than the envelope of the first surface electrode 91. Since other structures are the same as those in the first embodiment, description thereof is omitted. Also in the second embodiment, each first surface electrode 91 is in contact with both the transparent conductive layer 7 and the current spreading layer 5.
[0021]
In any form, in order to obtain sufficient bonding strength between the first surface electrode 91 and the lower layer, the area of the opening 11 (the total area in the case of having a plurality of openings 11) is the second The area of the surface electrode 92 is preferably 1% or more, more preferably 3 to 50%. If the area of the opening 11 is less than 1%, the peel resistance of the surface electrode 9 cannot be improved. On the other hand, when the area of the opening 11 exceeds 95%, the current dispersion effect of the transparent conductive layer 7 becomes insufficient, and the color output becomes low.
[0022]
(B) Each layer
(1) The material of the substrate substrate is preferably the same as that of the crystal layer constituting the epitaxial layer and has the same characteristics such as thermal expansion coefficient and lattice constant. Specifically, GaAs, GaP, InP and the like are preferable, and GaAs is particularly preferable.
[0023]
(2) Light emitting part layer The light emitting part layer 12 preferably has a pn junction type double heterojunction structure, and includes a first conductivity type cladding layer (n-type cladding layer 2), an active layer 3 and a second conductivity type. It is preferable that it consists of a cladding layer (p-type cladding layer 4). The light emitting portion layer 12 is preferably composed of a mixed crystal compound semiconductor. Specifically, mixed crystals such as AlGaInP, GaInP, GaInAsP, and AlGaInAs are preferable, and AlGaInP and GaInP are more preferable. In particular, (Al x Ga 1-x ) 0.5 In 0.5 P (0 ≦ x ≦ 1) with an indium composition ratio of about 0.5 is preferable because lattice matching with a GaAs single crystal substrate is achieved.
[0024]
(3) Current Dispersion Layer The p-type current dispersion layer 5 is selected from materials that have low emission wavelength absorption and low specific resistance. Specifically, compound semiconductors such as GaP, GaAlP, AlGaInP, GaAsP, and AlGaAs are preferable. The current spreading layer 5 is preferably as thin as possible.
[0025]
(4) Peeling prevention layer The peeling prevention layer is composed of (1) a binary compound semiconductor of InP or InAs, (2) a ternary compound semiconductor of AlInAs or AlInP, and (3) a group consisting of AlGaAs, AlGaP, GaInAs and GaInP. (4) AlInAsP quaternary compound semiconductor, (5) AlGaInP, AlGaInAs, AlGaAsP, and GaInAsP selected from the group consisting of at least one ternary compound semiconductor (Ga molar ratio: 0.2 or less) selected from Further, it is preferably at least one kind of quaternary compound semiconductor (Ga molar ratio: 0.2 or less) or (6) a quaternary compound semiconductor composed of AlGaInAsP (Ga molar ratio: 0.2 or less).
[0026]
(5) Transparent Conductive Layer The specific resistance of the transparent conductive layer 7 is significantly lower than the specific resistance of the current spreading layer 5. For example, the specific resistance of the ITO layer is generally about 3 × 10 −6 Ωm, and the specific resistance of ITO is about one-hundred of the specific resistance of the p-type GaP layer. Therefore, by using the transparent conductive layer 7, the thickness of the epitaxial semiconductor layer can be greatly reduced. The transparent conductive layer 7 is preferably made of an oxide such as tin oxide (SnO 2 ), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium tin oxide (ITO), magnesium oxide (MgO), In particular, it is preferably made of indium tin oxide (ITO). Since the specific resistance of ITO is about 3 × 10 −6 Ωm and about one-hundred of the specific resistance of p-type GaP, the thickness of the transparent conductive layer 7 can be reduced by forming the transparent conductive layer 7 from ITO. Can be greatly reduced.
[0027]
(6) Electrode
(a) Surface electrode The surface electrode 9 comprises a first surface electrode 91 and a second surface electrode 92, and the first surface electrode 91 has good ohmic characteristics and adhesion with the lower layer, The surface electrode 92 preferably has good bonding characteristics. Each of the surface electrodes 91 and 92 may be a multilayer electrode composed of a plurality of layers such as metal (Au, Zn, Ni, Al, etc.), metal alloy (Au—Zn, Au—Be, etc.). The second surface electrode 92 is preferably made of a metal having good bonding characteristics such as Au and Al. The multilayer electrode of each of the surface electrodes 91 and 92 may include a layer made of a metal oxide such as nickel oxide (NiO) or titanium oxide (TiO 2 ).
[0028]
(b) Back electrode Since the back electrode 10 is required to have good ohmic characteristics and adhesiveness like the front electrode 9, a plurality of layers of metal (Au, Ni, etc.), metal alloy (Au-Ge, etc.), etc. A multilayer electrode made of For example, an Au—Ge alloy, an electrode in which Ni and Au are sequentially stacked are preferable. The back electrode 10 is preferably formed on the entire or part of the back surface of the substrate, and the uppermost layer is preferably made of a metal having good bonding characteristics such as Au and Al.
[0029]
[2] Manufacturing method of semiconductor light emitting device
(1) Formation of Epitaxial Layer Preferred methods for forming an epitaxial layer include solid phase epitaxial growth, liquid phase epitaxial growth, or vapor phase epitaxial growth, but vapor phase epitaxial growth is preferred from the viewpoint of epitaxial layer quality and uniformity. More preferred. Specifically, organometallic vapor phase epitaxy (MOVPE method), molecular beam epitaxy (MBE method) and the like are preferable.
[0030]
(2) Formation of a transparent conductive layer having an opening The transparent conductive layer 7 having the opening 11 is known on the light emitting portion layer (if a current dispersion layer and / or a peeling prevention layer is provided). It can produce by this method. For example, (1) A method of forming the transparent conductive layer 7 by a coating method (spin type, dip type, roller type, spray type, etc.), etc., forming a resist mask, exposing and then forming the opening 11 by etching. , (2) A method of directly forming a transparent conductive layer 7 having a desired opening 11 by vapor deposition using a mask, (3) Transparent by a coating method (spin type, dip type, roller type, spray type, etc.) After forming the conductive layer 7, a method of removing a part of the transparent conductive layer 7 by a film removal method such as ion milling to form the opening 11, and (4) a method by any combination of these known methods Can be mentioned.
[0031]
The shape of the opening 11 is not particularly limited, and an arbitrary shape such as a circular shape, a rectangular shape (square, rhombus, polygon, etc.), a circular shape or a rectangular shape with a protrusion, or a ring shape can be provided. Further, the number of openings 11 need not be one, and may be plural as shown in FIGS.
[0032]
(3) Formation of electrode As shown in FIGS. 1 and 3, a first surface electrode 91 thicker than the transparent conductive layer 7 is deposited over the opening 11 of the transparent conductive layer 7, and then the first surface electrode 91 is formed. A second surface electrode 92 is deposited so as to cover and in contact with the surface of the surrounding transparent conductive layer 7. For this reason, the surface electrode 9 is thicker on the transparent conductive layer 7 on the opening 11 than on the transparent conductive layer 7. The back electrode 10 is formed by depositing the same conductive metal or alloy thereof on the back surface of the substrate 1. Examples of the vapor deposition method include a high frequency sputtering method, an ion plating method, an electron beam (EB) vapor deposition method, and a vacuum vapor deposition method.
[0033]
From the viewpoint of uniform current dispersibility, for example, when the first surface electrode 91 is formed in one opening 11 as in the first embodiment, the center of the first surface electrode 91 and the center of the opening 11 It is preferable that the center of the second surface electrode 92 substantially coincides. Further, when the first surface electrode 91 is formed in each of the plurality of openings 11 as in the second embodiment, the center of the region surrounded by all the first surface electrodes 91 and all the openings 11 It is preferable that the center of the surrounded region substantially coincides with the center of the second surface electrode 92.
[0034]
In order to impart ohmic properties to the electrode, for example, heat treatment (alloying) may be performed in an inert atmosphere such as nitrogen gas or argon gas.
[0035]
【Example】
The present invention will be described in more detail with reference to the following examples, but the present invention is not limited thereto.
[0036]
Example 1
A red light emitting diode (emission wavelength around 630 nm) having the structure shown in FIGS. 1 and 2 was fabricated by the MOVPE method.
[0037]
(1) Fabrication of epitaxial wafer First, on an n-type GaAs substrate 1 heated to 700 ° C., an n-type (Se-doped) GaAs buffer layer having a thickness of 500 nm, an n-type (Se-doped) having a thickness of 500 nm (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P cladding layer 2 (Se doping amount: 1.0 × 10 18 cm −3 ), 600 nm thick undoped (Al 0.15 Ga 0.85 ) 0.5 In 0.5 P active layer 3, 500 nm thick p Type (zinc-doped) (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P clad layer 4 (zinc-doped amount: 5 × 10 17 cm −3 ) and p-type (zinc-doped) GaP current spreading layer 5 having a thickness of 2 μm (zinc Dope amount: 5 × 10 18 cm −3 ) was epitaxially grown in order by the MOVPE method. MOVPE growth of the light emitting layer 12 (cladding layer 2, light emitting layer 3, cladding layer 4) is performed at a temperature of 700 ° C. and a pressure of 50 Torr (66.7 hPa) at a growth rate of 0.3 to 1.0 nm / sec. The ratio of group V elements to group III elements (V / III ratio) was in the range of 300-600. The GaP current dispersion layer 5 was formed under conditions of a growth rate of 1 nm / second and a V / III ratio of 100.
[0038]
Hydrogen is used as the carrier gas, trimethylaluminum (TMA) as the Al supply source, trimethylgallium (TMG) as the Ga supply source, trimethylindium (TMI) as the In supply source, arsine (AsH 3 ) as the As supply source, P Phosphine (PH 3 ) was used as the source, diethyl zinc (DEZ) as the Zn source, and H 2 Se as the Se source.
[0039]
(2) Production of transparent conductive layer An ITO film was formed on the surface of the epitaxial wafer produced as described above by a coating method. The epitaxial wafer on which the ITO film was formed was baked at 500 ° C. for 1 hour in a vacuum of 2 × 10 −6 Torr (2.7 × 10 −4 Pa) to form an ITO transparent conductive layer 7 having a thickness of 300 nm.
[0040]
(3) Fabrication of surface electrode
Openings 11 were formed in the ITO transparent conductive layer 7 by photolithography. Specifically, a resist mask having circular openings with a diameter of 75 μm is formed two-dimensionally at regular intervals on the ITO transparent conductive layer 7, and the resist is etched using an etching solution composed of hydrochloric acid / nitric acid / pure water after exposure. The ITO film exposed in the circular opening of the mask was removed, and an opening 11 was produced. After vapor-depositing a 60 nm thick gold-zinc alloy, a 10 nm thick nickel, and a 1000 nm thick gold in this order on the circular opening 11 of the resist mask, the resist mask is removed to remove a diameter of 75 μm. A circular first surface electrode 91 was formed. Next, a resist mask having a circular opening with a diameter of 135 μm whose center coincided with the opening 11 was formed on the ITO film. After vapor deposition of gold with a thickness of 500 nm to cover the first surface electrode 91 in the circular opening of the resist mask, the resist mask is removed to form a circular second surface electrode 92 with a diameter of 135 μm did. The thickness of the part on the opening part 11 of the obtained surface electrode was 1570 nm, and the thickness of the part on the transparent conductive layer 7 around it was 500 nm.
[0041]
(4) Formation of back electrode On the entire back surface of the substrate 1, a 60 nm thick gold-germanium alloy, 10 nm thick nickel and 500 nm gold are sequentially deposited to form an n-type back electrode 10. did.
[0042]
In order to impart ohmic properties to the first and second front surface electrodes 91 and 92 and the back surface electrode 10, heat treatment (alloying) was performed at 400 ° C. for 5 minutes in a nitrogen gas atmosphere.
[0043]
(5) Fabrication and Evaluation of Semiconductor Light-Emitting Element The epitaxial wafer formed up to the surface electrode 9 and the back electrode 10 composed of the first and second surface electrodes 91 and 92 as described above includes the surface electrode 9 one by one. Dicing was performed with a size of 300 μm square. Each semiconductor light emitting element was fixed to a frame, wire bonding was performed on the second front surface electrode 92, and die bonding was performed on the back surface electrode 10, thereby manufacturing a light emitting diode chip. When the forward operating voltage (at 20 mA energization) and light emission output (at 20 mA energization) of the obtained light emitting diode chip were examined, they were 1.90 V and 2.2 mW, respectively. The defect rate of wire bonding of the light emitting diode chip was zero.
[0044]
Comparative Example 1
After forming an opening 11 having a diameter of 75 μm in the ITO transparent conductive layer 7, a resist mask having a circular opening having a diameter of 135 μm is formed so as to coincide with the center of the opening 11, and a gold-zinc alloy having a thickness of 60 nm A light-emitting diode chip shown in FIG. 5 was fabricated in the same manner as in Example 1 except that 10 nm thick nickel and 1000 nm thick gold were sequentially deposited. When the forward operating voltage (at 20 mA energization) and light emission output (at 20 mA energization) of the obtained light emitting diode chip were examined, they were 1.90 V and 2.2 mW, respectively. Moreover, the defect rate of the wire bonding of the light emitting diode chip was 5 to 10%.
[0045]
As described above, in the semiconductor light emitting device of the present invention in which the surface electrode 9 is formed so that the portion on the opening of the transparent conductive layer is thicker than the portion on the transparent conductive layer, wire bonding defects are effectively prevented. .
[0046]
The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope of the technical idea of the present invention. For example, the shape and the number of openings provided in the transparent conductive layer are not limited to the illustrated example, and the transparent conductive layer is in contact with the layer below the transparent conductive layer (cladding layer, current spreading layer or peeling prevention layer), and the opening of the transparent conductive layer. Any surface electrode may be used as long as the surface electrode is formed so that the portion on the portion is thicker than the portion on the transparent conductive layer.
[0047]
【The invention's effect】
As described above, in the semiconductor light emitting device of the present invention, since the surface electrode is thicker on the transparent conductive layer than on the transparent conductive layer, peeling of the surface electrode and wire bonding failure are effectively prevented, Furthermore, the forward operating voltage can be kept low. Therefore, it is possible to reduce the thickness of the epitaxial wafer, and it is possible to reduce the cost and improve the manufacturing yield.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view showing a semiconductor light emitting device according to an embodiment of the present invention, and corresponds to the AA longitudinal sectional view of FIG.
FIG. 2 is a plan view showing a semiconductor light emitting device according to an embodiment of the present invention.
3 is a longitudinal end view showing a semiconductor light emitting device according to another embodiment of the present invention, and corresponds to the BB longitudinal end view of FIG. 4;
FIG. 4 is a plan view showing a semiconductor light emitting device according to another embodiment of the present invention.
FIG. 5 is a longitudinal sectional view showing a conventional semiconductor light emitting device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... 1st clad layer 3 ... Active layer 4 ... 2nd clad layer 5 ... Current dispersion layer 7 ... Transparent conductive layer 9 ... Surface electrode
91 ... first surface electrode
92 ... Second surface electrode
10 ... Back electrode
11 ... Opening
12 ... Light emitting layer

Claims (9)

金属酸化物からなり、開口部を有してエピタキシャルウエハの上に設けられる透明導電層と、
前記開口部を介して前記エピタキシャルウエハに接すると共に前記透明導電層より厚い第一の表面電極と、
前記第一の表面電極を覆うと共に前記第一の表面電極の周囲の前記透明導電層の表面と接する第二の表面電極と
を備える半導体発光素子。 Consists metallic oxide, and a transparent conductive layer provided on the epitaxial wafer has an opening,
A first surface electrode in contact with the epitaxial wafer through the opening and thicker than the transparent conductive layer;
A second surface electrode covering the first surface electrode and in contact with the surface of the transparent conductive layer around the first surface electrode;
A semiconductor light emitting device comprising: 前記エピタキシャルウエハは、電流分散層を有し、
前記第一の表面電極は、前記電流分散層に接して設けられる
請求項１に記載の半導体発光素子。 The epitaxial wafer has a current spreading layer ,
The first surface electrode is provided in contact with the current spreading layer
The semiconductor light emitting device according to claim 1 . 前記透明導電層の下に剥離防止層
を更に備え、
前記第一の表面電極は、前記剥離防止層と接して設けられる
請求項１又は２に記載の半導体発光素子。Peeling prevention layer below the previous SL transparent conductive layer
Further comprising
The first surface electrode is provided in contact with the peeling prevention layer.
The semiconductor light emitting element according to claim 1 . 前記エピタキシャルウエハは、
裏面電極が形成された第一導電型のＧａＡｓからなる基板と、
前記基板上に形成されるＡｌＧａＩｎＰ又はＧａＩｎＰからなり、少なくとも第一導電型のクラッド層と第二導電型のクラッド層とに挟まれた活性層からなる発光部層と
を有し、
前記電流分散層は、前記発光部層の上に形成される
請求項２に記載の半導体発光素子。 The epitaxial wafer is
A substrate made of GaAs of the first conductivity type on which a back electrode is formed ;
A light emitting part layer made of AlGaInP or GaInP formed on the substrate, and comprising an active layer sandwiched between at least a first conductivity type cladding layer and a second conductivity type cladding layer;
Have
The current spreading layer is formed on the light emitting part layer.
The semiconductor light emitting device according to claim 2 . 前記電流分散層は、ＧａＰ、ＧａＡｌＰ、ＡｌＧａＩｎＰ、ＡｌＧａＡｓ、及びＧａＡｓＰからなる群から選ばれた少なくとも１種の化合物半導体からなる
請求項２又は４に記載の半導体発光素子。 Before SL current spreading layer, GaP, GaAlP, AlGaInP, AlGaAs, and at least one compound semiconductor selected from the group consisting of GaAsP
The semiconductor light emitting device according to claim 2 . 前記剥離防止層は、（１）ＩｎＰ又はＩｎＡｓの二元系化合物半導体、（２）ＡｌＩｎＡｓ又はＡｌＩｎＰの三元系化合物半導体、（３）ＡｌＧａＡｓ、ＡｌＧａＰ、ＧａＩｎＡｓ及びＧａＩｎＰからなる群から選ばれた少なくとも１種の三元系化合物半導体（Ｇａのモル比：０．２以下）、（４）ＡｌＩｎＡｓＰの四元系化合物半導体、（５）ＡｌＧａＩｎＰ、ＡｌＧａＩｎＡｓ、ＡｌＧａＡｓＰ及びＧａＩｎＡｓＰからなる群から選ばれた少なくとも１種の四元系化合物半導体（Ｇａのモル比：０．２以下）、又は（６）ＡｌＧａＩｎＡｓＰからなる五元系化合物半導体（Ｇａのモル比：０．２以下）のいずれかからなる
請求項３に記載の半導体発光素子。 Before SL separation prevention layer, selected from (1) InP or InAs of binary compound semiconductor, (2) AlInAs or AlInP ternary compound semiconductor, (3) AlGaAs, AlGaP, the group consisting of GaInAs and GaInP At least one ternary compound semiconductor (molar ratio of Ga: 0.2 or less), (4) a quaternary compound semiconductor of AlInAsP, (5) at least selected from the group consisting of AlGaInP, AlGaInAs, AlGaAsP and GaInAsP One kind of quaternary compound semiconductor (Ga molar ratio: 0.2 or less), or (6) a quaternary compound semiconductor composed of AlGaInAsP (Ga molar ratio: 0.2 or less)
The semiconductor light-emitting device according to claim 3 . 前記透明導電層を形成する金属酸化物はＳｎＯ２、Ｉｎ２Ｏ３、ＩＴＯ、及びＧａ含有ＺｎＯからなる群から選ばれた少なくとも１種である
請求項１から６のいずれか１項に記載の半導体発光素子。Metal oxide forming the pre-SL transparent conductive layer is SnO 2, In 2 O 3, ITO, and at least one selected from the group consisting of Ga-containing ZnO
The semiconductor light-emitting device according to claim 1 . 前記第一の表面電極は、前記開口部と同形であるThe first surface electrode has the same shape as the opening.
請求項１から７のいずれか１項に記載の半導体発光素子。The semiconductor light emitting element according to claim 1. 前記透明導電層の前記開口部に前記透明導電層より厚い第一の表面電極を形成する工程と、
前記第一の表面電極を覆うと共に前記表面電極の周囲の前記透明導電層の表面に接する第二の表面電極を形成する工程と
を備える請求項１から８のいずれか１項に記載の半導体発光素子を製造する方法。 Forming a thick first surface electrode than the transparent conductive layer in the opening of the front Symbol transparent conductive layer,
Forming a second surface electrode that covers the first surface electrode and is in contact with the surface of the transparent conductive layer around the surface electrode;
A method for manufacturing a semiconductor light emitting device according to claim 1 .
JP2002353527A 2002-12-05 2002-12-05 Semiconductor light emitting device and manufacturing method thereof Expired - Fee Related JP4123360B2 (en)

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