JP2000174333A - Gallium nitride compound semiconductor light-emitting element and manufacture thereof - Google Patents

Gallium nitride compound semiconductor light-emitting element and manufacture thereof

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Publication number
JP2000174333A
JP2000174333A JP34247998A JP34247998A JP2000174333A JP 2000174333 A JP2000174333 A JP 2000174333A JP 34247998 A JP34247998 A JP 34247998A JP 34247998 A JP34247998 A JP 34247998A JP 2000174333 A JP2000174333 A JP 2000174333A
Authority
JP
Japan
Prior art keywords
layer
cladding layer
electrode
gan cladding
gan
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP34247998A
Other languages
Japanese (ja)
Inventor
Haruhiko Okazaki
治彦 岡崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP34247998A priority Critical patent/JP2000174333A/en
Publication of JP2000174333A publication Critical patent/JP2000174333A/en
Abandoned legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/49105Connecting at different heights
    • H01L2224/49107Connecting at different heights on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Led Devices (AREA)
  • Led Device Packages (AREA)

Abstract

PROBLEM TO BE SOLVED: To facilitate chip-formation by a method, wherein an active layer is formed on an n-GaN clad layer, and a p-GaN clad layer, a connection layer, and a conductive substrate are sequentially formed thereon, and a first electrode is formed on the conductive substrate, and at the same time a second electrode is formed on a part of the n-GaN clad layer. SOLUTION: A GaN buffer layer 13 is formed on a sapphire substrate 14, and a double heterostructure is formed which comprises an n-GaN clad layer 11, an InGaN active layer 10, and a P-GaN clad layer 9 on the GaN buffer layer 13. An Au connection layer 8 is formed through a vapor-deposition method on the P-GaN clad layer 9, and is closely adhered to the Au connection layer 8 in a pressurized state, annealed, so that GaAs conductive substrates 7 are stuck to each other. Thereafter, a sapphire substrate 14 and a GaN buffer layer 13 are removed to form an n electrode 1 in a part of the n-GaN clad layer 11 exposed, and also a p-electrode 4 is formed on the GaAs conductive substrate 7.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は窒化ガリウム系AlxG
ayIn1-x-yN(0≦x,y≦1,x+y≦1)化合物半導体発光素子構
造およびその製造方法に関する。
The present invention relates to a gallium nitride-based AlxG.
The present invention relates to an ayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) compound semiconductor light emitting device structure and a method of manufacturing the same.

【0002】[0002]

【従来の技術】緑色から青色領域に至る発光ダイオード
(LED)の材料として、窒化ガリウム系化合物半導体であ
るAlxGayIn1-x-yN(0≦x,y≦1,x+y≦1)が用いられてい
る。この材料は直接遷移型のバンド構造を有するといわ
れており、高い発光強度をもつ。高輝度発光素子用材料
として開発の期待されるこの材料は、シリコンの理論限
界を超える電流・電圧・周波数領域下での電子デバイス
としての利用という点からも注目を集めている。AlxGay
In1-x-yN(0≦x,y≦1,x+y≦1)化合物半導体材料の結晶成
長温度は700℃から800℃であり、特にGaNでは1200℃の
高い値を持つ。そこで高温度下でも劣化せず安定した基
板材料としてサファイアやSiCが用いられている。図1
2は従来の窒化ガリウム系化合物半導体発光素子の構造
を示す断面図である。サファイア基板14の絶縁性のた
めp電極4、n電極1は共にサファイア基板側と反対の
結晶成長面側に形成される。ダブルへテロ構造部はn-Ga
Nクラッド層11、活性層10、p-GaNクラッド層9から
構成され、これら全体へ電流を流すために、p-GaNクラ
ッド層9上に透明電極27と電流阻止用の絶縁膜28を
形成し、透明電極27上の一部と絶縁膜28上にp電極
4は形成される。この従来の発光素子の製造方法を記
す。まずサファイア基板14上にGaNバッファ層13、n
-GaNクラッド層11、AlxGayIn1-x-yN(0≦x,y≦1,x+y≦
1)活性層10、そしてp-GaNクラッド層9を順次結晶成
長させる。AlxGayIn1-x-yN(0≦x,y≦1,x+y≦1)活性層1
0とp-GaNクラッド層9の一部をエッチング除去してn-G
aNクラッド層11の一部を露出させる。露出したn-GaN
クラッド層11上の一部にn電極1を形成させる。p-Ga
Nクラッド層9上に透明電極27と電流阻止用の絶縁膜
28を形成させる。透明電極27上の一部と電流阻止用
の絶縁膜28上にP電極4を形成させる。
2. Description of the Related Art Light emitting diodes ranging from green to blue regions
As a material for (LED), AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1), which is a gallium nitride-based compound semiconductor, is used. This material is said to have a direct transition type band structure, and has high emission intensity. This material, which is expected to be developed as a material for a high-brightness light-emitting element, has also attracted attention in terms of its use as an electronic device in a current, voltage, and frequency range exceeding the theoretical limits of silicon. AlxGay
The crystal growth temperature of the In1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) compound semiconductor material is from 700 ° C. to 800 ° C., particularly GaN has a high value of 1200 ° C. Therefore, sapphire or SiC is used as a stable substrate material that does not deteriorate even at high temperatures. FIG.
2 is a sectional view showing the structure of a conventional gallium nitride-based compound semiconductor light emitting device. Because of the insulating property of the sapphire substrate 14, both the p-electrode 4 and the n-electrode 1 are formed on the crystal growth surface side opposite to the sapphire substrate side. Double heterostructure is n-Ga
A transparent electrode 27 and a current blocking insulating film 28 are formed on the p-GaN cladding layer 9 in order to allow current to flow therethrough, comprising an N cladding layer 11, an active layer 10, and a p-GaN cladding layer 9. The p-electrode 4 is formed on a part of the transparent electrode 27 and on the insulating film 28. A method for manufacturing this conventional light emitting device will be described. First, the GaN buffer layer 13 and n
-GaN cladding layer 11, AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦
1) The active layer 10 and the p-GaN cladding layer 9 are sequentially crystal-grown. AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) active layer 1
0 and a part of the p-GaN cladding layer 9 are removed by etching to obtain nG
A part of the aN cladding layer 11 is exposed. Exposed n-GaN
An n-electrode 1 is formed on a part of the cladding layer 11. p-Ga
On the N cladding layer 9, a transparent electrode 27 and a current blocking insulating film 28 are formed. The P electrode 4 is formed on a part of the transparent electrode 27 and on the insulating film 28 for blocking current.

【0003】図11は従来の窒化ガリウム系化合物半導
体発光素子を用いたLEDの概略構造を示す断面図であ
る。半導体発光素子はp電極4側を上にしてリード24
の上に配置され、p電極4はボンディングワイヤー25
を介して、リード26に接続しており、n電極1はボン
ディングワイヤー23を介して、リード24に接続して
いる。
FIG. 11 is a sectional view showing a schematic structure of an LED using a conventional gallium nitride-based compound semiconductor light emitting device. The semiconductor light-emitting element has a lead 24 with the p-electrode 4 side facing up.
And the p electrode 4 is connected to the bonding wire 25
, And the n-electrode 1 is connected to the lead 24 via the bonding wire 23.

【0004】[0004]

【発明が解決しようとする課題】図12に示す従来の窒
化ガリウム系化合物半導体発光素子はn電極1をn-GaN
クラッド層11の結晶成長面に形成するために、図中1
2の部分だけ大きい基板を必要とした。またn電極1の
n-GaNクラッド層11との接続面積部分からの発光は行
われないため、非効率であった。従来の発光素子はn-Ga
Nクラッド層11内において、n電極1へ向かって電流
を横方向に流す構造であるため広がり抵抗を生じ、素子
抵抗の大きいものであった。従来の窒化ガリウム系化合
物半導体発光素子の製造工程は、結晶成長したAlxGayIn
1-x-yN(0≦x,y≦1,x+y≦1)活性層10とp-GaNクラッド
層9の一部の除去を必要とし、また透明電極27や絶縁
膜28の形成を必要とした。n電極1はn-GaNクラッド
層11上に形成されており、図11に示すようにボンデ
ィグワイヤー23を介してリード24に接続する工程が
必要であった。チップ化の工程はサファイア基板の硬い
材質のため難しく、歩留まりの低下を招いていた。
The conventional gallium nitride based compound semiconductor light emitting device shown in FIG.
In order to form on the crystal growth surface of the cladding layer 11,
A large substrate was required only for the portion 2. Also, the n-electrode 1
Since light was not emitted from the connection area portion with the n-GaN cladding layer 11, it was inefficient. Conventional light emitting devices are n-Ga
In the N-cladding layer 11, the current flows in the lateral direction toward the n-electrode 1, so that a spreading resistance is generated and the element resistance is large. Conventional gallium nitride-based compound semiconductor light-emitting devices are manufactured using AlxGayIn
1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) It is necessary to remove a part of the active layer 10 and the p-GaN cladding layer 9 and to form the transparent electrode 27 and the insulating film 28. Needed. The n-electrode 1 is formed on the n-GaN cladding layer 11, and requires a step of connecting to the lead 24 via the bonding wire 23 as shown in FIG. The step of chip formation is difficult due to the hard material of the sapphire substrate, which has led to a decrease in yield.

【0005】[0005]

【課題を解決するための手段】本発明の窒化ガリウム系
化合物半導体発光素子はn-GaNクラッド層と、前記n-GaN
クラッド層上に形成されたAlxGayIn1-x-yN(0≦x,y≦1,x
+y≦1)材料からなる活性層と、前記活性層上に形成され
たp-GaNクラッド層と、前記p-GaNクラッド層上に形成さ
れた接続層と、前記接続層上に形成された導電性基板
と、前記導電性基板上に形成された第一の電極と、前記
n-GaNクラッド層上の一部に形成された第二の電極とを
具備することを特徴とする。また前記導電性基板はSi,G
e,GaP,GaAs,InPのいづれかであることを特徴とする。ま
た前記接続層はAu,Ag,Ni,In,Gaのいづれかであることを
特徴とする。更に窒化ガリウム系化合物半導体発光素子
の製造方法は基板上にバッファ層を形成する工程と、前
記バッファ層上にn-GaNクラッド層と活性層とP-GaNクラ
ッド層を順に形成する工程と、接続層を前記P-GaNクラ
ッド層上に形成する工程と、前記接続層上に導電性基板
を張り合わせる工程と、前記導電性基板上に第一の電極
を形成する工程と、前記基板および前記バッファ層を除
去する工程と、前記n-GaNクラッド層上の一部に第二の
電極を形成する工程とを具備することを特徴とする。
The gallium nitride based compound semiconductor light emitting device of the present invention comprises an n-GaN cladding layer and the n-GaN cladding layer.
AlxGayIn1-x-yN formed on the cladding layer (0 ≦ x, y ≦ 1, x
+ y ≦ 1) an active layer made of a material, a p-GaN cladding layer formed on the active layer, a connection layer formed on the p-GaN cladding layer, and a p-GaN cladding layer formed on the p-GaN cladding layer. A conductive substrate, a first electrode formed on the conductive substrate,
a second electrode formed on a part of the n-GaN cladding layer. The conductive substrate is made of Si, G
e, GaP, GaAs or InP. Further, the connection layer is made of one of Au, Ag, Ni, In, and Ga. Further, the method for manufacturing a gallium nitride-based compound semiconductor light emitting device includes a step of forming a buffer layer on a substrate, a step of sequentially forming an n-GaN cladding layer, an active layer, and a P-GaN cladding layer on the buffer layer, Forming a layer on the P-GaN cladding layer, laminating a conductive substrate on the connection layer, forming a first electrode on the conductive substrate, the substrate and the buffer A step of removing a layer; and a step of forming a second electrode on a part of the n-GaN cladding layer.

【0006】このように本発明は、発光素子の構造にお
いて2つの電極のうち一方を導電性基板上に形成するも
のであり、従来n-GaNクラッド層上に形成していた電極
の接続面積分だけ発光の増加を可能とする。また電流の
流れはダブルへテロ構造部の層に対して垂直方向になる
ため、従来のn-GaNクラッド層内での横方向の流れに比
べて素子抵抗を抑えられる。発光素子の製造において、
固いサファイア基板を除去することによりチップ化が容
易になり、歩留まりを向上させることができる。
As described above, according to the present invention, in the structure of the light emitting device, one of the two electrodes is formed on the conductive substrate, and the connection area of the electrode conventionally formed on the n-GaN cladding layer is reduced. Only the emission can be increased. Further, since the current flows in a direction perpendicular to the layer of the double heterostructure, the element resistance can be suppressed as compared with the conventional flow in the lateral direction in the n-GaN cladding layer. In the manufacture of light emitting devices,
By removing the hard sapphire substrate, it becomes easy to make a chip, and the yield can be improved.

【0007】[0007]

【発明の実施の形態】以下、本発明の詳細を図示の実施
例によって説明する。図1は本発明の半導体発光素子を
用いたLEDの概略構造を示す断面図である。半導体発光
素子はn電極1を上にしてリード5の上に配置され、n
電極1はボンディングワイヤー2を介して、リード3に
接続している。p電極4はボンディングワイヤーを介さ
ず、直接リード5に接続している。発光素子およびリー
ドの一部は透明樹脂6により覆われている。図2は第一
の実施例における半導体発光素子の概略構造を示す断面
図である。半導体発光素子は下から順にp電極4、GaAs
導電性基板7、Au接続層8、p-GaNクラッド層9、InGaN
活性層10、n-GaNクラッド層11およびn-GaNクラッド
層11上の一部に形成されたn電極1で構成されてい
る。第一の実施例においてn電極1とp電極4はダブル
へテロ構造部とGaAs導電性基板7を挟むように上下に形
成している。このため、従来n電極1を結晶成長面に接
続するために必要であった面積分(図12の12)だけ
チップサイズは小さくできる。1辺350μmの正方形を1
辺200μmに縮小出来るため、2インチウエハから取れる
チップ数は従来の約16,000個から約49,000個に増大する
ことが出来る。またチップサイズを変えない場合は、発
光領域を広くすることが出来る。第一の実施例における
半導体発光素子のI-V特性は図3に示した。第一の実施
例における半導体発光素子は従来の発光素子に比べて注
入電流20mA時に約0.3Vの電圧低下を示した。電流のダブ
ルへテロ構造部内での上下方向の流れにより、素子抵抗
が低減したことがこの結果に起因していると考えられ
る。本実施例では導電性基板7にGaAs を用いたが代わ
りにSi,Ge,GaP,InPのいづれかを用いることを可能と
し、接続層8はAuの代わりにGa,In,Ni,Agのいづれかを
用いることを可能とする。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the illustrated embodiments. FIG. 1 is a sectional view showing a schematic structure of an LED using the semiconductor light emitting device of the present invention. The semiconductor light emitting device is arranged on the lead 5 with the n-electrode 1 facing up, and n
The electrode 1 is connected to a lead 3 via a bonding wire 2. The p electrode 4 is directly connected to the lead 5 without using a bonding wire. The light emitting element and a part of the lead are covered with the transparent resin 6. FIG. 2 is a sectional view showing a schematic structure of the semiconductor light emitting device in the first embodiment. The semiconductor light emitting element is a p-electrode 4, GaAs in order from the bottom.
Conductive substrate 7, Au connection layer 8, p-GaN cladding layer 9, InGaN
It comprises an active layer 10, an n-GaN cladding layer 11, and an n-electrode 1 formed on a part of the n-GaN cladding layer 11. In the first embodiment, the n-electrode 1 and the p-electrode 4 are formed vertically so as to sandwich the double heterostructure and the GaAs conductive substrate 7 therebetween. For this reason, the chip size can be reduced by the area (12 in FIG. 12) conventionally required to connect the n-electrode 1 to the crystal growth surface. 1 square of 350 μm on each side
Since the side can be reduced to 200 μm, the number of chips that can be obtained from a 2-inch wafer can be increased from about 16,000 to about 49,000. If the chip size is not changed, the light emitting area can be widened. FIG. 3 shows the IV characteristics of the semiconductor light emitting device in the first embodiment. The semiconductor light emitting device in the first embodiment showed a voltage drop of about 0.3 V at an injection current of 20 mA as compared with the conventional light emitting device. This is considered to be due to the fact that the element resistance was reduced due to the vertical flow of current in the double heterostructure. In this embodiment, GaAs is used for the conductive substrate 7, but any one of Si, Ge, GaP, and InP can be used instead, and the connection layer 8 can be made of Ga, In, Ni, or Ag instead of Au. Can be used.

【0008】次に第一の実施例に示した半導体発光素子
の製造工程を図2、図4、図5を用いて説明する。図4
において、サファイア基板14上にGaNバッファ層13
を形成する。GaNバッファ層13上に分子線エピタキシ
ャル成長(MBE)法を用いてn-GaNクラッド層11、InGa
N活性層10、p-GaNクラッド層9からなるダブルへテロ
構造部を形成する。そして蒸着法によりAu接続層8をp-
GaNクラッド層9上に形成する(図5)。このAu接続層
8の厚さは10nm以下に設定する。GaAs導電性基板7をAu
接続層8に加圧状態で密着させながら、窒素ガス雰囲気
中で700℃、1時間のアニールを行うことにより張り合
わせる。接続層8に用いられるAuはp-GaNクラッド層9
とGaAs導電性基板7からGaの析出を促す。析出したGaと
接続層Auとの化合により、GaAs導電性基板7はダブルへ
テロ構造部上に接着する。GaAs導電性基板7の厚さは50
μmから100μmの範囲に設定する。サファイア基板14
は約10μmの厚さに研磨し、RIE(Reactive Ion Etchin
g)法を用いて完全に除去する。GaNバッファ層13もRIE
法により完全に除去する。サファイア基板14およびGa
Nバッファ層13を除去して露出したn-GaNクラッド層1
1上の一部にNiからなるn電極1を形成する(図2)。
なおn電極1にTi,AlあるいはAuGeを用いることも可能
である。GaAs導電性基板7上にはAuZnからなるp電極4
を形成する。p電極、n電極は共に窒素雰囲気中500
℃、20秒のアニールによりオーミック電極として形成す
る。第一の実施例の製造工程において サファイア基板
14を除去しGaAs導電性基板7を形成することにより、
チップ化の工程は容易になり、歩留まりを向上させるこ
とができる。図6は本発明の第二の実施例に係わる発光
素子を示す断面図である。図中n電極1、p電極4、Ga
As導電性基板7、Au接続層8、p-GaNクラッド層9、InG
aN活性層10、n-GaNクラッド層11は第一の実施例と
同様の構造であるため、説明を省略する。本実施例では
Au接続層8とGaAs導電性基板7との間にPt膜15、Au接
続層16が形成されている点で第一の実施例と異なる。
Au接続層8の形成後、Pt膜15はAu接続層8上に蒸着し
て形成し、Au接続層16はPt膜15上に蒸着して形成す
る。次にGaAs導電性基板7をAu接続層16に加圧状態で
密着させながら窒素ガス雰囲気中700℃、1時間のアニ
ールを行うことにより張り合わせる。本実施例では接続
層8および16にAuを用いたが代わりにGa,Ni,In,Agのい
づれかを用いることが可能である。また接続層8および
16は必ずしも均一な薄膜でなくクラスター状あるいは
何らかのパターン状であってもよい。Pt膜15はNi,Pd,
W,Mo,Tiを用いてもよい。Pt膜15はAu接続層8と16
を熱に対して安定させることが出来る。
Next, a manufacturing process of the semiconductor light emitting device shown in the first embodiment will be described with reference to FIGS. 2, 4 and 5. FIG. FIG.
In the GaN buffer layer 13 on the sapphire substrate 14,
To form An n-GaN cladding layer 11 is formed on the GaN buffer layer 13 by molecular beam epitaxy (MBE).
A double hetero structure comprising the N active layer 10 and the p-GaN cladding layer 9 is formed. Then, the Au connection layer 8 is p-
It is formed on the GaN cladding layer 9 (FIG. 5). The thickness of the Au connection layer 8 is set to 10 nm or less. Au GaAs conductive substrate 7
Bonding is performed by performing annealing at 700 ° C. for 1 hour in a nitrogen gas atmosphere while being in close contact with the connection layer 8 in a pressurized state. Au used for the connection layer 8 is a p-GaN cladding layer 9.
And the deposition of Ga from the GaAs conductive substrate 7 is promoted. The combination of the deposited Ga and the connection layer Au causes the GaAs conductive substrate 7 to adhere to the double heterostructure. The thickness of the GaAs conductive substrate 7 is 50
Set in the range of μm to 100 μm. Sapphire substrate 14
Is polished to a thickness of about 10 μm, and RIE (Reactive Ion Etchin
Complete removal using method g). GaN buffer layer 13 is also RIE
Remove completely by method. Sapphire substrate 14 and Ga
N-GaN cladding layer 1 exposed by removing N buffer layer 13
An n-electrode 1 made of Ni is formed on a part of the first electrode 1 (FIG. 2).
Note that Ti, Al or AuGe can be used for the n-electrode 1. P electrode 4 made of AuZn on GaAs conductive substrate 7
To form Both p-electrode and n-electrode are in nitrogen atmosphere 500
An ohmic electrode is formed by annealing at 20 ° C. for 20 seconds. By removing the sapphire substrate 14 and forming the GaAs conductive substrate 7 in the manufacturing process of the first embodiment,
The step of chip formation is facilitated, and the yield can be improved. FIG. 6 is a sectional view showing a light emitting device according to the second embodiment of the present invention. In the figure, n electrode 1, p electrode 4, Ga
As conductive substrate 7, Au connection layer 8, p-GaN cladding layer 9, InG
Since the aN active layer 10 and the n-GaN cladding layer 11 have the same structure as in the first embodiment, description thereof will be omitted. In this embodiment,
It differs from the first embodiment in that a Pt film 15 and an Au connection layer 16 are formed between the Au connection layer 8 and the GaAs conductive substrate 7.
After the formation of the Au connection layer 8, the Pt film 15 is formed by vapor deposition on the Au connection layer 8, and the Au connection layer 16 is formed by vapor deposition on the Pt film 15. Next, the GaAs conductive substrate 7 is bonded to the Au connection layer 16 by being annealed at 700 ° C. for 1 hour in a nitrogen gas atmosphere while being closely adhered to the Au connection layer 16. In the present embodiment, Au is used for the connection layers 8 and 16, but any of Ga, Ni, In, and Ag can be used instead. The connection layers 8 and 16 are not necessarily a uniform thin film but may be in a cluster shape or some pattern shape. The Pt film 15 is made of Ni, Pd,
W, Mo, Ti may be used. The Pt film 15 has Au connection layers 8 and 16
Can be stabilized against heat.

【0009】図7は本発明の第三の実施例に係わる発光
素子を示す断面図である。図中n電極1、p電極4、導
電性基板7、Au接続層8、p-GaNクラッド層9、InGaN活
性層10、n-GaNクラッド層11は第一の実施例と同様
の構造であるため、説明を省略する。本実施例ではAu接
続層8とGaAs導電性基板7との間にp-AlGaInP層17が
形成され、さらにAu接続層8とp-GaNクラッド層9との
間にp-InGaN層18が形成されている点で第一の実施例
と異なる。p-InGaN層18はp-GaNクラッド層9上に結晶
成長させ、Au接続層8はp-InGaN層18上に蒸着させ、p
-AlGaInP層17はGaAs導電性基板7上に結晶成長させ
る。そしてp-AlGaInP層17とAu接続層8を加圧状態で
密着させながら窒素ガス雰囲気中700℃、1時間のアニ
ールを行うことにより両者を張り合わせる。Au接続層8
はp-AlGaInP層17およびp-InGaN層18からGaやInの析
出を促す。従って導電性基板7とダブルへテロ構造部と
の張り合わせは容易に行われるようになる。p-AlGaInP
層17はInGaAs,InGaP,AlGaAs,AlGaAsP, InGaAsP,AlGa
InP, p-InGaAsを用いることも可能であり、p-InGaN層
18はAlGaN,InGaN,AlGaInN,p-AlGaNを用いることも可
能である。
FIG. 7 is a sectional view showing a light emitting device according to a third embodiment of the present invention. In the figure, an n-electrode 1, a p-electrode 4, a conductive substrate 7, an Au connection layer 8, a p-GaN cladding layer 9, an InGaN active layer 10, and an n-GaN cladding layer 11 have the same structure as in the first embodiment. Therefore, the description is omitted. In this embodiment, a p-AlGaInP layer 17 is formed between the Au connection layer 8 and the GaAs conductive substrate 7, and a p-InGaN layer 18 is formed between the Au connection layer 8 and the p-GaN cladding layer 9. This is different from the first embodiment. The p-InGaN layer 18 is crystal-grown on the p-GaN cladding layer 9, the Au connection layer 8 is deposited on the p-InGaN layer 18,
The -AlGaInP layer 17 is grown on the GaAs conductive substrate 7. Then, while the p-AlGaInP layer 17 and the Au connection layer 8 are brought into close contact with each other in a pressurized state, annealing is performed at 700 ° C. for 1 hour in a nitrogen gas atmosphere to bond them together. Au connection layer 8
Promotes the precipitation of Ga and In from the p-AlGaInP layer 17 and the p-InGaN layer 18. Therefore, the bonding of the conductive substrate 7 and the double hetero structure portion can be easily performed. p-AlGaInP
Layer 17 is made of InGaAs, InGaP, AlGaAs, AlGaAsP, InGaAsP, AlGaP.
InP and p-InGaAs can also be used, and the p-InGaN layer 18 can also use AlGaN, InGaN, AlGaInN, and p-AlGaN.

【0010】図8は本発明の第四の実施例に係わる発光
素子を示す断面図である。図中n電極1、p電極4、p-
GaNクラッド層9、InGaN活性層10、n-GaNクラッド層
11は第一の実施例と同様の構造であるため、説明を省
略する。本実施例ではGaAs導電性基板7の代わりにp-Si
導電性基板20を用いる点およびAu接続層8の代わりに
p-GaP/p-GaAs からなるスーパーラティス19を用いる
点で第一の実施例とは異なる。p-Si導電性基板20はス
ーパーラティス19に加圧状態で密着させながら窒素ガ
ス雰囲気中700℃、1時間のアニールを行うことにより
張り合わせる。p-Si導電性基板20のダブルへテロ構造
部への張り合わせにおいてAu接続層8を用いると、p-Ga
Nクラッド層からのみGaが析出し、張り合わせは難しく
なる。スーパーラティス19はp-GaNクラッド層9上か
ら単原子層ずつ結晶成長して形成されていくが、その際
に格子が徐々にひずみp-Si導電性基板20とp-GaNクラ
ッド層9の格子定数の差を緩和する役目を果たすもので
ある。スーパーラティス19をAu接続層8の代わりに用
いれば、導電性基板にp-Siを用いることが出来る。スー
パーラティス19は約20組のp-GaP/p-GaAsの層からな
る。p-GaP層はp-Si導電性基板20に近いほど厚く、GaA
s導電性基板7側で薄くなるように形成される。反対にp
-GaAs層はp-Si導電性基板20に近いほど薄く、GaAs導
電性基板7側で厚くなるように形成される。
FIG. 8 is a sectional view showing a light emitting device according to a fourth embodiment of the present invention. In the figure, n electrode 1, p electrode 4, p-
Since the GaN cladding layer 9, the InGaN active layer 10, and the n-GaN cladding layer 11 have the same structure as in the first embodiment, the description is omitted. In this embodiment, the GaAs conductive substrate 7 is replaced with p-Si
The point of using the conductive substrate 20 and instead of the Au connection layer 8
It differs from the first embodiment in that a super lattice 19 made of p-GaP / p-GaAs is used. The p-Si conductive substrate 20 is bonded to the super lattice 19 by being annealed at 700 ° C. for 1 hour in a nitrogen gas atmosphere while being brought into close contact with the super lattice 19 in a pressurized state. When the Au connection layer 8 is used in bonding the p-Si conductive substrate 20 to the double hetero structure, p-Ga
Ga is deposited only from the N cladding layer, and bonding becomes difficult. The super lattice 19 is formed by crystal growth of a single atomic layer from the p-GaN cladding layer 9 on the p-GaN cladding layer 9. It serves to reduce the difference between the constants. If the super lattice 19 is used instead of the Au connection layer 8, p-Si can be used for the conductive substrate. The super lattice 19 is composed of about 20 pairs of p-GaP / p-GaAs layers. The p-GaP layer is thicker as the p-SiP
It is formed to be thin on the s conductive substrate 7 side. Conversely p
The -GaAs layer is formed to be thinner near the p-Si conductive substrate 20 and to be thicker on the GaAs conductive substrate 7 side.

【0011】図9は本発明の第五の実施例に係わる発光
素子を示す断面図である。図中n電極1、p電極4、Au
接続層8、p-GaNクラッド層9、InGaN活性層10、n-Ga
Nクラッド層11は第一の実施例と同様の構造であるた
め、説明を省略する。本実施例ではAu接続層8とp-GaN
クラッド層9との間にIn0.1GaN/AlNの15組からなるDBR
(Distributed Bragg Reflector)層21が形成されて
いる。DBR層のIn0.1GaNの厚さは0、045μmであ
り、AlNは0,052μmに設定されている。導電性基
板22はSiを用いている。DBR層21は90%の光反射
率を持つため、p-GaNクラッド層9とAu接続層8との間
に形成すれば光の基板吸収を防止出来る。DBR層21はA
u接続層8とSi導電性基板22の間に形成することも可
能である。図10は本発明の実施例に係わる発光素子を
上部から見た図である。図中11はn-GaNクラッド層で
あり、n電極1はn-GaNクラッド層1の中央に形成され
ている。n電極1はn-GaNクラッド層11上の中央に位
置する限りではなく、中央以外の位置に配置することも
可能である。
FIG. 9 is a sectional view showing a light emitting device according to a fifth embodiment of the present invention. In the figure, n electrode 1, p electrode 4, Au
Connection layer 8, p-GaN cladding layer 9, InGaN active layer 10, n-Ga
Since the N clad layer 11 has the same structure as that of the first embodiment, the description is omitted. In this embodiment, the Au connection layer 8 and the p-GaN
DBR consisting of 15 pairs of In0.1GaN / AlN between cladding layer 9
(Distributed Bragg Reflector) layer 21 is formed. The thickness of the In0.1GaN of the DBR layer is 0.045 μm, and the AlN is set to 0.052 μm. The conductive substrate 22 uses Si. Since the DBR layer 21 has a light reflectance of 90%, if it is formed between the p-GaN cladding layer 9 and the Au connection layer 8, the substrate absorption of light can be prevented. DBR layer 21 is A
It can be formed between the u connection layer 8 and the Si conductive substrate 22. FIG. 10 is a top view of a light emitting device according to an embodiment of the present invention. In the figure, reference numeral 11 denotes an n-GaN cladding layer, and the n-electrode 1 is formed at the center of the n-GaN cladding layer 1. The n-electrode 1 is not limited to being located at the center on the n-GaN cladding layer 11, but can be arranged at a position other than the center.

【0012】[0012]

【発明の効果】本発明の窒化ガリウム系化合物半導体発
光素子の構造により、発光有効面積率およびチップ収率
を上げることが出来る。発光素子の構造上、電流の流れ
はダブルへテロ構造部の層に対して垂直方向であるた
め、従来の横方向の流れに比べて素子抵抗を抑えること
が出来る。接続層をダブルへテロ構造部と導電性基板上
に介在させることにより密着性をよくすることができ
る。窒化ガリウム系化合物半導体発光素子の製造工程に
おいてサファイア基板を除去し導電性基板を形成するこ
とにより、チップ化が容易になり、歩留まりを向上させ
ることができる。
According to the structure of the gallium nitride based compound semiconductor light emitting device of the present invention, the effective light emitting area ratio and the chip yield can be increased. Due to the structure of the light emitting element, the current flows in the direction perpendicular to the layer of the double heterostructure, so that the element resistance can be suppressed as compared with the conventional flow in the lateral direction. Adhesion can be improved by interposing the connection layer on the double heterostructure and the conductive substrate. By removing the sapphire substrate and forming the conductive substrate in the manufacturing process of the gallium nitride-based compound semiconductor light-emitting device, it becomes easy to make a chip and the yield can be improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施例に係わる半導体発光素子を用い
たLEDを示す断面図、
FIG. 1 is a sectional view showing an LED using a semiconductor light emitting device according to an embodiment of the present invention;

【図2】本発明の第一の実施例に係わる半導体発光素子
を示す断面図、
FIG. 2 is a sectional view showing a semiconductor light emitting device according to a first embodiment of the present invention;

【図3】本発明の実施例に係わる半導体発光素子および
従来の発光素子のI-V特性を示す図、
FIG. 3 is a diagram showing IV characteristics of a semiconductor light emitting device according to an embodiment of the present invention and a conventional light emitting device.

【図4】本発明の第一の実施例に係わる半導体発光素子
の製造工程を示す断面図、
FIG. 4 is a sectional view showing a manufacturing process of the semiconductor light emitting device according to the first embodiment of the present invention;

【図5】本発明の第一の実施例に係わる半導体発光素子
の製造工程を示す断面図、
FIG. 5 is a sectional view showing a manufacturing process of the semiconductor light emitting device according to the first embodiment of the present invention;

【図6】本発明の第二の実施例に係わる半導体発光素子
を示す断面図、
FIG. 6 is a sectional view showing a semiconductor light emitting device according to a second embodiment of the present invention;

【図7】本発明の第三の実施例に係わる半導体発光素子
を示す断面図、
FIG. 7 is a sectional view showing a semiconductor light emitting device according to a third embodiment of the present invention;

【図8】本発明の第四の実施例に係わる半導体発光素子
を示す断面図、
FIG. 8 is a sectional view showing a semiconductor light emitting device according to a fourth embodiment of the present invention;

【図9】本発明の第五の実施例に係わる半導体発光素子
を示す断面図、
FIG. 9 is a sectional view showing a semiconductor light emitting device according to a fifth embodiment of the present invention;

【図10】本発明の実施例に係わる半導体発光素子の上
部の図、
FIG. 10 is a top view of a semiconductor light emitting device according to an embodiment of the present invention;

【図11】従来の窒化ガリウム系化合物半導体発光素子
を用いたLEDを示す断面図、
FIG. 11 is a cross-sectional view showing an LED using a conventional gallium nitride-based compound semiconductor light emitting device.

【図12】従来の窒化ガリウム系化合物半導体発光素子
を示す断面図。
FIG. 12 is a sectional view showing a conventional gallium nitride-based compound semiconductor light emitting device.

【符号の説明】[Explanation of symbols]

1…n電極、2、23、25…ボンディングワイヤー、
3、5、24、26…リード、4…p電極、6…透明樹
脂、7…GaAs導電性基板、8,16…Au接続層、9…p-GaN
クラッド層、10…AlxGayIn1-x-yN(0≦x,y≦1,x+y≦1)
活性層、11…n-GaNクラッド層、12…n電極の形成
に必要な部分、13…GaNバッファ層、14…サファイ
ア基板、15…Pt膜、17…p-AlGaInP層、18…InGaN
層、19…スーパーラティス、20…p-Si導電性基板、
21…DBR層、22…Si導電性基板、27…透明電極、
28…絶縁膜。
1 ... n electrode, 2, 23, 25 ... bonding wire,
3, 5, 24, 26 lead, 4 p electrode, 6 transparent resin, 7 GaAs conductive substrate, 8, 16 Au connection layer, 9 p-GaN
Cladding layer, 10 ... AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1)
Active layer, 11 n-GaN cladding layer, 12 parts required for forming n electrode, 13 GaN buffer layer, 14 sapphire substrate, 15 Pt film, 17 p-AlGaInP layer, 18 InGaN
Layer, 19 ... super lattice, 20 ... p-Si conductive substrate,
21: DBR layer, 22: Si conductive substrate, 27: transparent electrode,
28 ... Insulating film.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】n-GaNクラッド層と、前記n-GaNクラッド層
上に形成されたAlxGayIn1-x-yN(0≦x,y≦1,x+y≦1)材料
からなる活性層と、前記活性層上に形成されたp-GaNク
ラッド層と、前記p-GaNクラッド層上に形成された接続
層と、前記接続層上に形成された導電性基板と、前記導
電性基板上に形成された第一の電極と、前記n-GaNクラ
ッド層上の一部に形成された第二の電極と、を具備する
ことを特徴とする窒化ガリウム系化合物半導体発光素
子。
1. An n-GaN cladding layer, and an active layer made of AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) formed on the n-GaN cladding layer; A p-GaN cladding layer formed on the active layer, a connection layer formed on the p-GaN cladding layer, a conductive substrate formed on the connection layer, and formed on the conductive substrate A gallium nitride-based compound semiconductor light emitting device, comprising: a first electrode formed as described above; and a second electrode formed on a part of the n-GaN cladding layer.
【請求項2】前記導電性基板はSi,Ge,GaP,GaAs,InPのい
づれかであることを特徴とする請求項1記載の窒化ガリ
ウム系化合物半導体発光素子。
2. The gallium nitride-based compound semiconductor light-emitting device according to claim 1, wherein said conductive substrate is any one of Si, Ge, GaP, GaAs and InP.
【請求項3】前記接続層はAu,Ag,Ni,In,Gaのいづれかで
あることを特徴とする請求項1記載の窒化ガリウム系化
合物半導体発光素子。
3. The gallium nitride-based compound semiconductor light-emitting device according to claim 1, wherein said connection layer is made of one of Au, Ag, Ni, In, and Ga.
【請求項4】基板上にバッファ層を形成する工程と、前
記バッファ層上にn-GaNクラッド層とAlxGayIn1-x-yN(0
≦x,y≦1,x+y≦1)材料からなる活性層とP-GaNクラッド
層を順に形成する工程と、接続層を前記P-GaNクラッド
層上に形成する工程と、前記接続層上に導電性基板を張
り合わせる工程と、前記導電性基板上に第一の電極を形
成する工程と、前記基板および前記バッファ層を除去す
る工程と、前記n-GaNクラッド層上の一部に第二の電極
を形成する工程と、を具備することを特徴とする窒化ガ
リウム系化合物半導体発光素子の製造方法。
4. A step of forming a buffer layer on a substrate, and forming an n-GaN cladding layer and AlxGayIn1-x-yN (0
≦ x, y ≦ 1, x + y ≦ 1) a step of sequentially forming an active layer made of a material and a P-GaN cladding layer; a step of forming a connection layer on the P-GaN cladding layer; and Laminating a conductive substrate on, a step of forming a first electrode on the conductive substrate, a step of removing the substrate and the buffer layer, and a part on the n-GaN cladding layer Forming a second electrode. A method for manufacturing a gallium nitride-based compound semiconductor light emitting device, comprising:
【請求項5】n-GaNクラッド層と、前記n-GaNクラッド層
上に形成されたAlxGayIn1-x-yN(0≦x,y≦1,x+y≦1)材料
からなる活性層と、前記活性層上に形成されたp-GaNク
ラッド層と、前記p-GaNクラッド層上に形成された第一
の接続層と、前記第一の接続層上に形成された高融点金
属膜と、前記高融点金属膜上に形成された第二の接続層
と、前記第二の接続層上に形成された導電性基板と、前
記導電性基板上に形成された第一の電極と、前記n-GaN
クラッド層上の一部に形成された第二の電極と、を具備
することを特徴とする窒化ガリウム系化合物半導体発光
素子。
5. An n-GaN cladding layer, and an active layer made of AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) formed on the n-GaN cladding layer; A p-GaN cladding layer formed on the active layer, a first connection layer formed on the p-GaN cladding layer, a refractory metal film formed on the first connection layer, A second connection layer formed on the refractory metal film, a conductive substrate formed on the second connection layer, a first electrode formed on the conductive substrate, and the n -GaN
A gallium nitride-based compound semiconductor light emitting device, comprising: a second electrode formed on a part of the cladding layer.
【請求項6】n-GaNクラッド層と、前記n-GaNクラッド層
上に形成されたAlxGayIn1-x-yN(0≦x,y≦1,x+y≦1)材料
からなる活性層と、前記活性層上に形成されたp-GaNク
ラッド層と、前記p-GaNクラッド層上に形成された光反
射層と、前記光反射層上に形成された接続層と、前記接
続層上に形成された導電性基板と、前記導電性基板上に
形成された第一の電極と、前記n-GaNクラッド層上の一
部に形成された第二の電極と、を具備することを特徴と
する窒化ガリウム系化合物半導体発光素子。
6. An n-GaN cladding layer, and an active layer made of AlxGayIn1-x-yN (0 ≦ x, y ≦ 1, x + y ≦ 1) material formed on the n-GaN cladding layer, A p-GaN cladding layer formed on the active layer, a light reflection layer formed on the p-GaN cladding layer, a connection layer formed on the light reflection layer, and a light reflection layer formed on the connection layer. A conductive substrate, a first electrode formed on the conductive substrate, and a second electrode formed on a part of the n-GaN cladding layer. Gallium nitride based compound semiconductor light emitting device.
JP34247998A 1998-12-02 1998-12-02 Gallium nitride compound semiconductor light-emitting element and manufacture thereof Abandoned JP2000174333A (en)

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