JP4122159B2 - ビルドアップ基板の製造方法 - Google Patents

ビルドアップ基板の製造方法 Download PDF

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Publication number
JP4122159B2
JP4122159B2 JP2002017616A JP2002017616A JP4122159B2 JP 4122159 B2 JP4122159 B2 JP 4122159B2 JP 2002017616 A JP2002017616 A JP 2002017616A JP 2002017616 A JP2002017616 A JP 2002017616A JP 4122159 B2 JP4122159 B2 JP 4122159B2
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Japan
Prior art keywords
via hole
conductor foil
wiring pattern
plating
layer
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Expired - Fee Related
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JP2002017616A
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Japanese (ja)
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JP2003218533A5 (enExample
JP2003218533A (ja
Inventor
節 有賀
秀明 吉沢
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Eastern KK
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Eastern KK
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Priority to JP2002017616A priority Critical patent/JP4122159B2/ja
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Publication of JP2003218533A5 publication Critical patent/JP2003218533A5/ja
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  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2002017616A 2002-01-25 2002-01-25 ビルドアップ基板の製造方法 Expired - Fee Related JP4122159B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002017616A JP4122159B2 (ja) 2002-01-25 2002-01-25 ビルドアップ基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002017616A JP4122159B2 (ja) 2002-01-25 2002-01-25 ビルドアップ基板の製造方法

Publications (3)

Publication Number Publication Date
JP2003218533A JP2003218533A (ja) 2003-07-31
JP2003218533A5 JP2003218533A5 (enExample) 2005-08-18
JP4122159B2 true JP4122159B2 (ja) 2008-07-23

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ID=27653243

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JP2002017616A Expired - Fee Related JP4122159B2 (ja) 2002-01-25 2002-01-25 ビルドアップ基板の製造方法

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JP (1) JP4122159B2 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6963414B2 (ja) * 2017-05-29 2021-11-10 株式会社図研 設計支援装置、設計支援方法およびプログラム

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Publication number Publication date
JP2003218533A (ja) 2003-07-31

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