JP4103983B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of forming a transistor having a structure capable of efficiently extracting holes of impact ions generated near a drain in a transistor formed on an SOI wafer. In particular, the present invention relates to a transistor having a so-called source-body-tie structure in which a body-source-tie region is provided in the vicinity of a source region of the transistor.
[0002]
[Prior art]
FIG. 4 shows a manufacturing method of a conventional SOI transistor, and FIG. 5 shows a top view and a cross-sectional view of the structure of the conventional SOI transistor. Here, a transistor is formed using a wafer in which a P-type semiconductor film is formed on a P-type support substrate with a buried insulating film interposed therebetween. As shown in FIG. 5, the conventional SOI transistor is formed in the semiconductor film 1 in the region surrounded by the LOCOS 11 reaching the buried insulating film, and each transistor is completely separated by the LOCOS 11. In the case of an N-type transistor, since the semiconductor film 1 is P-type, the transistor is formed by implanting N-type ions into the source / drain regions 14 and 15. On the other hand, in the case of a P-type transistor, N-type ion implantation is performed on the semiconductor film 1 surrounded by the LOCOS 11, and P-type ions are implanted into the source / drain regions 14 and 15 with the semiconductor film 1 being N-type. A transistor is formed. As shown in FIG. 4, in the manufacturing method, first, a nitride film 8 is formed, patterned, and thermally oxidized to form LOCOS 11. The thickness of the LOCOS 11 is oxidized to a thickness that reaches the buried insulating film 2 on the support substrate 3. Next, ion implantation is performed using the resist 6 as a mask to form the well 7. At this time, the energy of ion implantation is controlled so that a concentration peak comes in the semiconductor film. Next, heat treatment is performed to activate and diffuse the implanted ions. After forming the LOCOS 11, the gate oxide film 13, the gate electrode 12, and the ion implantation into the source / drain regions 14 and 15 of the transistor are performed to form the interlayer insulating film 18. Next, the interlayer insulating film 18 is patterned and etched to form contacts 19 to the gate electrode 12 and the source / drain regions 14 and 15. Further, the wiring 20 is formed.
[0003]
Here, in the SOI transistor, it is necessary to provide a body terminal and fix the potential in order to pull out holes generated by impact ionization in the vicinity of the drain. Therefore, a high-concentration impurity region having the same conductivity type as that of the body is provided in a part of the source as a body terminal to fix the potential. At this time, the body terminal is directly connected to the ground terminal or set to the same potential as the source.
[0004]
As a method of providing a body terminal, there is a method of providing a region for taking a body terminal in the channel width direction of a transistor. In this case, the body terminal is directly connected to the ground terminal.
[0005]
[Problems to be solved by the invention]
In a conventional method for forming an SOI transistor, a semiconductor film serving as a body is thinned to several hundred nm or less in order to obtain steep subthreshold characteristics. In this case, a body terminal is provided to efficiently pull out holes generated by impact ionization. However, since the body is made thin, the resistance increases and a voltage drop occurs in the body, so holes accumulate in the body. Parasitic bipolar phenomenon occurs.
[0006]
Similarly, an SOI transistor having a semiconductor film thinned to several hundred nanometers or less has a high resistance due to the thinning of the source region and the drain region, which increases the voltage drop in the source region and the drain region. There is a demerit that the current value of the transistor decreases.
[0007]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit manufacturing method in which a CMOS transistor is formed on a first conductive type semiconductor film provided via a buried insulating film on a first conductive type support substrate. Etching the body in the vicinity of the drain of the first conductivity type transistor, the drain in the vicinity of the body, and the silicon in the portion that becomes the LOCOS and thermal oxidation reaching the buried oxide film to form LOCOS for element isolation between the transistors Forming a gate oxide film of the first conductivity type transistor; and forming a first conductivity type impurity region reaching the buried insulating film on the semiconductor film in a region where the first conductivity type transistor is to be formed. And a step of forming a second conductive type impurity by forming polysilicon as a gate electrode of the first conductive type transistor Forming a second conductivity type impurity region in the source region and the drain region; forming an interlayer insulating film; forming a contact hole in the source region, the drain region, and the gate electrode; and the interlayer insulation. It consists of a step of forming a wiring on the film.
[0008]
This makes it possible to form a transistor on the semiconductor film that can efficiently extract holes generated in the body while maintaining the steep subthreshold characteristics, similar to the case where the entire body is thinned by thinning the vicinity of the drain. can do.
[0009]
Further, in the transistor manufactured by this manufacturing method, since the semiconductor film remains thick in the contact portions of the source region and the drain region, the voltage drop in the source region and the drain region does not increase. That is, a decrease in the current value of the transistor can be prevented.
[0010]
According to a second aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit, a CMOS transistor is formed on a first conductive type semiconductor film provided on a first conductive type support substrate via a buried insulating film. The body near the drain of the first conductivity type transistor, the drain near the body, and the portion that becomes the LOCOS are thermally oxidized to a thickness that does not reach the buried oxide film, and the thermal oxide film is peeled off and the buried oxide film is reached. A step of forming a LOCOS for performing thermal oxidation to separate elements between transistors; a step of forming a gate oxide film of a first conductivity type transistor; and a region for forming the first conductivity type transistor in the region where the semiconductor film is formed A step of forming a first conductivity type impurity region reaching the buried insulating film, and a step of forming a polycrystal to be a gate electrode of the first conductivity type transistor; Forming a second conductive type impurity; forming a second conductive type impurity region in the source region and the drain region; forming an interlayer insulating film; and The method includes a step of forming a contact hole in the drain region and the gate electrode and a step of forming a wiring on the interlayer insulating film. This makes it easier to control the film thickness of the thin film portion of the semiconductor film of the transistor than etching the silicon to form the thin film portion of the semiconductor film.
[0011]
According to a third aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit, a CMOS transistor is formed on a first conductive type semiconductor film provided on a first conductive type support substrate via a buried insulating film. Etching the body in the vicinity of the drain of the first conductivity type transistor, the drain in the vicinity of the body, and the silicon in the portion that becomes the LOCOS and thermal oxidation reaching the buried oxide film to form LOCOS for element isolation between the transistors Forming a gate oxide film of the first conductivity type transistor; and forming a first conductivity type impurity region reaching the buried insulating film on the semiconductor film in a region where the first conductivity type transistor is to be formed. And a first conductivity type having a concentration higher than that of the impurity region of the first conductivity type in a region serving as a source of the first conductivity type transistor. A step of forming a pure material, a step of forming polysilicon as a gate electrode of the first conductivity type transistor to form a second conductivity type impurity, and a second conductivity type impurity in the source region and the drain region. Forming a region, forming a first conductivity type impurity region in a part of the source region, forming an interlayer insulating film, and forming contact holes in the source region, the drain region, and the gate electrode And a step of forming a wiring on the interlayer insulating film. As a result, since the first conductivity type impurity region serving as the body terminal is formed so as to enter under the source region, a transistor capable of efficiently extracting holes generated by impact ionization in the vicinity of the drain is formed in the semiconductor film. Can be created on top.
[0012]
Furthermore, in the first and second means of the present invention, the first conductivity type impurity region is provided in a part of the source region, but in the third means, a body terminal is provided under the source region of the transistor. Therefore, the area reduction effect is greater than the transistors manufactured by the first means and the second means.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
A first embodiment of the present invention will be described with reference to FIGS.
[0014]
In the method for manufacturing a semiconductor integrated circuit described in the first embodiment of the present invention, an N-type transistor and a P-type transistor are formed on a P-type semiconductor film formed on a P-type support substrate via a buried oxide film. Although the method will be described, the same applies to a method of forming a transistor in an N-type semiconductor film formed on a N-type support substrate through a buried oxide film. That is, it is assumed that the first conductivity type is P type, the second conductivity type is N type, and the first conductivity type is N type and the second conductivity type is P type. Although only an example of an N-type SOI transistor in which the first conductivity type is an N-type is described here, a P-type SOI transistor can also be implemented by forming the conductivity type completely opposite.
[0015]
A method for manufacturing a semiconductor integrated circuit according to the present invention will be described below.
[0016]
As shown in FIG. 1A, the thickness of several thousand provided on the support substrate 3 via the buried insulating film 2 nm On the SOI wafer having the semiconductor film 1, the silicon in the LOCOS forming portion and the portion that becomes the thin film region of the body region and the drain region is etched. First, the thermal oxide film 5 is formed to several hundred nm, and the nitride film 8 is formed to about 1600 nm thereon. Next, alignment & exposure is performed, and patterning is performed on the LOCOS forming portion 111 and portions that become the thin film region 17 of the body region and the drain region. Next, the nitride film 8 is etched using the resist 6 as a mask to form a LOCOS formation portion. 111 And the part which becomes the thin film area | region 17 of a body region and a drain region is opened (FIG. 1 (B)). In this state, as shown in FIG. 1C, the silicon in the LOCOS forming portion 111 and the portion that becomes the thin film region 17 of the body region and the drain region is etched. Etching of silicon is performed to such a depth that the semiconductor film 1 remains on the buried oxide film 2 on the support substrate 3 by about several hundred nm. In addition, the thin film region 17 in the body region and the drain region extends from a portion about 0.1 μm from the portion 141 serving as the source region to a portion about 0.1 μm from the portion 151 serving as the drain region. It is desirable that
[0017]
Next, a LOCOS 11 is formed as shown in FIG. Although not shown, the thermal oxide film 51 is first formed to several hundred nm, and the nitride film 81 is formed to about 1600 nm thereon. Next, alignment & exposure is performed, the nitride film 81 is etched, and the LOCOS formation part is opened. In this state, it is put into a thermal oxidation furnace, and a LOCOS 11 is formed as shown in FIG. The LOCOS 11 is formed so that the LOCOS 11 reaches the buried insulating film 2 on the support substrate 3. After the LOCOS 11 is formed, the remaining nitride film 81 is removed as shown in FIG. 1E, and all the oxide film 51 other than the LOCOS 11 is removed.
[0018]
Next, as shown in FIG. 2A, patterning is performed with a resist 61 on the gate oxide film 13 formed by the gate oxidation process to form an opening for well 7 ion implantation. Further, ion implantation is performed through the gate oxide film 13 using the resist 61 as a mask. As a result, ions are implanted only into the opening of the resist 61. At this time, the energy of ion implantation is adjusted so that the concentration distribution peaks at the thin film portion of the semiconductor film 1.
[0019]
Next, after forming a polysilicon film, alignment & exposure is performed to pattern the gate electrode 12. Further, as shown in FIG. 2B, the polysilicon is etched by dry etching to form the gate electrode 12.
[0020]
Next, as shown in FIG. 2C, a high concentration N-type source region 14 and a drain region 15 are formed in the source region and the drain region by a photolithography process and ion implantation. Further, a high concentration P-type body terminal region 26 is formed in the body terminal region. Thereafter, the process proceeds in the same steps as in a normal CMOS manufacturing process. An interlayer insulating film 18 is formed, and contacts are formed between the source / drain regions 14 and 15 and the body terminal region 26 of the transistor. As shown in FIG. 2D, a resist is applied on the interlayer insulating film 18, alignment & exposure is performed, and the contact 19 is patterned and etched.
[0021]
Next, as shown in FIG. 2E, a metal film is formed, a resist is applied, alignment & exposure is performed, and the wiring 20 is patterned and etched. Thereafter, a protective film is formed on the wiring 20, and bonding pads are formed to complete the semiconductor integrated circuit.
[0022]
The structure of the transistor manufactured as described above is shown in a top view and a cross-sectional view in FIG. In the top view of FIG. 3A, 22 is a mask region for silicon etching, 24 is an N-type impurity implantation region, and 25 is a P-type impurity implantation region. 3B and 3C are cross-sectional views taken along cross-sections AA1 and BB1 in FIG. 3A, respectively. As shown in the transistor cross-sectional view, the transistor has a body-source-tie structure in which a region to be a body terminal 26 is provided in part of the source region 14.
[0023]
By thinning the vicinity of the drain, the steep subthreshold characteristic can be obtained as in the case where the entire body is thinned.
[0024]
Further, since the vicinity of the source is not thinned and remains a thick film, the hole outlet of the body terminal is wide, and holes generated in the body due to impact ionization can be efficiently extracted.
[0025]
Further, since the semiconductor film remains thick in the contact portions of the source region and the drain region, a voltage drop in the source region and the drain region can be suppressed, and a decrease in the current value of the transistor can be prevented. .
[0026]
Next, a second embodiment of the present invention will be described.
[0027]
A method for manufacturing a semiconductor integrated circuit according to the present invention will be described below with reference to FIGS.
[0028]
As shown in FIG. 6A, the thickness of several thousand provided on the support substrate 3 with the embedded insulating film 2 interposed therebetween. nm A thick thermal oxide film is formed on the SOI wafer having the semiconductor film 1 on the LOCOS forming portion and the thin film regions of the body region and the drain region, and a part of the semiconductor film is thinned by peeling the thermal oxide film. To do. First, the thermal oxide film 5 is formed to several hundred nm, and the nitride film 8 is formed to about 1600 nm thereon. Next, alignment & exposure is performed, and patterning is performed on the LOCOS forming portion 111 and portions that become the thin film region 17 of the body region and the drain region. Next, the nitride film 8 is etched using the resist 6 as a mask to form a LOCOS forming portion. 111 And the part which becomes the thin film region 17 of the body region and the drain region is opened (FIG. 6B). In this state, it is put into a thermal oxidation furnace, and as shown in FIG. 6C, a thick thermal oxide film is formed on the LOCOS forming portion 111 and the portions that become the thin film region 17 of the body region and the drain region. The thermal oxide film is formed to such a depth that the semiconductor film 1 remains on the buried oxide film 2 on the support substrate 3 on the order of several hundred nm. In addition, the thin film region 17 in the body region and the drain region extends from a portion about 0.1 μm from the portion 141 serving as the source region to a portion about 0.1 μm from the portion 151 serving as the drain region. It is desirable that
[0029]
Further, the thermal oxide film is wet-etched to strip the nitride film 8 and the thermal oxide film 5. FIG. 6D shows a state where the thermal oxide film is wet etched and the nitride film is peeled off.
[0030]
Next, LOCOS 11 is formed as shown in FIG. Although not shown, the thermal oxide film 51 is first formed to several hundred nm, and the nitride film 81 is formed to about 1600 nm thereon. Furthermore, alignment & exposure is performed and LOCOS 11 is patterned. Next, the nitride film 81 is etched to open the LOCOS formation portion. In this state, it is put into a thermal oxidation furnace to form LOCOS 11 as shown in FIG. The LOCOS 11 is formed so that the LOCOS 11 reaches the buried insulating film 2 on the support substrate 3. After the LOCOS 11 is formed, the nitride film 81 is removed, and all the oxide film 51 other than the LOCOS 11 is removed (FIG. 7A). Next, as shown in FIG. 7B, patterning is performed with a resist 6 on the gate oxide film 13 formed by the gate oxidation process to form an opening for well 7 ion implantation. Next, as shown in FIG. 7B, ion implantation is performed through the gate oxide film 13 using the resist 61 as a mask. As a result, ions are implanted only into the opening of the resist 61. At this time, the energy of ion implantation is adjusted so that the concentration distribution peaks at the thin film portion of the semiconductor film 1.
[0031]
Next, after forming a polysilicon film, alignment & exposure is performed to pattern the gate electrode 12. Further, as shown in FIG. 7C, the polysilicon is etched by dry etching to form the gate electrode 12.
[0032]
Next, as shown in FIG. 7D, a high concentration N-type source region 14 and a drain region 15 are formed in the source region and the drain region by a photolithography process and ion implantation. Further, a high concentration P-type body terminal region 26 is formed in the body terminal region. Thereafter, the process proceeds in the same steps as in a normal CMOS manufacturing process. An interlayer insulating film 18 is formed, and contacts 19 of the source / drain regions 14 and 15 of the transistor are formed. As shown in FIG. 7E, a resist is applied on the interlayer insulating film 18 and alignment & exposure is performed to pattern and etch the contact 19.
[0033]
Next, as shown in FIG. 8, a metal film is formed, a resist is applied, alignment & exposure are performed, and the wiring 20 is patterned and etched. Thereafter, a protective film is formed on the wiring and a bonding pad is formed to complete the semiconductor integrated circuit.
[0034]
The film thickness of the thin film portion of the semiconductor film of the transistor manufactured as described above is determined by the film thickness of the thick thermal oxide film. There is an advantage that the film thickness can be easily controlled.
[0035]
The structure of the transistor manufactured as described above is shown in a top view and a cross-sectional view in FIG. 9A, reference numeral 23 denotes a mask region for forming a thick thermal oxide film, a mask region for silicon etching, 24 is an N-type impurity implantation region, and 25 is This is a P-type impurity implantation region. 9B and 9C are cross-sectional views taken along cross sections AA1 and BB1 in FIG. 9A, respectively. As shown in the transistor cross-sectional view, the transistor has a body-source-tie structure in which a region to be a body terminal 26 is provided in part of the source region 14.
Next, a third embodiment of the present invention will be described.
[0036]
A method for manufacturing a semiconductor integrated circuit according to the present invention will be described below with reference to FIGS.
[0037]
As shown in FIG. 10A, a thickness of several thousand provided on the support substrate 3 with the embedded insulating film 2 interposed therebetween. nm On the SOI wafer having the semiconductor film 1, the silicon in the LOCOS forming portion and the portion that becomes the thin film region of the body region and the drain region is etched. First, the thermal oxide film 5 is formed to several hundred nm, and the nitride film 8 is formed to about 1600 nm thereon. Next, alignment & exposure is performed, and patterning is performed on the LOCOS forming portion 111 and portions that become the thin film region 17 of the body region and the drain region. Next, the nitride film 8 is etched using the resist 6 as a mask to form a LOCOS forming portion. 111 And the part which becomes the thin film area | region 17 of a body region and a drain region is opened (FIG. 10 (B)). In this state, as shown in FIG. 10C, the silicon in the LOCOS forming portion 111 and the portions that become the thin film region 17 of the body region and the drain region are etched. Etching of silicon is performed to such a depth that the semiconductor film 1 remains on the buried oxide film 2 on the support substrate 3 by about several hundred nm. In addition, the thin film region 17 in the body region and the drain region extends from a portion about 0.1 μm from the portion 141 serving as the source region to a portion about 0.1 μm from the portion 151 serving as the drain region. It is desirable that
[0038]
Next, LOCOS 11 is formed as shown in FIG. Although not shown, a thermal oxide film 51 is first formed to several hundred nm, and a nitride film 81 is formed to about 1600 nm thereon. Next, alignment & exposure is performed, the nitride film 81 is etched, and the LOCOS formation part is opened. In this state, it is put into a thermal oxidation furnace to form LOCOS 11 as shown in FIG. The LOCOS 11 is formed so that the LOCOS 11 reaches the buried insulating film 2 on the support substrate 3. After the LOCOS 11 is formed, the nitride film 81 is removed as shown in FIG. 10E, and all the oxide film 51 other than the LOCOS 11 is removed.
[0039]
Next, as shown in FIG. 11A, patterning is performed with a resist 61 on the gate oxide film 13 formed by the gate oxidation process to form an opening for the well 7 ion implantation. Further, ion implantation is performed through the gate oxide film 13 using the resist 61 as a mask. As a result, ions are implanted only into the opening of the resist 61. At this time, the energy of ion implantation is adjusted so that the concentration distribution peaks at the thin film portion of the semiconductor film 1.
[0040]
Next, after forming a polysilicon film, alignment & exposure is performed to pattern the gate electrode 12. Further, as shown in FIG. 11B, the polysilicon is etched by dry etching to form the gate electrode 12.
[0041]
Next, as shown in FIG. 11C, a low concentration P-type body region 161 having a concentration of about 1E17 / cm 3 is formed in the source region.
[0042]
Next, as shown in FIG. 11D, a high concentration N-type source region 14 and a drain region 15 are formed in the source region and the drain region. Further, a high concentration P-type body terminal region 26 is formed in the body terminal region.
[0043]
Thereafter, the process proceeds in the same steps as in a normal CMOS manufacturing process. An interlayer insulating film 18 is formed, and contacts are formed for the source / drain regions 14 and 15 of the transistor. As shown in FIG. 11E, a resist is applied on the interlayer insulating film 18, alignment and exposure are performed, and the contact 19 is patterned and etched.
[0044]
Next, as shown in FIG. 12, a metal film is formed, a resist is applied, alignment & exposure are performed, and the wiring 20 is patterned and etched. Thereafter, a protective film is formed on the wiring and a bonding pad is formed to complete the semiconductor integrated circuit.
[0045]
The structure of the transistor manufactured as described above is shown in a top view and a cross-sectional view in FIG. In the top view of FIG. 13A, 22 is a mask region for silicon etching, 24 is an N-type impurity implantation region, and 25 is a P-type impurity implantation region. FIG. 13B is a cross-sectional view taken along a cross-section AA1 in FIG. As shown in the transistor cross-sectional view, the transistor has a body-source-tie structure in which a region to be a body terminal 26 is provided in part of the source region 14. By thinning the vicinity of the drain, the steep subthreshold characteristic can be obtained as in the case where the entire body is thinned. Further, a P-type impurity region serving as a body terminal is located under the source region, and holes generated by impact ionization near the drain can be efficiently extracted.
[0046]
Further, in the first embodiment and the second embodiment of the present invention, the P-type impurity region is provided in a part of the source region. However, in the third means, a body terminal is provided under the source region. Therefore, the area reduction effect is great.
[0047]
【The invention's effect】
The present invention is implemented in the form described above and has the effects described below.
[0048]
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit manufacturing method in which a CMOS transistor is formed on a first conductive type semiconductor film provided via a buried insulating film on a first conductive type support substrate. Etching the body in the vicinity of the drain of the first conductivity type transistor, the drain in the vicinity of the body, and the silicon in the portion that becomes the LOCOS and thermal oxidation reaching the buried oxide film to form LOCOS for element isolation between the transistors Forming a gate oxide film of the first conductivity type transistor; and forming a first conductivity type impurity region reaching the buried insulating film on the semiconductor film in a region where the first conductivity type transistor is to be formed. And a step of forming a second conductive type impurity by forming polysilicon as a gate electrode of the first conductive type transistor Forming a second conductivity type impurity region in the source region and the drain region; forming an interlayer insulating film; forming a contact hole in the source region, the drain region, and the gate electrode; and the interlayer insulation. It consists of a step of forming a wiring on the film.
[0049]
As a result, the transistor formed on the semiconductor film can obtain the steep subthreshold characteristic similar to the case where the entire body is thinned by thinning the vicinity of the drain.
Further, since the vicinity of the source is not thinned and remains a thick film, the hole outlet of the body terminal is wide, and holes generated in the body due to impact ionization can be efficiently extracted.
[0050]
Further, since the semiconductor film remains thick in the contact portions of the source region and the drain region, a voltage drop in the source region and the drain region can be suppressed, and a decrease in the current value of the transistor can be prevented. .
[0051]
According to a second aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit, a CMOS transistor is formed on a first conductive type semiconductor film provided on a first conductive type support substrate via a buried insulating film. The body near the drain of the first conductivity type transistor, the drain near the body, and the portion that becomes the LOCOS are thermally oxidized to a thickness that does not reach the buried oxide film, and the thermal oxide film is peeled off and the buried oxide film is reached. A step of forming a LOCOS for performing thermal oxidation to separate elements between transistors; a step of forming a gate oxide film of a first conductivity type transistor; and a region for forming the first conductivity type transistor in the region where the semiconductor film is formed A step of forming a first conductivity type impurity region reaching the buried insulating film, and a step of forming a polycrystal to be a gate electrode of the first conductivity type transistor; Forming a second conductive type impurity; forming a second conductive type impurity region in the source region and the drain region; forming an interlayer insulating film; and The method includes a step of forming a contact hole in the drain region and the gate electrode and a step of forming a wiring on the interlayer insulating film. Thus, the transistor formed over the semiconductor film has an advantage that it is easier to control the film thickness of the thin film portion of the semiconductor film than etching the silicon to form the thin film portion of the semiconductor film.
[0052]
According to a third aspect of the present invention, in the method of manufacturing a semiconductor integrated circuit, a CMOS transistor is formed on a first conductive type semiconductor film provided on a first conductive type support substrate via a buried insulating film. Etching the body in the vicinity of the drain of the first conductivity type transistor, the drain in the vicinity of the body, and the silicon in the portion that becomes the LOCOS and thermal oxidation reaching the buried oxide film to form LOCOS for element isolation between the transistors Forming a gate oxide film of the first conductivity type transistor; and forming a first conductivity type impurity region reaching the buried insulating film on the semiconductor film in a region where the first conductivity type transistor is to be formed. And a first conductivity type having a concentration higher than that of the impurity region of the first conductivity type in a region serving as a source of the first conductivity type transistor. A step of forming a pure material, a step of forming polysilicon as a gate electrode of the first conductivity type transistor to form a second conductivity type impurity, and a second conductivity type impurity in the source region and the drain region. Forming a region, forming a first conductivity type impurity region in a part of the source region, forming an interlayer insulating film, and forming contact holes in the source region, the drain region, and the gate electrode And a transistor formed on the semiconductor film, the first conductivity type impurity region serving as a body terminal is located under the source region, and the step of forming a wiring on the interlayer insulating film. Holes generated by impact ionization in the vicinity of the drain can be efficiently extracted.
[0053]
Further, in the first and second means of the present invention, the first conductivity type impurity region is provided in a part of the source region. In the third means, a body terminal is provided under the source region. Therefore, the area reduction effect is great.
[Brief description of the drawings]
FIG. 1 is a process flow diagram showing a first manufacturing method of the present invention.
FIG. 2 is a process flow diagram showing a first manufacturing method of the present invention.
FIGS. 3A and 3B are a top view and a cross-sectional view illustrating a structure of a transistor according to a first manufacturing method of the present invention. FIGS.
FIG. 4 is a process flow diagram showing a conventional manufacturing method.
5A and 5B are a top view and a cross-sectional view illustrating a structure of a transistor in a conventional manufacturing method.
FIG. 6 is a process flow diagram showing a second manufacturing method of the present invention.
FIG. 7 is a process flow diagram showing a second manufacturing method of the present invention.
FIG. 8 is a process flow diagram showing a second manufacturing method of the present invention.
FIGS. 9A and 9B are a top view and a cross-sectional view showing a structure of a transistor in a second manufacturing method of the present invention. FIGS.
FIG. 10 is a process flow diagram showing a third manufacturing method of the present invention.
FIG. 11 is a process flow diagram showing a third manufacturing method of the present invention.
FIG. 12 is a process flow diagram showing a third manufacturing method of the present invention.
13A and 13B are a top view and a cross-sectional view showing a structure of a transistor in a third manufacturing method of the present invention.
[Explanation of symbols]
1 Semiconductor film
2 Embedded insulating film
3 Support substrate
5, 51 Thermal oxide film
6, 61 resist
7 wells
8 Nitride film used for silicon etching of semiconductor film
9 P-type transistor formation region
10 N-type transistor formation region
11 LOCOS
12 Gate electrode
13 Gate oxide film
14 N-type transistor source region
15 N-type transistor drain region
16 N-type transistor body low concentration region
17 Thin region of body region and drain region
18 Interlayer insulation film
19 Contacts
20 Wiring
22 Mask area for silicon etching
23 Mask area for thick thermal oxide film formation
24 N-type impurity implantation region
25 P-type impurity implantation region
26 N-type transistor body terminal area
81 Nitride film for performing LOCOS oxidation
111 LOCOS formation part
141 Transistor source region
151 Transistor drain region
161 Low-concentration P-type impurity implantation region

Claims (3)

In a method for manufacturing a semiconductor integrated circuit, a transistor is formed on a first conductivity type semiconductor film provided on a support substrate via a buried insulating film.
Etching the semiconductor film in a portion to be a thin film region of a drain region of the second conductivity type transistor, a portion to be a thin film region of a body region, and a portion to be a LOCOS;
Forming a LOCOS with an oxide film that opens a portion to become the LOCOS after the nitride film is formed, thermally oxidizes the semiconductor film, and reaches the buried insulating film;
Forming a gate oxide film on the surface of the semiconductor film where the LOCOS is not formed after removing the nitride film;
Forming a gate electrode made of polysilicon on a thick film region of the body region of the second conductivity type transistor and on the thin film region of the body region in contact with the thick film region;
Using the gate electrode as a mask, forming a high-concentration second-conductivity type impurity region to be a source region and a drain region in a region to be the second-conductivity type transistor of the semiconductor film;
Forming a high-concentration first conductivity type impurity region in contact with the body region to be a body terminal region in a part of the source region;
Forming an interlayer insulating film, and forming a contact hole of the source region, the drain region, the body terminal region and the gate electrode in the interlayer insulating film ;
Forming a wiring on the interlayer insulating film. A method of manufacturing a semiconductor integrated circuit, comprising: In a method for manufacturing a semiconductor integrated circuit, a transistor is formed on a first conductivity type semiconductor film provided on a support substrate via a buried insulating film.
Oxidation is performed using the first nitride film having openings as a thin film region in the drain region of the second conductivity type transistor, a thin film region in the body region, and a portion serving as the LOCOS as a mask, on the buried insulating film. Forming an oxide film so that the semiconductor film remains; and
Peeling off the oxide film and the first nitride film formed in the thin film region of the drain region, the thin film region of the body region, and the LOCOS portion of the second conductivity type transistor;
Forming a second nitride film, then opening a portion to be the LOCOS, thermally oxidizing the semiconductor film and forming the LOCOS with an oxide film reaching the buried insulating film;
Forming a gate oxide film on the surface of the semiconductor film where the LOCOS is not formed after removing the second nitride film;
Forming a gate electrode made of polysilicon on a thick film region of the body region of the second conductivity type transistor and on the thin film region of the body region in contact with the thick film region;
Using the gate electrode as a mask, forming a high-concentration second-conductivity type impurity region to be a source region and a drain region in a region to be the second-conductivity type transistor of the semiconductor film;
Forming a high-concentration first conductivity type impurity region in contact with the body region to be a body terminal region in a part of the source region;
Forming an interlayer insulating film, and forming a contact hole of the source region, the drain region, the body terminal region and the gate electrode in the interlayer insulating film ;
Forming a wiring on the interlayer insulating film. A method of manufacturing a semiconductor integrated circuit, comprising: In a method for manufacturing a semiconductor integrated circuit, a transistor is formed on a first conductivity type semiconductor film provided on a support substrate via a buried insulating film.
Etching the semiconductor film in a portion to be a thin film region of a drain region of the second conductivity type transistor, a portion to be a thin film region of a body region, and a portion to be a LOCOS;
Forming a LOCOS with an oxide film that opens a portion to become the LOCOS after the nitride film is formed, thermally oxidizes the semiconductor film, and reaches the buried insulating film;
Forming a gate oxide film on the surface of the semiconductor film where the LOCOS is not formed after removing the nitride film;
Forming a gate electrode made of polysilicon on a thick film region of the body region of the second conductivity type transistor and on the thin film region of the body region in contact with the thick film region;
Forming a first impurity region of a first conductivity type in contact with the thick film region of the body region in a thick film region on the source side of the second conductivity type transistor using the gate electrode as a mask;
Using the gate electrode as a mask, a drain region and a source in a region of the semiconductor film that becomes a drain of the second conductivity type transistor and a portion near the surface of the first impurity region and along the gate electrode, respectively. Forming a second conductivity type impurity region to be a region;
Forming a high-concentration first conductivity type second impurity region to be a body terminal region in a region near the surface of the first impurity region and not occupied by the source region;
Forming an interlayer insulating film, and forming a contact hole of the source region, the drain region, the body terminal region and the gate electrode in the interlayer insulating film ;
Forming a wiring on the interlayer insulating film. A method of manufacturing a semiconductor integrated circuit, comprising:

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