JP4089384B2 - Wiring board manufacturing method - Google Patents

Wiring board manufacturing method Download PDF

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Publication number
JP4089384B2
JP4089384B2 JP2002303015A JP2002303015A JP4089384B2 JP 4089384 B2 JP4089384 B2 JP 4089384B2 JP 2002303015 A JP2002303015 A JP 2002303015A JP 2002303015 A JP2002303015 A JP 2002303015A JP 4089384 B2 JP4089384 B2 JP 4089384B2
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Prior art keywords
insulating adhesive
wiring board
adhesive material
wiring
film
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JP2004140160A (en
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洋 杉本
達也 大高
裕寿 遠藤
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Hitachi Cable Ltd
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Hitachi Cable Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48471—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details

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  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structure Of Printed Boards (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、配線板の製造方法、特に、放熱用の放熱用導体板（以下、放熱板と称する）を有する配線板の製造方法に適用して有効な技術に関するものである。
【０００２】
【従来の技術】
従来、配線板上に半導体チップが実装された半導体装置には、前記半導体チップで発生する熱を外部に放出するための放熱板が設けられた半導体装置がある。前記放熱板が設けられた半導体装置には、例えば、ＴＢＧＡ（Tape Ball Grid Array）と呼ばれる半導体装置がある。
【０００３】
前記ＴＢＧＡと呼ばれる半導体装置には、例えば、絶縁基板の表面に配線（導体パターン）が設けられた配線板と、前記配線板に接着された放熱板と、前記配線板及び前記放熱板に設けられた凹部に収容された半導体チップとからなる半導体装置がある（例えば、非特許文献１参照。）。
【０００４】
前記非特許文献１に示されているＴＢＧＡ型の半導体装置では、例えば、図８に示すように、前記絶縁基板１４の第１主面及びその裏面（以下、第２主面と称する）に配線２が設けられている。このとき、前記絶縁基板１４の第２主面側の配線２、言い換えると、放熱板３が接着された面側の配線２は、例えば、グラウンド電位にする配線が全面的に設けられている。以下、前記絶縁基板１４の第２主面側の配線をグラウンド面２Ｇと称する。このとき、前記絶縁基板１４の第１主面の配線２と前記グラウンド面２Ｇとは、例えば、前記絶縁基板１４に形成されたブラインドビアホールの内部に設けられた導体（ビア）２Ａ、あるいはめっきスルーホールにより電気的に接続されている。
【０００５】
前記非特許文献１に示されているＴＢＧＡ型の半導体装置を製造するときには、大きく分けて、前記半導体装置に用いる配線板を形成する配線板形成工程と、前記配線板形成工程で形成された配線板に半導体チップを実装する半導体チップ実装工程がある。
【０００６】
前記配線板形成工程は、まず、例えば、ポリイミドテープなどのテープ状の絶縁基板１４の第１主面及び第２主面に導体膜を形成した後、あらかじめ定められた位置に、前記絶縁基板１４の第１主面及び前記第２主面に設けられた各導体膜を電気的に接続するビア２Ａあるいはめっきスルーホールを形成する。次に、前記各導体膜の不要な部分を除去して前記配線２や前記グラウンド面２Ｇを形成し、前記絶縁基板１４の半導体チップを収容する領域に開口部を形成する。次に、前記配線２及び前記グラウンド面２Ｇの表面に、例えば、はんだ保護膜（ソルダレジスト）などの保護膜や、はんだめっきなどの接合材を形成する。その後、前記配線板の第２主面、言い換えると前記グラウンド面２Ｇが形成された面に、絶縁性接着剤１５を用いて放熱板３を接着する。このとき、前記放熱板３には、前記配線板の開口部と対応する凹部（座ぐり）３Ａを形成しておく。
【０００７】
また、前記半導体チップ実装工程では、まず、前記配線板の開口部（デバイスホール）５の内部に半導体チップ９を配置し、前記放熱板３の凹部３Ａの底面に前記半導体チップ９を接着する。次に、前記配線２のインナーリード部２Ｂと前記半導体チップ９の外部電極９０１とをボンディングワイヤ１０で電気的に接続し、前記半導体チップ９及び前記ボンディングワイヤ１０による接続部を絶縁樹脂（モールド樹脂）１１で封止する。その後、前記配線板の定められた位置に、ボール状の外部接続端子１２を形成する。
【０００８】
また、前記放熱板３を設けた半導体装置には、前記非特許文献１に示された形態の半導体装置の他に、例えば、銅又はアルミニウムを主成分とする金属板からなるメタルベース上に、有機系絶縁体からなる絶縁層を介して薄膜パターンが設けられた配線板を用いたＭＢＧＡ（Metal Ball Grid Array）と呼ばれる半導体装置がある（例えば、特許文献１参照。）。
【０００９】
【非特許文献１】
大高達也，杉本洋，大森智夫，鈴木幸雄、「画像処理および通信システムＬＳＩ搭載用ＴＢＧＡ（Tape Ball Grid Array）」、日立電線、日立電線株式会社、２０００年１月、Ｎｏ１９、ｐ．７９−８４
【特許文献１】
特開平０８−３０６８２０号公報（第６項、第４図）
【００１０】
【発明が解決しようとする課題】
しかしながら、前記従来の技術のうち、前記非特許文献１に記載された形態の半導体装置に用いる配線板の製造工程には、前記絶縁基板の第１主面及び前記第２主面に導体膜を張り合わせる工程と、前記放熱板を張り合わせる工程がある。このとき、前記導体膜を張り合わせる工程や前記放熱板を張り合わせる工程では、一般に、フィルム状（シート状）の接着剤を用いるか、あるいは前記絶縁基板又は前記導体膜、前記放熱板などの表面に接着剤を塗布する工程が必要である。そのため、工程数が増えるとともに、材料費が増え、前記配線板の製造コストが上昇するという問題があった。
【００１１】
また、前記非特許文献１に記載されたＴＢＧＡ型の半導体装置では、一般に、前記配線板の厚さが７５μｍから１５０μｍ程度、前記放熱板３の厚さが３００μｍから８００μｍ程度である。また、前記配線板と前記放熱板３を接着する絶縁性接着剤１５の厚さは５０μｍから１００μｍ程度である。また、前記ボール状の外部接続端子１２は、例えば、直径が６５０μｍ程度のはんだボールを用いて形成される。そのため、前記半導体装置の厚さＴ６は１mm以上となり、半導体装置の薄型化が難しいという問題があった。
【００１２】
また、前記特許文献１に記載された形態（ＭＢＧＡ型）の半導体装置の場合、前記半導体チップを実装する面と、前記ボール状の外部接続端子を形成する面が異なるとともに、前記半導体チップを実装した面に、中空状のキャップをかぶせている。そのため、半導体装置の薄型化が難しいという問題があった。
【００１３】
本発明の目的は、放熱板を有する配線板の製造コストを低減することが可能な技術を提供することにある。
【００１４】
本発明の他の目的は、放熱板を有する配線板を用いた半導体装置の薄型化が可能な技術を提供することにある。
【００１５】
本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかになるであろう。
【００１６】
【課題を解決するための手段】
本願において開示される発明の概要を説明すれば、以下の通りである。
【００１７】
（１）絶縁体の表面、もしくは表面及び内部に配線（導体パターン）が形成され、前記絶縁体の裏面に、放熱用導体板と外部接続端子が形成された配線板の製造方法であって、導体板の表面に、絶縁性接着材料を用いて導体膜を接着し、前記導体膜の不要な部分を除去して前記配線を形成する前、もしくは前記配線を形成した後、前記導体板の不要な部分を除去して、前記絶縁性接着材料の開口部を覆う放熱用導体板と、前記放熱用導体板と電気的に分離された外部接続端子（ランド）とを形成し、しかる後、前記絶縁性接着材料のあらかじめ定められた領域を開口するとともに、前記放熱用導体板の、前記絶縁性接着材料との接着面側の、前記絶縁性接着材料の開口した領域と重なる領域に凹部を形成する配線板の製造方法である。
【００１８】
前記（１）の手段によれば、導体板に前記絶縁性接着材料で接着した導体膜を用いて前記配線を形成することにより、従来の、例えば、前記非特許文献１に記載された配線板の製造方法に比べて、製造工程及び材料費を低減することができる。そのため、前記配線板の製造コストを低減することができる。
また、前記外部接続端子は、前記放熱用導体板と同じ厚さであり、前記配線の厚さに比べて十分に厚い。また、前記外部接続端子は、前記放熱用導体板と同じ材料であるため、めっきなどで形成する端子（配線）に比べて、表面の平坦性が高い。そのため、前記配線板を用いて半導体装置を製造したときに、前記外部接続端子と他の配線板（実装基板）の配線（端子）との接続性を良くすることができる。
【００１９】
また、前記（１）の手段において、前記配線を形成する前に、あらかじめ定められた位置で、前記導体膜と前記導体板を電気的に接続してもよい。この場合、前記導体膜の不要な部分を除去して配線を形成したときに、前記配線のうち、例えば、グラウンド電位（接地電位）や電源電位などの、特定の電位の配線と前記放熱用の導体板が接続されるようにすれば、前記放熱用の導体板をグラウンド層（面）として用いることができ、マイクロストリップと呼ばれる形態の伝送路を有する配線板を容易に製造することができる。
【００２０】
また、前記（１）の手段において、前記絶縁性接着材料には、例えば、イミド系樹脂のような高耐熱性接着剤を用いることが好ましい。このとき、前記高耐熱性接着剤は、例えば、前記導体膜の表面、あるいは前記導体板の表面に形成（塗布）しておき、熱プレスにより接着する。
【００２１】
また、前記絶縁性接着材料には、フィルム状の絶縁板の両面に絶縁性の接着剤が形成された３層構造の接着フィルムを用いることもできる。前記接着フィルムの場合、中央の前記フィルム状の絶縁板がコア（芯）の役割をするため、接着後の、前記導体膜及び前記絶縁性接着材料、ならびに前記導体板からなる積層体の厚さのばらつきを低減することができる。
【００２２】
また、前記絶縁性接着材料として、フィルム状の絶縁板の両面に絶縁性の接着剤が形成された３層構造の接着フィルムを用いると、中央の前記フィルム状の絶縁板がコア（芯）の役割をするため、前記配線板の厚さのばらつきを低減することができ、前記半導体装置の厚さのばらつきを低減することができる。
【００２３】
以下、本発明について、図面を参照して実施の形態（実施例）とともに詳細に説明する。
【００２４】
なお、実施例を説明するための全図において、同一機能を有するものは、同一符号を付け、その繰り返しの説明は省略する。
【００２５】
【発明の実施の形態】
（実施形態）
図１乃至図３は、本発明による実施形態の配線板の概略構成を示す模式図であり、図１は配線板の平面図、図２は図１のＢ−Ｂ’線での断面図、図３は図２の部分拡大断面図である。
【００２６】
図１乃至図３において、１は絶縁体（絶縁性接着材料）、２は配線、２Ａはビア、２Ｂは配線のインナーリード部、２０１は第１導体膜、２０２は第２導体膜、３は導体板（放熱板）、６Ａは第１接合材、６Ｂは第２接合材、１３は外部接続端子（ランド）である。
【００２７】
本実施形態の配線板は、図１乃至図３に示すように、絶縁体１の第１主面に配線（導体パターン）２が設けられており、前記絶縁体１の第１主面の裏面（以下、第２主面と称する）には、導体板３が設けられている。このとき、前記絶縁体１には、例えば、イミド系樹脂などの高耐熱性接着剤を用いる。以下、前記絶縁体１のことを、絶縁性接着材料と称する。
【００２８】
また、本実施形態の配線板は、半導体チップを実装して半導体装置を製造するときに用いる配線板であり、前記絶縁性接着材料１は、半導体チップが実装される領域（チップ実装領域）４が開口している。
【００２９】
また、前記導体板３は、前記絶縁性接着材料１のチップ実装領域４の開口部１Ａを覆うように設けられており、且つ前記絶縁性接着材料１のチップ実装領域４の開口部１Ａと重なる領域に凹部（座ぐり）３Ａが設けられている。このとき、前記半導体チップは、前記導体板３の凹部３Ａの底面に接着される。すなわち、本実施形態の配線板を用いて半導体装置を製造するときには、前記絶縁性接着材料１の開口部１Ａ及び前記導体板３の凹部３Ａで構成される凹部空間（デバイスホール）５の内部に半導体チップを収容することになる。
【００３０】
またこのとき、前記導体板３の凹部３Ａの深さは、前記配線２の表面から前記放熱板３の凹部３Ａの底面までの距離Ｄ２が１００μｍ程度になる深さであるとする。
【００３１】
また、前記導体板３は、本実施形態の配線板を用いて半導体装置を製造したときに、前記半導体チップから発生する熱を外部に放出しやすくするために設けている。そのため、以下、前記導体板３を放熱板と称する。
【００３２】
また、本実施形態の配線板では、前記絶縁性接着材料１の第２主面の、前記放熱板３の外側の領域に、前記放熱板３とは電気的に分離しており、且つ前記配線２と電気的に接続された外部接続端子（ランド）１３が設けられている。また、前記放熱板３は、図２に示したように、前記配線２のうち、例えば、グラウンド電位（接地電位）や電源電位などの、特定の電位の配線と電気的に接続されているものとする。このとき、前記配線２と前記ランド１３、及び前記配線２と前記放熱板３は、前記絶縁性接着材料１の開口部（ブラインドビアホール）１Ｂの内部に設けられた導体（ビア）２Ａにより電気的に接続されている。
【００３３】
またこのとき、前記配線２は、例えば、図３に示したように、第１導体膜２０１上に第２導体膜２０２が積層された状態になっており、前記絶縁性接着材料１のブラインドビアホール１Ｂ内には、前記第２導体膜２０２が埋め込まれた状態になっている。つまり、前記ビア２Ａは前記第２導体膜２０２でなる。
【００３４】
また、前記配線２は、例えば、半導体装置を製造したときに、半導体チップの外部電極と接続される領域（インナーリード部）２Ｂの表面に、金めっきなどの第１接合材６Ａが設けられている。また、前記配線２の、前記第１接合材６Ａが設けられた領域以外の領域の表面には、はんだ保護膜（ソルダレジスト）などの保護膜７が設けられている。また、前記外部接続端子１３及び前記放熱板３の表面には、例えば、金めっき、錫鉛合金めっき、錫銀合金めっきなどの第２接合材６Ｂが設けられている。
【００３５】
また、本実施形態の配線板でも、前記絶縁性接着材料１の厚さは１０μｍから７５μｍ程度にすることができる。また、前記放熱板３及び前記外部接続端子１３には、例えば、厚さが７５μｍから２５０μｍの銅板を用いることができる。また、前記配線２は、前記第１導体膜２０１の厚さが１２μｍ程度であり、前記第２導体膜２０２の厚さが１５μｍ程度である。このとき、前記絶縁性接着材料１の厚さを２５μｍ、前記放熱板３の厚さを７５μｍとすれば、本実施形態の配線板の厚さＴ３は、前記保護膜７や前記第２接合材６Ｂの厚さを考慮しても、１４μｍから１５０μｍとなる。
【００３６】
図４乃至図６は、本実施形態の配線板の製造方法を説明するための模式図であり、図４（ａ）は積層体を形成する工程の断面図、図４（ｂ）はブラインドビアホールを形成する工程の断面図、図５（ａ）は第２導体膜（ビア）を形成する工程の断面図、図５（ｂ）は配線を形成する工程の断面図、図６（ａ）は放熱板及び外部接続端子を形成する工程の断面図、図６（ｂ）はデバイスホールを形成する工程の断面図である。
【００３７】
以下、図４乃至図６に沿って、本実施形態の配線板の製造方法について説明する。
【００３８】
本実施形態の配線板を製造するときには、まず、図４（ａ）に示すように、導体板３’の一表面に、絶縁性接着材料１を用いて銅箔などの第１導体膜２０１を接着した積層板を形成する。
【００３９】
次に、図４（ｂ）に示すように、前記第１導体膜２０１及び前記絶縁性接着材料１を貫通して前記導体板３’に達する開口部（ブラインドビアホール）１Ｂを形成する。その後、例えば、電気銅めっきにより、前記ブラインドビアホール１Ｂの内部及び前記第１導体膜２０１の表面に第２導体膜２０２を形成して、図５（ａ）に示すように、配線形成用の導体膜２’及び前記配線形成用の導体膜２’と前記導体板３を電気的に接続する導体（ビア）２Ａを形成する。
【００４０】
次に、図５（ｂ）に示すように、前記配線形成用の導体膜２’、すなわち前記第１導体膜２０１とその表面の第２導体膜２０２の不要な部分を除去して配線２を形成する。前記配線２は、一般に、ウェットエッチングにより形成するので、前記エッチングを行う前に、前記導体板３’の表面に溶解を防ぐレジスト（エッチングレジスト）を形成し、エッチング後に前記エッチングレジストを除去する。
【００４１】
次に、図６（ａ）に示すように、前記導体板３’の不要な部分を除去して、前記放熱板３及び前記外部接続端子１３を形成する。前記放熱板３及び前記外部接続端子１３を形成するときも、ウェットエッチングで行うのが一般的であるため、エッチングを行う前に、前記配線２上にレジスト（エッチングレジスト）を形成し、エッチング後に前記エッチングレジストを除去する。
【００４２】
次に、図６（ｂ）に示すように、半導体装置を製造するときに半導体チップを収容する凹部空間であるデバイスホール５を形成する。前記デバイスホール５は、前記絶縁性接着材料１のチップ実装領域４を開口するとともに、前記放熱板３の、前記絶縁性接着材料１のチップ実装領域４の開口部１Ａと重なる領域に凹部３Ａを形成する。このとき、前記絶縁性接着材料１の開口部１Ａ及び前記導体板３の凹部３Ａは、例えば、ルータを用いた座ぐり加工（spot facing）により形成する。また、前記導体板３の凹部３Ａの深さは、例えば、前記配線２の表面から前記凹部３Ａの底面までの距離が１００μｍ程度になるようにする。
【００４３】
その後、図２及び図３に示したように、前記配線２の表面に第１接合材６Ａ及びはんだ保護膜などの保護膜７を形成し、前記放熱板３及び前記外部接続端子１３の表面に、第２接合材６Ｂを形成すると、本実施形態２の配線板が得られる。このとき、前記第１接合材４Ａと前記第２接合材４Ｂは、同種の材料を用いて形成してもよいし、異なる種類の材料を用いて形成してもよい。
【００４４】
図７は、本実施形態の配線板を用いた半導体装置の概略構成を示す模式図である。
【００４５】
本実施形態の配線板を用いて半導体装置を製造するときも、図７に示すように、前記デバイスホール５の底面、すなわち、前記放熱板３の凹部３Ａの底面に、銀ペーストなどの接着剤８を用いて半導体チップ９を接着し、前記配線２のインナーリード部２Ｂと前記半導体チップ９の外部電極９０１をボンディングワイヤ１０で電気的に接続する。その後、前記半導体チップ９及び前記ボンディングワイヤ１０による接続部を絶縁樹脂（モールド樹脂）１１で封止する。
【００４６】
また、本実施形態の配線板を用いた半導体装置は、ＬＧＡ（Land Grid Array）と呼ばれる形態の半導体装置であり、実装基板などに実装するときには、前記外部接続端子１３を、前記実装基板の配線（端子）と直接接続することができる。このとき、前記外部接続端子１３は、前記放熱板３と同じ材料、すなわち、導体板を用いているため、表面の平坦性が高い。そのため、従来のＬＧＡ型の半導体装置に比べて、前記半導体装置を実装するときの実装性が向上する。
【００４７】
また、本実施形態の配線板を用いた半導体装置の場合、前記半導体チップ９を実装する面の裏面に、前記外部接続端子１３が設けられている。そのため、本実施形態の配線板を用いた半導体装置の厚さＴ４は、図７に示したように、前記配線板の厚さＴ３と、前記半導体チップ９が実装された領域の前記絶縁樹脂（モールド樹脂）１１の突出分（隆起分）の高さＴ５の和となる。このとき、前記絶縁性接着材料１の厚さが５０μｍ程度、前記放熱板３の厚さが１００μｍだとすると、前記配線板の厚さＴ３は、１８０μｍから１９０μｍ程度である。またこのとき、前記デバイスホール５の深さは１００μｍ程度であるので、厚さが１００μｍ程度の半導体チップ９を実装した場合、前記半導体チップ９は、ほぼ全体が前記デバイスホール５の内部に収容される。そのため、前記樹脂材料１１の、前記配線板から突出（隆起）した部分の高さＴ５は１００μｍから１２０μｍ程度にすることができ、半導体装置の厚さＴ４を３００μｍ程度にすることができる。
【００４８】
以上説明したように、本実施形態の配線板の製造方法によれば、接着剤を用いて各材料を接着する工程は、前記導体板３の表面に前記第１導体膜２０１を接着する工程のみである。そのため、例えば、従来のＬＧＡ型の半導体装置に用いられる配線板（両面配線板）の製造方法と比べて、製造工程の増加や、材料費の増加を防ぐことができる。また、本実施形態の配線板の製造方法では、前記デバイスホール５を形成する工程を除けば、前記従来の両面配線板と同じ工程数で前記放熱板３も形成することができる。そのため、前記放熱板３が設けられた配線板を容易に製造することができる。
【００４９】
また、本実施形態の配線板は、前記絶縁性接着材料１の厚さを５０μｍ程度、前記導体板（放熱板）３の厚さを１００μｍにすることができるので、本実施形態の配線板を用いたＬＧＡ型の半導体装置の厚さＴ４を１mm以下にすることができる。そのため、例えば、従来のＬＧＡ型の半導体装置に比べて、半導体装置の薄型化が容易になる。
【００５０】
また、本実施形態の配線板では、前記絶縁性接着材料１の厚さを５０μｍ程度としたが、これに限らず、前記絶縁性接着材料１の厚さは、１０μｍから７５μｍ程度にすることができる。また、前記導体板（放熱板）３も、厚さが１００μｍのものに限らず、７５μｍから２５０μｍ程度のものを用いることができる。そのため、前記絶縁性接着材料１の厚さを１０μｍとし、前記導体板（放熱板）３の厚さを７５μｍとすれば、半導体装置の厚さＴ４をさらに薄くすることができる。
【００５１】
また、本実施形態の配線板のように、前記配線２のうち、グラウンド電位（接地電位）などの等電位の配線と前記放熱板３をビア２Ａにより電気的に接続することにより、前記放熱板３をグラウンド層（面）にすることができる。そのため、前記配線板に、マイクロストリップと呼ばれる形態の伝送路を設けることができ、高周波信号（電流）を伝送するときのクロストークノイズ、伝送ロスや遅延を低減することができる。
【００５２】
なお、前記実施形態の配線板の製造方法では、前記配線２を形成した後、前記放熱板３及び前記外部接続端子１３を形成したが、これに限らず、前記放熱板３及び前記外部接続端子１３を形成した後、前記配線２を形成してもよいことは言うまでもない。
【００５３】
また、前記絶縁性接着材料１として、フィルム状の絶縁板の両面に絶縁性の接着剤が形成された３層構造の接着フィルムを用いると、中央の前記フィルム状の絶縁板がコア（芯）の役割をするため、接着後の、前記導体膜及び前記絶縁性接着材料、ならびに前記導体板からなる積層体の厚さのばらつきを低減することができる。そのため、前記配線板のばらつきを低減することができ、前記半導体装置の厚さのばらつきを低減することができる。
【００５４】
以上、本発明を、前記実施形態に基づき具体的に説明したが、本発明は、前記実施形態に限定されるものではなく、その要旨を逸脱しない範囲において、種々変更可能であることはもちろんである。
【００５５】
例えば、前記実施形態の配線板では、前記配線２と前記放熱板３、あるいは前記配線２と前記外部接続端子１３は、ビア２Ａ、すなわち、前記絶縁性接着材料（絶縁体）１に形成したブラインドビアホール１Ｂ内に充填された第２導体膜２０２により電気的に接続したが、これに限らず、めっきスルーホール（plated through hole）により電気的に接続してもよい。
【００５６】
また、前記実施形態の配線板では、前記放熱板３をグラウンド層（面）として用いる例を示したが、例えば、高周波信号（電流）を扱わない場合などは、前記配線２と前記放熱板３を電気的に接続しなくてもよい。
【００５７】
また、例えば、前記実施形態では、前記絶縁性接着材料１の第１主面に前記配線２を設け、前記絶縁性接着材料１の第２主面に前記放熱板３を設けた配線板、すなわち、配線層が２層の配線板（両面配線板）を例に挙げて説明したが、これに限らず、配線層が３層以上の多層配線板に、本発明を適用することもできる。前記多層配線板に適用する場合は、例えば、前記配線２を形成した後、前記配線２が形成された面（第１主面）に、前記絶縁性接着材料１を用いて導体膜を接着し、前記導体膜を用いて新たな配線を形成すればよい。
【００５８】
【発明の効果】
本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば、以下の通りである。
【００５９】
（１）放熱板を有する配線板の製造コストを低減することができる。
【００６０】
（２）放熱板を有する配線板を用いた半導体装置の薄型化が可能である。
【図面の簡単な説明】
【図１】 本発明による実施形態の配線板の概略構成を示す模式図であり、配線板の平面図である。
【図２】 本実施形態の配線板の概略構成を示す模式図であり、図１のＢ−Ｂ’線での断面図である。
【図３】 本実施形態の配線板の概略構成を示す模式図であり、図２の部分拡大断面図である。
【図４】 本実施形態の配線板の製造方法を説明するための模式図であり、図４（ａ）は積層体を形成する工程の断面図、図４（ｂ）はブラインドビアホールを形成する工程の断面図である。
【図５】 本実施形態の配線板の製造方法を説明するための模式図であり図５（ａ）は第２導体膜（ビア）を形成する工程の断面図、図５（ｂ）は配線を形成する工程の断面図である。
【図６】 本実施形態の配線板の製造方法を説明するための模式図であり、図６（ａ）は放熱板及び外部接続端子を形成する工程の断面図、図６（ｂ）はデバイスホールを形成する工程の断面図である。
【図７】 本実施形態の配線板を用いた半導体装置の概略構成を示す模式断面図である。
【図８】 従来のＴＢＧＡ型の半導体装置の概略構成を示す模式断面図である。
【符号の説明】
１ 絶縁体（絶縁性接着材料）
１Ａ チップ実装領域の開口部
１Ｂ ブラインドビアホール
２ 配線
２Ａ ビア
２Ｂ 配線のインナーリード部
２Ｃ 配線の外部端子部
２０１ 第１導体膜
２０２ 第２導体膜
３ 導体板（放熱板）
３Ａ 放熱板の凹部の底面
３’ 導体板
４ 半導体チップを実装する領域
５ 凹部空間（デバイスホール）
６ 接合材
６Ａ 第１接合材
６Ｂ 第２接合材
７ 保護膜
８ 接着剤
９ 半導体チップ
９０１ 半導体チップの外部電極
１０ ボンディングワイヤ
１１ 絶縁樹脂（モールド樹脂）
１２ ボール状の外部接続端子
１３ 外部接続端子（ランド）
１４ 絶縁基板
１５ 絶縁性接着剤[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing a wiring board, in particular, the radiating conductor plate for heat radiation (hereinafter, referred to as the heat sink) to a technique effectively applied to a method of manufacturing a wiring board having a.
[0002]
[Prior art]
Conventionally, a semiconductor device in which a semiconductor chip is mounted on a wiring board includes a semiconductor device provided with a heat radiating plate for releasing heat generated in the semiconductor chip to the outside. An example of a semiconductor device provided with the heat sink is a semiconductor device called TBGA (Tape Ball Grid Array).
[0003]
In the semiconductor device called TBGA, for example, a wiring board provided with wiring (conductor pattern) on the surface of an insulating substrate, a heat sink bonded to the wiring board, and provided on the wiring board and the heat sink. There is a semiconductor device including a semiconductor chip housed in a recessed portion (see, for example, Non-Patent Document 1).
[0004]
In the TBGA type semiconductor device disclosed in Non-Patent Document 1, for example, as shown in FIG. 8, wiring is provided on the first main surface and the back surface (hereinafter referred to as the second main surface) of the insulating substrate 14. 2 is provided. At this time, the wiring 2 on the second main surface side of the insulating substrate 14, in other words, the wiring 2 on the surface side to which the heat radiating plate 3 is bonded, for example, is entirely provided with a ground potential. Hereinafter, the wiring on the second main surface side of the insulating substrate 14 is referred to as a ground surface 2G. At this time, the wiring 2 on the first main surface of the insulating substrate 14 and the ground surface 2G are, for example, a conductor (via) 2A provided inside a blind via hole formed in the insulating substrate 14 or a plated through. It is electrically connected by a hall.
[0005]
When manufacturing the TBGA type semiconductor device shown in Non-Patent Document 1, a wiring board forming process for forming a wiring board used for the semiconductor device and a wiring formed in the wiring board forming process are roughly divided. There is a semiconductor chip mounting process for mounting a semiconductor chip on a plate.
[0006]
In the wiring board forming step, for example, a conductive film is first formed on a first main surface and a second main surface of a tape-shaped insulating substrate 14 such as a polyimide tape, and then the insulating substrate 14 is formed at a predetermined position. Vias 2A or plated through holes for electrically connecting the respective conductor films provided on the first main surface and the second main surface are formed. Next, unnecessary portions of each conductor film are removed to form the wiring 2 and the ground surface 2G, and an opening is formed in a region of the insulating substrate 14 that accommodates the semiconductor chip. Next, a protective film such as a solder protective film (solder resist) or a bonding material such as solder plating is formed on the surfaces of the wiring 2 and the ground surface 2G. Thereafter, the heat radiating plate 3 is bonded to the second main surface of the wiring board, in other words, the surface on which the ground surface 2G is formed using the insulating adhesive 15. At this time, the heat sink 3 is formed with a recess 3A corresponding to the opening of the wiring board.
[0007]
In the semiconductor chip mounting step, first, the semiconductor chip 9 is disposed inside the opening (device hole) 5 of the wiring board, and the semiconductor chip 9 is bonded to the bottom surface of the recess 3 </ b> A of the heat radiating plate 3. Next, the inner lead portion 2B of the wiring 2 and the external electrode 901 of the semiconductor chip 9 are electrically connected by a bonding wire 10, and the connection portion by the semiconductor chip 9 and the bonding wire 10 is insulated resin (mold resin). ) 11 to seal. Thereafter, ball-shaped external connection terminals 12 are formed at predetermined positions on the wiring board.
[0008]
In addition to the semiconductor device of the form shown in Non-Patent Document 1, the semiconductor device provided with the heat sink 3 is, for example, on a metal base made of a metal plate mainly composed of copper or aluminum. There is a semiconductor device called MBGA (Metal Ball Grid Array) using a wiring board provided with a thin film pattern through an insulating layer made of an organic insulator (see, for example, Patent Document 1).
[0009]
[Non-Patent Document 1]
Tatsuya Otaka, Hiroshi Sugimoto, Tomoo Omori, Yukio Suzuki, “TBGA (Tape Ball Grid Array) for Image Processing and Communication System LSI”, Hitachi Cable, Hitachi Cable, Ltd., January 2000, No. 19, p. 79-84
[Patent Document 1]
Japanese Patent Laid-Open No. 08-306820 (Section 6, FIG. 4)
[0010]
[Problems to be solved by the invention]
However, in the conventional technique, in the manufacturing process of the wiring board used for the semiconductor device having the form described in Non-Patent Document 1, conductor films are provided on the first main surface and the second main surface of the insulating substrate. There are a step of pasting and a step of pasting the heat sink. At this time, in the step of laminating the conductor film and the step of laminating the heat dissipation plate, generally, a film-like (sheet-like) adhesive is used, or the surface of the insulating substrate or the conductor film, the heat dissipation plate, etc. The process of apply | coating an adhesive agent to is required. For this reason, there are problems that the number of steps increases, the material cost increases, and the manufacturing cost of the wiring board increases.
[0011]
In the TBGA type semiconductor device described in Non-Patent Document 1, generally, the wiring board has a thickness of about 75 μm to 150 μm, and the radiator plate 3 has a thickness of about 300 μm to 800 μm. The insulating adhesive 15 for bonding the wiring board and the heat sink 3 has a thickness of about 50 μm to 100 μm. The ball-shaped external connection terminal 12 is formed using, for example, a solder ball having a diameter of about 650 μm. For this reason, the thickness T6 of the semiconductor device is 1 mm or more, which makes it difficult to reduce the thickness of the semiconductor device.
[0012]
In the case of the semiconductor device of the form described in Patent Document 1 (MBGA type), the surface on which the semiconductor chip is mounted is different from the surface on which the ball-shaped external connection terminal is formed, and the semiconductor chip is mounted. A hollow cap is put on the surface. Therefore, there is a problem that it is difficult to reduce the thickness of the semiconductor device.
[0013]
The objective of this invention is providing the technique which can reduce the manufacturing cost of the wiring board which has a heat sink.
[0014]
Another object of the present invention is to provide a technique capable of reducing the thickness of a semiconductor device using a wiring board having a heat sink.
[0015]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0016]
[Means for Solving the Problems]
The outline of the invention disclosed in the present application will be described as follows.
[0017]
(1) A method of manufacturing a wiring board in which wiring (conductor pattern) is formed on the surface of the insulator, or on the surface and inside, and on the back surface of the insulator, a heat dissipating conductor plate and external connection terminals are formed. The conductor plate is adhered to the surface of the conductor plate using an insulating adhesive material, and unnecessary portions of the conductor film are removed before forming the wiring by removing unnecessary portions of the conductor film, or after forming the wiring, the conductor plate is unnecessary. Forming a heat-dissipating conductor plate covering the opening of the insulating adhesive material and an external connection terminal (land) electrically separated from the heat-dissipating conductor plate. A predetermined area of the insulating adhesive material is opened, and a concave portion is formed in an area overlapping the area where the insulating adhesive material is opened, on the side of the heat-dissipating conductor plate that is bonded to the insulating adhesive material. It is the manufacturing method of the wiring board to do.
[0018]
According to the means (1), the wiring board is formed by using the conductive film bonded to the conductive board with the insulating adhesive material, so that the conventional wiring board described in Non-Patent Document 1, for example, is used. Compared with this manufacturing method, the manufacturing process and material costs can be reduced. Therefore, the manufacturing cost of the wiring board can be reduced.
The external connection terminal has the same thickness as the heat radiating conductor plate, and is sufficiently thicker than the thickness of the wiring. Further, since the external connection terminal is made of the same material as the heat radiating conductor plate, the surface flatness is higher than a terminal (wiring) formed by plating or the like. Therefore, when a semiconductor device is manufactured using the wiring board, the connectivity between the external connection terminal and the wiring (terminal) of another wiring board (mounting substrate) can be improved.
[0019]
In the means (1), the conductor film and the conductor plate may be electrically connected at a predetermined position before the wiring is formed. In this case, when an unnecessary portion of the conductor film is removed to form a wiring, among the wiring, for example, a wiring having a specific potential such as a ground potential (ground potential) or a power supply potential and the heat radiation If the conductor plates are connected, the heat dissipating conductor plate can be used as a ground layer (surface), and a wiring board having a transmission path called a microstrip can be easily manufactured.
[0020]
In the means (1), it is preferable to use a high heat-resistant adhesive such as an imide resin for the insulating adhesive material. At this time, the high heat-resistant adhesive is formed (coated) on the surface of the conductor film or the surface of the conductor plate, for example, and bonded by hot pressing.
[0021]
The insulating adhesive material may be an adhesive film having a three-layer structure in which an insulating adhesive is formed on both surfaces of a film-like insulating plate. In the case of the adhesive film, since the film-like insulating plate at the center serves as a core, the thickness of the laminated body composed of the conductive film, the insulating adhesive material, and the conductive plate after bonding. Can be reduced.
[0022]
Further, when an adhesive film having a three-layer structure in which an insulating adhesive is formed on both surfaces of a film-like insulating plate is used as the insulating adhesive material, the film-like insulating plate at the center is a core (core). Since it plays a role, variation in the thickness of the wiring board can be reduced, and variation in the thickness of the semiconductor device can be reduced.
[0023]
Hereinafter, the present invention will be described in detail together with embodiments (examples) with reference to the drawings.
[0024]
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted.
[0025]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment)
1 to 3 are schematic views showing a schematic configuration of a wiring board according to an embodiment of the present invention. FIG. 1 is a plan view of the wiring board. FIG. 2 is a cross-sectional view taken along line BB ′ of FIG. FIG. 3 is a partially enlarged sectional view of FIG.
[0026]
1 to 3, 1 is an insulator (insulating adhesive material), 2 is a wiring, 2A is a via, 2B is an inner lead portion of the wiring, 201 is a first conductor film, 202 is a second conductor film, A conductor plate (heat radiating plate), 6A is a first bonding material, 6B is a second bonding material, and 13 is an external connection terminal (land).
[0027]
As shown in FIGS. 1 to 3, the wiring board of the present embodiment is provided with wiring (conductor pattern) 2 on the first main surface of the insulator 1, and the back surface of the first main surface of the insulator 1. (Hereinafter referred to as the second main surface) is provided with a conductor plate 3. At this time, a high heat-resistant adhesive such as an imide resin is used for the insulator 1. Hereinafter, the insulator 1 is referred to as an insulating adhesive material.
[0028]
In addition, the wiring board of this embodiment is a wiring board used when a semiconductor chip is mounted to manufacture a semiconductor device, and the insulating adhesive material 1 is an area (chip mounting area) 4 in which the semiconductor chip is mounted. Is open.
[0029]
The conductor plate 3 is provided so as to cover the opening 1A of the chip mounting region 4 of the insulating adhesive material 1 and overlaps the opening 1A of the chip mounting region 4 of the insulating adhesive material 1. A recess (spot face) 3A is provided in the region. At this time, the semiconductor chip is bonded to the bottom surface of the recess 3 </ b> A of the conductor plate 3. That is, when manufacturing a semiconductor device using the wiring board of the present embodiment, the inside of the opening 1A of the insulating adhesive material 1 and the recess space formed by the concave portion 3A of the conductive plate 3 (device hole) 5 A semiconductor chip is accommodated.
[0030]
At this time, the depth of the concave portion 3A of the conductor plate 3 is assumed to be such that the distance D2 from the surface of the wiring 2 to the bottom surface of the concave portion 3A of the heat sink 3 is about 100 μm.
[0031]
In addition, the conductor plate 3 is provided to easily release the heat generated from the semiconductor chip to the outside when a semiconductor device is manufactured using the wiring board of this embodiment. Therefore, hereinafter, the conductor plate 3 is referred to as a heat sink.
[0032]
Further, in the wiring board of the present embodiment, the second main surface of the insulating adhesive material 1 is electrically separated from the heat radiating plate 3 in a region outside the heat radiating plate 3, and the wiring 2 is provided with an external connection terminal (land) 13 that is electrically connected to 2. Further, as shown in FIG. 2, the heat radiating plate 3 is electrically connected to a wiring having a specific potential such as a ground potential (ground potential) or a power supply potential among the wiring 2. And At this time, the wiring 2 and the land 13 and the wiring 2 and the heat sink 3 are electrically connected by a conductor (via) 2A provided inside an opening (blind via hole) 1B of the insulating adhesive material 1. It is connected to the.
[0033]
At this time, the wiring 2 is in a state in which the second conductive film 202 is laminated on the first conductive film 201 as shown in FIG. 3, for example, and the blind via hole of the insulating adhesive material 1 is formed. The second conductor film 202 is embedded in 1B. That is, the via 2 </ b> A is made of the second conductive film 202.
[0034]
For example, when the semiconductor device is manufactured, the wiring 2 is provided with a first bonding material 6A such as gold plating on the surface of the region (inner lead portion) 2B connected to the external electrode of the semiconductor chip. Yes. A protective film 7 such as a solder protective film (solder resist) is provided on the surface of the wiring 2 other than the region where the first bonding material 6A is provided. Further, on the surfaces of the external connection terminal 13 and the heat radiating plate 3, a second bonding material 6B such as gold plating, tin-lead alloy plating, tin-silver alloy plating, or the like is provided.
[0035]
Also in the wiring board of this embodiment, the thickness of the insulating adhesive material 1 can be about 10 μm to 75 μm. For example, a copper plate having a thickness of 75 μm to 250 μm can be used for the heat radiating plate 3 and the external connection terminal 13. In the wiring 2, the thickness of the first conductor film 201 is about 12 μm, and the thickness of the second conductor film 202 is about 15 μm. At this time, if the thickness of the insulating adhesive material 1 is 25 μm and the thickness of the heat radiating plate 3 is 75 μm, the thickness T3 of the wiring board of the present embodiment is equal to the protective film 7 or the second bonding material. Even when the thickness of 6B is taken into consideration, the thickness is 14 μm to 150 μm.
[0036]
4 to 6 are schematic views for explaining the method of manufacturing the wiring board according to the present embodiment. FIG. 4A is a cross-sectional view of a process of forming a laminate, and FIG. 4B is a blind via hole. 5A is a cross-sectional view of the step of forming the second conductor film (via), FIG. 5B is a cross-sectional view of the step of forming the wiring, and FIG. Sectional drawing of the process of forming a heat sink and an external connection terminal, FIG.6 (b) is sectional drawing of the process of forming a device hole.
[0037]
Hereinafter, the manufacturing method of the wiring board according to the present embodiment will be described with reference to FIGS.
[0038]
When manufacturing the wiring board of the present embodiment, first, as shown in FIG. 4A, the first conductive film 201 such as a copper foil is formed on one surface of the conductive plate 3 ′ using the insulating adhesive material 1. A bonded laminate is formed.
[0039]
Next, as shown in FIG. 4B, an opening (blind via hole) 1B that penetrates the first conductor film 201 and the insulating adhesive material 1 and reaches the conductor plate 3 ′ is formed. Thereafter, the second conductor film 202 is formed inside the blind via hole 1B and on the surface of the first conductor film 201 by, for example, electrolytic copper plating, and as shown in FIG. A conductor (via) 2A for electrically connecting the film 2 ′ and the conductor film 2 ′ for wiring formation and the conductor plate 3 is formed.
[0040]
Next, as shown in FIG. 5B, the wiring 2 is formed by removing the conductive film 2 ′ for forming the wiring, that is, unnecessary portions of the first conductive film 201 and the second conductive film 202 on the surface thereof. Form. Since the wiring 2 is generally formed by wet etching, a resist (etching resist) that prevents dissolution is formed on the surface of the conductor plate 3 ′ before the etching, and the etching resist is removed after the etching.
[0041]
Next, as shown in FIG. 6A, unnecessary portions of the conductor plate 3 ′ are removed to form the heat radiating plate 3 and the external connection terminals 13. Since the heat sink 3 and the external connection terminal 13 are generally formed by wet etching, a resist (etching resist) is formed on the wiring 2 before the etching, and after the etching. The etching resist is removed.
[0042]
Next, as shown in FIG. 6B, when the semiconductor device is manufactured, a device hole 5 which is a recessed space for accommodating a semiconductor chip is formed. The device hole 5 opens the chip mounting region 4 of the insulating adhesive material 1, and has a recess 3 </ b> A in a region overlapping the opening 1 </ b> A of the chip mounting region 4 of the insulating adhesive material 1. Form. At this time, the opening 1A of the insulating adhesive material 1 and the recess 3A of the conductor plate 3 are formed by spot facing using a router, for example. The depth of the recess 3A of the conductor plate 3 is set such that, for example, the distance from the surface of the wiring 2 to the bottom surface of the recess 3A is about 100 μm.
[0043]
Thereafter, as shown in FIGS. 2 and 3, the first bonding material 6 </ b> A and a protective film 7 such as a solder protective film are formed on the surface of the wiring 2, and the heat radiating plate 3 and the external connection terminal 13 are formed on the surface. When the second bonding material 6B is formed, the wiring board of the second embodiment is obtained. At this time, the first bonding material 4A and the second bonding material 4B may be formed using the same type of material, or may be formed using different types of materials.
[0044]
FIG. 7 is a schematic diagram showing a schematic configuration of a semiconductor device using the wiring board of the present embodiment.
[0045]
Even when a semiconductor device is manufactured using the wiring board of the present embodiment, an adhesive such as a silver paste is applied to the bottom surface of the device hole 5, that is, the bottom surface of the recess 3A of the heat radiating plate 3, as shown in FIG. 8 is used to bond the semiconductor chip 9, and the inner lead portion 2 </ b> B of the wiring 2 and the external electrode 901 of the semiconductor chip 9 are electrically connected by the bonding wire 10. Thereafter, the connection portion formed by the semiconductor chip 9 and the bonding wire 10 is sealed with an insulating resin (mold resin) 11.
[0046]
The semiconductor device using the wiring board of the present embodiment is a semiconductor device called LGA (Land Grid Array), and when mounted on a mounting board or the like, the external connection terminal 13 is connected to the wiring of the mounting board. (Terminal) can be connected directly. At this time, since the external connection terminal 13 uses the same material as the heat radiating plate 3, that is, a conductor plate, the surface flatness is high. Therefore, the mounting property when mounting the semiconductor device is improved as compared with the conventional LGA type semiconductor device.
[0047]
In the case of the semiconductor device using the wiring board of this embodiment, the external connection terminal 13 is provided on the back surface of the surface on which the semiconductor chip 9 is mounted. Therefore, as shown in FIG. 7, the thickness T4 of the semiconductor device using the wiring board of this embodiment is equal to the thickness T3 of the wiring board and the insulating resin (in the region where the semiconductor chip 9 is mounted). This is the sum of the height T5 of the protrusion (protrusion) of the mold resin 11. At this time, if the thickness of the insulating adhesive material 1 is about 50 μm and the thickness of the heat sink 3 is 100 μm, the thickness T3 of the wiring board is about 180 μm to 190 μm. At this time, since the depth of the device hole 5 is about 100 μm, when the semiconductor chip 9 having a thickness of about 100 μm is mounted, the semiconductor chip 9 is almost entirely accommodated in the device hole 5. The Therefore, the height T5 of the portion of the resin material 11 protruding (raised) from the wiring board can be set to about 100 μm to 120 μm, and the thickness T4 of the semiconductor device can be set to about 300 μm.
[0048]
As described above, according to the method for manufacturing a wiring board of the present embodiment, the step of bonding each material using an adhesive is only the step of bonding the first conductive film 201 to the surface of the conductive plate 3. It is. Therefore, for example, an increase in manufacturing steps and an increase in material costs can be prevented as compared with a method for manufacturing a wiring board (double-sided wiring board) used in a conventional LGA type semiconductor device. Further, in the method for manufacturing a wiring board according to the present embodiment, the heat radiating plate 3 can be formed by the same number of steps as the conventional double-sided wiring board except for the step of forming the device hole 5. Therefore, the wiring board provided with the heat radiating plate 3 can be easily manufactured.
[0049]
In addition, since the thickness of the insulating adhesive material 1 can be about 50 μm and the thickness of the conductor plate (heat radiating plate) 3 can be 100 μm in the wiring board of this embodiment, The thickness T4 of the used LGA type semiconductor device can be 1 mm or less. Therefore, for example, it is easy to reduce the thickness of the semiconductor device as compared with a conventional LGA type semiconductor device.
[0050]
In the wiring board of this embodiment, the thickness of the insulating adhesive material 1 is about 50 μm. However, the thickness is not limited to this, and the thickness of the insulating adhesive material 1 may be about 10 μm to 75 μm. it can. Further, the conductor plate (heat radiating plate) 3 is not limited to a thickness of 100 μm, and a plate having a thickness of about 75 μm to 250 μm can be used. Therefore, if the thickness of the insulating adhesive material 1 is 10 μm and the thickness of the conductor plate (heat radiating plate) 3 is 75 μm, the thickness T4 of the semiconductor device can be further reduced.
[0051]
Further, like the wiring board of the present embodiment, the heat sink 3 is electrically connected to the heat sink 3 via the via 2A and the wiring 2 having an equipotential such as a ground potential (ground potential). 3 can be a ground layer (plane). Therefore, a transmission path called a microstrip can be provided on the wiring board, and crosstalk noise, transmission loss, and delay when transmitting a high-frequency signal (current) can be reduced.
[0052]
In the method of manufacturing the wiring board according to the embodiment, the heat radiating plate 3 and the external connection terminal 13 are formed after the wiring 2 is formed. However, the present invention is not limited thereto, and the heat radiating plate 3 and the external connection terminal are formed. Needless to say, the wiring 2 may be formed after forming 13.
[0053]
In addition, when an adhesive film having a three-layer structure in which an insulating adhesive is formed on both surfaces of a film-like insulating plate is used as the insulating adhesive material 1, the film-like insulating plate at the center is a core (core). Therefore, it is possible to reduce variations in the thickness of the laminated body composed of the conductor film, the insulating adhesive material, and the conductor plate after bonding. Therefore, variations in the wiring board can be reduced, and variations in the thickness of the semiconductor device can be reduced.
[0054]
The present invention has been specifically described above based on the above embodiment, but the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the present invention. is there.
[0055]
For example, in the wiring board of the embodiment, the wiring 2 and the heat radiating plate 3 or the wiring 2 and the external connection terminal 13 are formed in the via 2A, that is, the blind formed in the insulating adhesive material (insulator) 1. The second conductive film 202 filled in the via hole 1B is electrically connected. However, the present invention is not limited to this, and the second conductive film 202 may be electrically connected by a plated through hole.
[0056]
Moreover, in the wiring board of the said embodiment, although the example which uses the said heat sink 3 as a ground layer (surface) was shown, for example, when not handling a high frequency signal (electric current), the said wiring 2 and the said heat sink 3 May not be electrically connected.
[0057]
Further, for example, in the embodiment, the wiring board in which the wiring 2 is provided on the first main surface of the insulating adhesive material 1 and the heat sink 3 is provided on the second main surface of the insulating adhesive material 1, that is, The wiring board having two wiring layers (double-sided wiring board) has been described as an example. However, the present invention is not limited to this, and the present invention can also be applied to a multilayer wiring board having three or more wiring layers. When applied to the multilayer wiring board, for example, after the wiring 2 is formed, a conductive film is bonded to the surface (first main surface) on which the wiring 2 is formed using the insulating adhesive material 1. What is necessary is just to form a new wiring using the said conductor film.
[0058]
【The invention's effect】
Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
[0059]
(1) The manufacturing cost of a wiring board having a heat sink can be reduced.
[0060]
(2) It is possible to reduce the thickness of a semiconductor device using a wiring board having a heat sink.
[Brief description of the drawings]
FIG. 1 is a schematic diagram showing a schematic configuration of a wiring board according to an embodiment of the present invention, and is a plan view of the wiring board.
FIG. 2 is a schematic diagram showing a schematic configuration of the wiring board of the present embodiment, and is a cross-sectional view taken along the line BB ′ of FIG.
3 is a schematic diagram showing a schematic configuration of the wiring board of the present embodiment, and is a partially enlarged sectional view of FIG.
4A and 4B are schematic views for explaining a method of manufacturing a wiring board according to the present embodiment, in which FIG. 4A is a cross-sectional view of a process for forming a laminate, and FIG. 4B is a process for forming a blind via hole. It is sectional drawing of a process.
5A and 5B are schematic views for explaining a method of manufacturing a wiring board according to the present embodiment, in which FIG. 5A is a cross-sectional view of a process of forming a second conductor film (via), and FIG. It is sectional drawing of the process of forming.
6A and 6B are schematic views for explaining a method of manufacturing a wiring board according to the present embodiment. FIG. 6A is a cross-sectional view of a process of forming a heat sink and external connection terminals, and FIG. It is sectional drawing of the process of forming a hole.
FIG. 7 is a schematic cross-sectional view showing a schematic configuration of a semiconductor device using the wiring board of the present embodiment.
FIG. 8 is a schematic cross-sectional view showing a schematic configuration of a conventional TBGA type semiconductor device.
[Explanation of symbols]
1 Insulator (insulating adhesive material)
DESCRIPTION OF SYMBOLS 1A Opening part of chip mounting area 1B Blind via hole 2 Wiring 2A Via 2B Inner lead part 2C Wiring external terminal part 201 First conductor film 202 Second conductor film 3 Conductor plate (heat sink)
3A Bottom surface of recess of heat sink 3 'Conductor plate 4 Area for mounting semiconductor chip 5 Recessed space (device hole)
6 Bonding Material 6A First Bonding Material 6B Second Bonding Material 7 Protective Film 8 Adhesive 9 Semiconductor Chip 901 External Electrode of Semiconductor Chip 10 Bonding Wire 11 Insulating Resin (Mold Resin)
12 Ball-shaped external connection terminal 13 External connection terminal (land)
14 Insulating substrate 15 Insulating adhesive

Claims (6)

絶縁性接着材料の第１主面に第１導体膜を張り合わせるとともに前記絶縁性接着材料の第２主面に放熱用導体板を張り合わせて積層体を形成し、
前記積層体のあらかじめ定められた位置に、前記第１導体膜側から、前記第１導体膜及び前記絶縁性接着材料を貫通して前記導体板に達する開口部を形成し、
前記導体膜の不要な部分を除去して配線を形成した後、
前記導体板の不要な部分を除去して、前記絶縁性接着材料の開口部を覆う放熱用導体板と、前記放熱用導体板と電気的に分離された外部接続端子とを形成した後、
前記絶縁性接着材料のあらかじめ定められた領域を開口するとともに、前記放熱用導体板の、前記絶縁性接着材料との接着面側の、前記絶縁性接着材料の開口した領域と重なる領域に凹部を形成することを特徴とする配線板の製造方法。 A laminated body is formed by laminating a first conductor film on the first main surface of the insulating adhesive material and laminating a heat radiating conductor plate on the second main surface of the insulating adhesive material,
Forming an opening reaching the conductor plate through the first conductor film and the insulating adhesive material from the first conductor film side at a predetermined position of the laminate,
After removing unnecessary portions of the conductor film to form wiring ,
By removing unnecessary portions of the conductive plate, the heat radiating conductor plate which covers the opening of the insulating adhesive material, after forming the external connection terminal to which the are radiating conductor plate electrically isolated,
A predetermined area of the insulating adhesive material is opened, and a recess is formed in an area overlapping the opening area of the insulating adhesive material on the bonding surface side of the heat radiating conductor plate with the insulating adhesive material. A method of manufacturing a wiring board, comprising forming the wiring board. 前記配線を形成する前に、あらかじめ定められた位置で、前記導体膜と前記導体板を電気的に接続することを特徴とする請求項１に記載の配線板の製造方法。  The method for manufacturing a wiring board according to claim 1, wherein the conductor film and the conductor plate are electrically connected at a predetermined position before the wiring is formed. 前記絶縁性接着材料として、フィルム状の絶縁体の両面に絶縁性の接着剤が形成された接着フィルムを用いることを特徴とする請求項１または請求項２に記載の配線板の製造方法。  The method for manufacturing a wiring board according to claim 1 or 2, wherein an adhesive film in which an insulating adhesive is formed on both surfaces of a film-like insulator is used as the insulating adhesive material. 絶縁性接着材料の第１主面に第１導体膜を張り合わせるとともに前記絶縁性接着材料の第２主面に放熱用導体板を張り合わせて積層体を形成し、
前記積層体のあらかじめ定められた位置に、前記第１導体膜側から、前記第１導体膜及び前記絶縁性接着材料を貫通して前記導体板に達する開口部を形成し、
前記導体板の不要な部分を除去して、前記絶縁性接着材料の開口部を覆う放熱用導体板と、前記放熱用導体板と電気的に分離された外部接続端子とを形成した後、
前記導体膜の不要な部分を除去して配線を形成した後、
前記絶縁性接着材料のあらかじめ定められた領域を開口するとともに、前記放熱用導体板の、前記絶縁性接着材料との接着面側の、前記絶縁性接着材料の開口した領域に凹部を形成することを特徴とする配線板の製造方法。 A laminated body is formed by laminating a first conductor film on the first main surface of the insulating adhesive material and laminating a heat radiating conductor plate on the second main surface of the insulating adhesive material,
Forming an opening reaching the conductor plate through the first conductor film and the insulating adhesive material from the first conductor film side at a predetermined position of the laminate,
After removing unnecessary portions of the conductive plate and forming a conductive plate for heat dissipation covering the opening of the insulating adhesive material, and an external connection terminal electrically separated from the conductive plate for heat dissipation,
After forming the wiring by removing unnecessary portions of the conductive film,
Opening a predetermined region of the insulating adhesive material, and forming a recess in the region where the insulating adhesive material is opened on the side of the heat-dissipating conductor plate that is bonded to the insulating adhesive material. A method of manufacturing a wiring board characterized by the above. 前記配線を形成する前に、あらかじめ定められた位置で、前記導体膜と前記導体板を電気的に接続することを特徴とする請求項４に記載の配線板の製造方法。 Before forming the wiring, in a predetermined position, a manufacturing method of a wiring board according to claim 4, characterized in that electrically connecting the conductor plate and the conductive film. 前記絶縁性接着材料として、フィルム状の絶縁体の両面に絶縁性の接着剤が形成された接着フィルムを用いることを特徴とする請求項４又は請求項５に記載の配線板の製造方法。Wherein the insulating adhesive material, method of manufacturing a wiring board according to claim 4 or claim 5, characterized by using an adhesive film film-like insulating adhesive to both sides of the insulating body is formed.
JP2002303015A 2002-10-17 2002-10-17 Wiring board manufacturing method Expired - Fee Related JP4089384B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04120081U (en) * 1991-02-12 1992-10-27 長瀬 匡夫 simple holder

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Publication number Priority date Publication date Assignee Title
JP5062583B2 (en) * 2005-10-20 2012-10-31 日本ミクロン株式会社 Package for electronic components
JP2015035495A (en) * 2013-08-08 2015-02-19 住友電工デバイス・イノベーション株式会社 Semiconductor device and manufacturing method of the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04120081U (en) * 1991-02-12 1992-10-27 長瀬 匡夫 simple holder

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