JP4086202B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4086202B2 JP4086202B2 JP2005309728A JP2005309728A JP4086202B2 JP 4086202 B2 JP4086202 B2 JP 4086202B2 JP 2005309728 A JP2005309728 A JP 2005309728A JP 2005309728 A JP2005309728 A JP 2005309728A JP 4086202 B2 JP4086202 B2 JP 4086202B2
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- 239000004065 semiconductor Substances 0.000 title claims description 38
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 238000005520 cutting process Methods 0.000 claims description 69
- 239000011347 resin Substances 0.000 claims description 42
- 229920005989 resin Polymers 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 28
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 229910052802 copper Inorganic materials 0.000 claims description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 8
- 238000007789 sealing Methods 0.000 claims description 7
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 229910052763 palladium Inorganic materials 0.000 claims description 4
- 239000000243 solution Substances 0.000 claims description 4
- 229910001030 Iron–nickel alloy Inorganic materials 0.000 claims description 3
- 238000001311 chemical methods and process Methods 0.000 claims 3
- 238000002347 injection Methods 0.000 claims 2
- 239000007924 injection Substances 0.000 claims 2
- 230000002378 acidificating effect Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 description 6
- 238000007598 dipping method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 239000002904 solvent Substances 0.000 description 2
- 230000008961 swelling Effects 0.000 description 2
- 239000003929 acidic solution Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000012670 alkaline solution Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000004382 potting Methods 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
104:マウント部 106:吊り部
108:本体リール部 110:ボンディングワイヤ
112:リード 120:モールド樹脂
130:ブレード 140:切断溝
L:切断面
Claims (14)
- 半導体チップと、マウント部および複数のリードが形成されたリードフレームとを樹脂封止する半導体装置の製造方法であって、
(a)前記リードフレームの各マウント部にそれぞれ半導体チップをマウントし、各半導体チップの電極を対応する前記リードに電気的に接続するステップと、
(b)少なくとも前記リードの一部が露出するように、前記リードフレームおよび複数の半導体チップを樹脂で封止するステップと、
(c)ダイシング用ブレードを切断面に沿って移動させ、少なくとも前記リードを完全に切断し、切断溝を形成する第1の切断ステップと、
(d)前記第1の切断ステップの後、前記切断溝内をデフラッシュするステップと、
(e)前記デフラッシュするステップに引き続いて、ダイシング用ブレードを切断面に沿って移動させ、前記切断溝から樹脂の残りの部分を切断する第2の切断ステップと、
を有する半導体装置の製造方法。 - 前記デフラッシュするステップは、高圧の水を前記切断溝内に噴射する噴射処理を含む、請求項1に記載の製造方法。
- 前記デフラッシュするステップは、前記切断溝に露出されたリードおよび樹脂をアルカリ性または酸性の溶液に晒すケミカル処理を含む、請求項1または2に記載の製造方法。
- 前記ケミカル処理は、一定温度に保持された前記溶液を収容する容器内に、前記切断溝を一定時間浸漬する処理を含む、請求項3に記載の製造方法。
- 前記デフラッシュするステップは、前記ケミカル処理の後に、前記高圧の水を前記切断溝内に噴射する噴射処理を行う、請求項3または4に記載の製造方法。
- 前記切断溝は、切断されたリードの側面と切断された樹脂の底部とを含む、請求項1に記載の製造方法。
- 前記第2の切断ステップのブレードの幅は、前記第1の切断ステップのブレードの幅よりも薄い、請求項1に記載の製造方法。
- 前記第1の切断ステップによる切断面と前記第2の切断ステップによる切断面に段差が形成される、請求項7に記載の製造方法。
- 前記第1の切断ステップは、ブレードを少なくとも100mm/secで移動させる、請求項1に記載の製造方法。
- 前記第2の切断ステップによるブレードの切断速度は、前記第1の切断ステップによるブレードの切断速度よりも速い、請求項1ないし9いずれか1つに記載の製造方法。
- 前記リードフレームは、銅、鉄−ニッケル合金、または半田もしくはパラジウムがメッキされた銅のいずれかを含む、請求項1ないし10いずれか1つに記載の製造方法。
- 前記マウント部は樹脂から露出されている、請求項1ないし11いずれか1つに記載の製造方法。
- 前記半導体装置は、QFNパッケージである、請求項1ないし12いずれか1つに記載の製造方法。
- 前記半導体装置は、SONパッケージである、請求項1ないし12いずれか1つに記載の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005309728A JP4086202B2 (ja) | 2005-10-25 | 2005-10-25 | 半導体装置の製造方法 |
US11/552,351 US7521291B2 (en) | 2005-10-25 | 2006-10-24 | Method for manufacturing a semiconductor device |
US12/400,499 US7851264B2 (en) | 2005-10-25 | 2009-03-09 | Semiconductor device singulation method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005309728A JP4086202B2 (ja) | 2005-10-25 | 2005-10-25 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2007123327A JP2007123327A (ja) | 2007-05-17 |
JP4086202B2 true JP4086202B2 (ja) | 2008-05-14 |
Family
ID=37985880
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005309728A Active JP4086202B2 (ja) | 2005-10-25 | 2005-10-25 | 半導体装置の製造方法 |
Country Status (2)
Country | Link |
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US (2) | US7521291B2 (ja) |
JP (1) | JP4086202B2 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4086202B2 (ja) * | 2005-10-25 | 2008-05-14 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
US7928541B2 (en) | 2008-03-07 | 2011-04-19 | Kobe Steel, Ltd. | Copper alloy sheet and QFN package |
JPWO2009113267A1 (ja) * | 2008-03-14 | 2011-07-21 | パナソニック株式会社 | 半導体装置および半導体装置の製造方法 |
TW200943505A (en) * | 2008-04-02 | 2009-10-16 | Advanced Semiconductor Eng | Reinforced package carrier and method for manufacturing the same as well as method for manufacturing semiconductor packages |
JP5098899B2 (ja) * | 2008-08-28 | 2012-12-12 | サンケン電気株式会社 | 半導体装置の製造方法 |
US8680659B2 (en) | 2009-05-15 | 2014-03-25 | Rohm Co., Ltd. | Semiconductor device |
JP2011216615A (ja) * | 2010-03-31 | 2011-10-27 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP2013069814A (ja) * | 2011-09-21 | 2013-04-18 | Renesas Electronics Corp | 半導体装置の製造方法 |
JP5897454B2 (ja) | 2012-12-03 | 2016-03-30 | Towa株式会社 | 電子部品製造用の切断装置及び切断方法 |
US9437458B2 (en) | 2013-11-12 | 2016-09-06 | Infineon Technologies Ag | Method of electrically isolating leads of a lead frame strip |
US9324642B2 (en) | 2013-11-12 | 2016-04-26 | Infineon Technologies Ag | Method of electrically isolating shared leads of a lead frame strip |
US9287238B2 (en) | 2013-12-02 | 2016-03-15 | Infineon Technologies Ag | Leadless semiconductor package with optical inspection feature |
US9252063B2 (en) * | 2014-07-07 | 2016-02-02 | Infineon Technologies Ag | Extended contact area for leadframe strip testing |
CN105810655A (zh) * | 2014-12-31 | 2016-07-27 | 无锡华润安盛科技有限公司 | 一种引线框引脚切割结构及其切割方法 |
JP7147501B2 (ja) | 2018-11-19 | 2022-10-05 | ローム株式会社 | 半導体装置の製造方法 |
CN112652583A (zh) * | 2019-10-10 | 2021-04-13 | 珠海格力电器股份有限公司 | 一种封装器件及其生产方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
SG80077A1 (en) * | 1998-10-19 | 2001-04-17 | Sony Corp | Semiconductor integrated circuit card manufacturing method, and semiconductor integrated circuit card |
US6812552B2 (en) * | 2002-04-29 | 2004-11-02 | Advanced Interconnect Technologies Limited | Partially patterned lead frames and methods of making and using the same in semiconductor packaging |
US6872599B1 (en) * | 2002-12-10 | 2005-03-29 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
US7049683B1 (en) * | 2003-07-19 | 2006-05-23 | Ns Electronics Bangkok (1993) Ltd. | Semiconductor package including organo-metallic coating formed on surface of leadframe roughened using chemical etchant to prevent separation between leadframe and molding compound |
JP4086202B2 (ja) * | 2005-10-25 | 2008-05-14 | 日本テキサス・インスツルメンツ株式会社 | 半導体装置の製造方法 |
US20070281393A1 (en) * | 2006-05-30 | 2007-12-06 | Viswanadam Gautham | Method of forming a trace embedded package |
-
2005
- 2005-10-25 JP JP2005309728A patent/JP4086202B2/ja active Active
-
2006
- 2006-10-24 US US11/552,351 patent/US7521291B2/en active Active
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2009
- 2009-03-09 US US12/400,499 patent/US7851264B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US7851264B2 (en) | 2010-12-14 |
JP2007123327A (ja) | 2007-05-17 |
US20070092991A1 (en) | 2007-04-26 |
US20090197373A1 (en) | 2009-08-06 |
US7521291B2 (en) | 2009-04-21 |
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