JP4082696B2 - Multilayer electronic component and manufacturing method thereof - Google Patents

Description

  The present invention relates to a multilayer electronic component such as a multilayer chip varistor and a method for manufacturing the same.

  In recent years, with the miniaturization and high performance of electronic devices, multilayer electronic components such as multilayer chip varistors as ESD (electrostatic discharge) components have become indispensable. In recent high-speed interfaces, the structure of the IC itself is becoming vulnerable to ESD in order to achieve high speed. For this reason, in recent years, there has been an increasing demand for ESD countermeasures especially for high-speed transmission ICs.

  As a characteristic required for ESD parts for high-speed transmission systems, it is essential to reduce the capacitance value. The reason is that if the developed capacitance value is large, there is a problem in signal quality, and in the worst case, communication may be disabled.

  Therefore, a technique for reducing the capacitance of the multilayer chip varistor has been proposed.

  For example, Patent Document 1 discloses a technique for reducing the area of an overlapping portion of internal electrodes of a multilayer chip varistor, thereby reducing a region where a capacitance can be formed, and as a result, reducing the developed capacitance. Has been.

  However, if the area of the overlapping portion of the internal electrodes is reduced too much, the ESD tolerance is reduced. This is because the electric field distribution in the overlapping portion of the internal electrodes when a surge voltage such as ESD is applied tends to concentrate on the “end” of the overlapping portion. When the electric field distribution of the overlapping portion is concentrated at the end portion, the ESD tolerance tends to decrease more rapidly as the area of the overlapping portion of the internal electrode decreases.

In view of the above, in recent years, it has been desired to develop a multilayer chip varistor capable of simultaneously reducing a capacitance and ensuring a sufficient ESD resistance.
JP-A-6-13260

  An object of the present invention is to provide a multilayer electronic component such as a multilayer chip varistor that exhibits a small capacitance while maintaining a sufficient ESD tolerance, and a method for manufacturing the same.

  In general, for a varistor of a predetermined size, it is possible to predict the capacitance value that will be obtained from the area of the overlapping portion of the designed internal electrodes. However, the actually obtained capacitance value is usually larger than the predicted capacitance value, as if it were an overlap area larger than the design overlap area. Become. For example, as shown in FIG. 4, the capacitance in the overlapping region of the internal electrodes that express the varistor function (the region expressed as “A” in the present invention) is CA, and the other stacked region B is used. It is necessary to consider that CA + CB is an actually obtained capacitance, where CB is the capacitance of CB. That is, since the relative dielectric constant of the varistor material is usually in the order of several hundreds, CB cannot be ignored as the capacitance decreases.

  The inventors of the present invention have made extensive studies aiming at a structure that reduces the CB value while maintaining the above-mentioned CA characteristics and has little characteristic deterioration even when an abnormal voltage such as ESD is applied. . As a result, it was found that it is effective to control the relative dielectric constant in the element body in the multilayer electronic component. The present invention has been completed based on this finding.

That is, according to the first aspect of the present invention,
A multilayer electronic component having an element body including a zinc oxide-based material layer and at least a pair of internal electrode layers,
The element body is formed between two internal electrode layers adjacent to each other in the stacking direction via the zinc oxide-based material layer and inside the end of the overlapping portion of the internal electrode layers when viewed in plan. Area A and area B other than area A,
Provided is a multilayer electronic component that satisfies the relationship of (εA / εB)> 1.4 when the relative permittivity of each region is region A: εA and region B: εB. .

  In the first aspect, the relative dielectric constant in the multilayer electronic component is controlled within an appropriate range for each part. Specifically, the relative dielectric constants of the region A exhibiting the varistor characteristics and the region B other than the region A within the element body are controlled so as to satisfy a predetermined relationship. For this reason, it is possible to realize a structure with less characteristic deterioration even in an abnormal time when a surge voltage such as ESD is applied while realizing a low capacitance as the whole element.

  The method for controlling the relative dielectric constant of each part in the multilayer electronic component is not particularly limited. For example, it can be realized by a method of diffusing alkali metal from the surface of the element body to the vicinity of the end of the overlapping portion.

  At the site where the alkali metal is diffused, the shape of the double Schottky barrier at the grain boundary that greatly affects the capacitance characteristics of the zinc oxide varistor changes. Specifically, alkali metal has the effect of lowering the electrical conductivity of zinc oxide, which is an n-type semiconductor, so that the area where the alkali metal is diffused has a wider width of the Schottky barrier at the grain boundary. As a result, a reduction in capacitance (decrease in relative dielectric constant) is realized.

According to a second aspect of the invention,
A multilayer electronic component including a zinc oxide-based material layer and at least a pair of internal electrode layers, and having an element body in which an alkali metal is diffused from the surface toward the inside,
The element body is formed between two internal electrode layers adjacent to each other in the stacking direction via the zinc oxide-based material layer and inside the end of the overlapping portion of the internal electrode layers when viewed in plan. Area A and area B other than area A,
When the ionic strength ratio (alkali metal / Zn) of alkali metal and zinc in each region is defined as region A: dB and region B: dB, the relationship (dA / dB) <0.04 is satisfied. A multilayer electronic component is provided.

  In the second aspect, the ionic strength ratio (alkali metal / Zn) of alkali metal and zinc in the multilayer electronic component is controlled within an appropriate range for each part. Specifically, among the regions inside the element body, the ionic strength ratio (alkali metal / Zn) of each alkali metal and zinc in the region A exhibiting varistor characteristics and the region B that is not so is set to a predetermined value. Control to satisfy the relationship.

  The site where the alkali metal is diffused widens the double Schottky barrier at the grain boundary, which has a large effect on the capacitance characteristics of the zinc oxide varistor, and as a result, the capacitance decreases, that is, the relative dielectric constant decreases. To do. As a result, the same effects as the first aspect can be obtained.

  The method of manufacturing the multilayer electronic component in which the ionic strength ratio of alkali metal and zinc (alkali metal / Zn) is controlled is not particularly limited. For example, from the surface of the element body to the vicinity of the end of the overlapping portion. Until the alkali metal is diffused, an external terminal electrode connected to the internal electrode layer may be formed on the outer surface of the element body. Further, after forming the external terminal electrode connected to the internal electrode layer on the outer surface of the formed element body, the alkali metal may be diffused from the surface of the element body to the vicinity of the end of the overlapping portion.

  Preferably, when the alkali metal is diffused, the element body is heat-treated at a temperature of 700 to 1000 ° C. with the powder of the alkali metal compound adhered to the surface of the element body, and the element body And controlling at least one of the amount of the powder adhering to the surface, the heat treatment temperature and the heat treatment time.

  Preferably, the alkali metal is at least one of Li, Na, K, Rb, and Cs. In an n-type semiconductor ZnO varistor, a monovalent metal (alkali metal) such as Li reduces donors and increases a resistance value. In other words, the alkali metal such as Li increases the bandwidth of the grain boundary that controls the capacitance, so that the capacitance can be reduced.

  In the present invention, the multilayer electronic component is not particularly limited, but preferably, the element body has a structure in which zinc oxide-based voltage nonlinear resistor layers and internal electrode layers are alternately stacked, The multilayer electronic component is a multilayer chip varistor.

  The multilayer electronic component of the present invention can be suitably used as an ESD countermeasure component of a high-speed transmission system IC that is compatible with a high frequency of 200 MHz or higher, preferably 700 MHz or higher, more preferably 1 GHz or higher.

  In general, a multilayer chip varistor exhibits varistor characteristics between two internal electrode layers adjacent in the stacking direction in the element body. In the present invention, the relative dielectric constant is lowered by diffusing alkali metal, for example, up to the vicinity between the internal electrode layers that develop varistor characteristics. That is, the alkali metal is intentionally diffused to the vicinity of the inside of the chip (the internal electrode layer exhibiting varistor characteristics) inside the innermost layer in the stacking direction of the internal electrode layers. As described above, the CB in FIG. 4 can be reduced by setting a low relative dielectric constant to the vicinity between the internal electrode layers exhibiting the varistor characteristics. For this reason, the capacitance of the entire chip can be reduced without reducing the overlapping area of the internal electrodes that develop the varistor characteristics.

  As a result, with this structure, the capacity can be reduced without reducing the ESD tolerance. Specifically, a small capacitance of, for example, about 2.0 pF or less can be expressed while maintaining a sufficient ESD tolerance of, for example, 8 kV or more.

Hereinafter, the present invention will be described based on embodiments shown in the drawings.
1 is a schematic sectional view of a multilayer chip varistor according to an embodiment of the present invention, FIG. 2 is a schematic sectional view of the multilayer chip varistor of FIG. 1 divided into regions, and FIG. 3 is an embodiment of the present invention. FIG. 4 is a flowchart illustrating the manufacturing process of the multilayer chip varistor, and FIG. 4 is a diagram illustrating the configuration of the total capacitance in the multilayer chip varistor.

As shown in FIG. 1, a multilayer chip varistor 10 as an example of a multilayer electronic component has an element body 12. A pair of internal electrode layers 2 are disposed inside the element body 12 so as to be opposed to each other via the interlayer voltage nonlinear resistor layer 1 and have an overlapping portion 2a when seen in a plan view. Yes. One end of each internal electrode layer 2 is drawn out to each opposing end face of the element body 12. One end of the drawn internal electrode layer 2 is connected to the external terminal electrode 3 to form a varistor circuit.

  The shape of the element body is not particularly limited, but is usually a rectangular parallelepiped shape. Further, there is no particular limitation on the dimensions, but in particular, 1005 shape (length 1.0 mm × width 0.5 mm × thickness 0.5 mm) or more, for example, 1608 shape (length 1.6 mm × width 0.8 mm × thickness) 0.8mm) size and the like.

The multilayer chip varistor 10 is formed between a pair of internal electrode layers 2 adjacent to each other in the stacking direction in the element body 12 and in a region inside the end portion of the overlapping portion 2a of the internal electrode layer 2 when viewed in plan. A capacitance region having varistor characteristics is formed. Area of the overlapping portion 2a of the internal electrode layer 2 in a plan view in the case of low capacitance products, usually 0.007～0.5Mm ^2, preferably 0.01 to 0.1 mm ² approximately.

  In the present embodiment, a pair of outer voltage nonlinear resistor layers 1 a are stacked on both outer sides of the internal electrode layer 2 in the stacking direction to protect the internal electrode layer 2. The outer voltage non-linear resistor layer 1a is usually made of the same material as the interlayer voltage non-linear resistor layer 1.

  The interlayer voltage nonlinear resistor layer 1 and the outer voltage nonlinear resistor layer 1a are composed of a zinc oxide varistor material layer. This zinc oxide-based varistor material layer has, for example, ZnO as a main component and rare earth elements, Co, IIIb group elements (B, Al, Ga and In), Si, Cr, alkali metal elements (K, Rb and Cs) as subcomponents. ) And alkaline earth metal elements (Mg, Ca, Sr and Ba) and the like. Alternatively, it may be made of a material containing ZnO as a main component and Bi, Co, Mn, Sb, Al, etc. as subcomponents.

  The main component containing ZnO acts as a substance that exhibits excellent voltage nonlinearity in voltage-current characteristics and a large surge resistance. The voltage non-linearity is a phenomenon in which a current flowing through the element increases non-linearly when a gradually increasing voltage is applied between the external terminal electrodes 3.

  The content of ZnO in the resistor layer 1 is not particularly limited, but is usually 99.8 to 69.0% by mass when the total material constituting the resistor layer 1 is 100% by mass. .

  The internal electrode layer 2 includes a conductive material. The conductive material contained in the internal electrode layer 2 is not particularly limited, but is preferably made of Pd or an Ag—Pd alloy. The thickness of the internal electrode layer 2 may be appropriately determined according to the application, but is usually about 0.5 to 5 μm.

  The external terminal electrode 3 is also configured to include a conductive material. Although it does not specifically limit as a electrically conductive material contained in the external terminal electrode 3, Usually, Ag, an Ag-Pd alloy, etc. are used. Further, if necessary, Ni and Sn / Pb films are formed on the surface of the underlayer such as Ag or Ag—Pd alloy by electroplating or the like. The thickness of the external terminal electrode 3 may be appropriately determined according to the application, but is usually about 10 to 50 μm.

  As shown in FIG. 2, the element body 12 is between a pair of internal electrode layers 2 adjacent to each other in the stacking direction via the interlayer zinc oxide-based material layer 1, and when viewed in plan, the element body 12 A region A (capacitance region having varistor characteristics) formed inside the end portion of the overlapping portion 2a and a region B other than the region A are configured.

  In the present embodiment, the relative dielectric constants of these regions A and B are controlled within an appropriate range. Specifically, it is assumed that the relative permittivity of the region A is εA and the relative permittivity of the region B is εB. At this time, (εA / εB)> 1.4, preferably (εA / εB) ≧ 1.5, more preferably (εA / εB) ≧ 2.0, and more preferably (εA / εB) ≧ 5.0. It is controlled to satisfy the relationship.

  The relative permittivity of each region A, B can be controlled, for example, by controlling the ionic strength ratio (alkali metal / Zn) between the alkali metal and zinc in each region A, B within an appropriate range. . As this ionic strength ratio increases, the width of the Schottky barrier at the grain boundary in that region becomes wider and the relative dielectric constant decreases.

  Specifically, as described below, it is preferable to control the ion intensity ratio of each of the regions A and B. That is, in another aspect of the present embodiment, the ionic strength ratio between the alkali metal and zinc in the region A (alkali metal / Zn) is dA, and the ionic strength ratio between the alkali metal and zinc in the region B (alkali metal / Zn). ) Is dB, (dA / dB) <0.04, preferably (dA / dB) ≦ 0.02, more preferably (dA / dB) ≦ 0.005. .

The ionic strength ratio between alkali metal and zinc (alkali metal / Zn) dA, dB can be determined by secondary ion mass spectrometry (SIMS).
SIMS is a method that can measure the ion concentration distribution in the depth direction with high sensitivity on the order of microns from the surface layer. When a solid surface is irradiated with a high energy (several keV to 20 keV) ion beam, the atoms constituting the sample are emitted as neutrons or ions by a sputtering phenomenon. In this way, SIMS is a method of performing elemental analysis and compound analysis of the sample surface by dividing secondaryly released ions into a mass / charge ratio using a mass spectrometer.

  The alkali metal is not particularly limited, but is preferably at least one of Li, Na, K, Rb, and Cs, and more preferably Li.

  The method of manufacturing the multilayer chip varistor 10 in which the ionic strength ratio (alkali metal / Zn) of alkali metal and zinc in each region A, B is controlled is not particularly limited. For example, from the surface of the element body 12, The external terminal electrode 3 connected to the internal electrode layer 2 may be formed on the outer surface of the element body 12 after diffusing the alkali metal to the vicinity of the end of the overlapping portion 2a. Further, after forming the external terminal electrode 3 connected to the internal electrode layer 2 on the outer surface of the formed element body 12, the alkali metal is diffused from the surface of the element body 12 to the vicinity of the end of the overlapping portion 2a. May be.

Manufacturing Method of Multilayer Chip Varistor 10 Next, an example of a manufacturing process of the multilayer chip varistor 10 according to the present invention will be described with reference to FIG.

  First, the interlayer voltage non-linear resistor layer 1 (varistor layer) and the internal electrode layer 2 are alternately formed so that every other internal electrode layer 2 is alternately exposed at both ends by a printing method or a sheet method. The outer voltage non-linear resistance layer 1a is stacked at both ends in the stacking direction to form a stacked body (step a in FIG. 3).

  Next, this laminate is cut to obtain a green chip (step b).

  Next, a binder removal process is performed as necessary, and the green chip is baked to obtain a chip body to be the chip body 12 (step c).

  The obtained chip body is adhered to the surface of the chip body by a sealed rotating pot (step d). Although it does not specifically limit as an alkali metal compound, It is a compound which an alkali metal can diffuse from the surface of the element main body 12 to the edge part vicinity of the overlapping part 2a of the internal electrode layer 2 by heat processing, and oxidation of an alkali metal , Hydroxides, chlorides, nitrates, borates, carbonates and oxalates are used. By appropriately controlling the adhesion amount of the alkali metal compound, the ionic strength ratio of each of the regions A and B can be controlled, and consequently the relative dielectric constant of each of the regions A and B is controlled within an appropriate range.

  Next, the chip body to which the alkali metal compound is adhered is heat-treated in an electric furnace at a predetermined temperature and time (step e). As a result, the alkali metal from the alkali metal compound diffuses from the surface of the chip body to the vicinity of the end of the overlapping portion 2a of the internal electrode layer 2, and the element body 12 is obtained. By appropriately controlling the heat treatment temperature and the heat treatment time, the ionic strength ratio of each of the regions A and B can be controlled, and consequently the relative dielectric constant of each of the regions A and B is controlled within an appropriate range. A preferable heat treatment temperature is 700 to 1000 ° C., and the heat treatment atmosphere is in the air. The heat treatment time (holding time) is preferably 10 minutes to 4 hours.

  Next, an external terminal electrode is applied to both ends of the heat-treated body and baked to form an Ag base electrode (step f). Here, Ag is selected as the base electrode material. However, the element body 12 has good seizure, good connectivity with the material constituting the internal electrode layer 2, and is easily plated in the subsequent plating process. Any material can be used as long as it is a material.

  Finally, a Ni plating film and / or a Sn / Pb plating film is formed on the surface of the base electrode by electroplating (step g) to obtain the multilayer chip varistor 10.

  The means for diffusing the alkali metal from the surface of the element body 12 is not limited to the above means, and for example, the following means can be employed. That is, a method in which the element body 12 before the external terminal electrode 3 is formed is embedded in an alkali supply source and heat-treated, and a method in which an alkali supply source that has been made into a solution by spraying is uniformly sprinkled on the outer periphery of the element body 12 and then heat-treated An example is a method in which air mixed with alkali metal source powder is uniformly sprinkled on the outer periphery of the element body 12 and then heat-treated.

  In these methods, alkali metal diffuses somewhat to the exposed end surfaces of the internal electrode layer 2 exposed at both ends of the element body 12, but this affects the conductivity of the internal electrode layer 2. There is no.

  Note that steps d and e in FIG. 3 may be performed after the external terminal electrode formation (step f). In this case, alkali metal diffusion to the exposed end face of the internal electrode layer 2 can be reliably prevented. As described above, when the external terminal electrode is applied and dried, the alkali metal is adhered to the surface and baking is performed, and the diffusion of the alkali metal into the element body can be simultaneously performed together with baking, thereby simplifying the process.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to such embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in various aspects. .

  For example, in the above-described embodiment, the multilayer chip varistor is exemplified as the multilayer electronic component according to the present invention, but the present invention is not particularly limited thereto.

  Further, as shown in FIG. 1, the present invention is not limited to a laminated chip varistor in which a pair of internal electrode layers are laminated. In FIG. 1, a pair of internal electrode layers are stacked, but a multilayer chip varistor in which a large number of internal electrode layers are stacked may be used.

  Hereinafter, although this invention is demonstrated based on a more detailed Example, this invention is not limited to these Examples.

Example 1
First, in accordance with steps a to c shown in FIG. 3 and a normal method, a chip body to be the element body 12 having a shape 1608 (outer dimensions, length 1.6 mm × width 0.8 mm × thickness 0.8 mm) was formed. The non-linear resistance layer 1 and the outermost layer 1a of the chip body are made of a zinc oxide-based material. Specifically, PrO is added to ZnO (99.725 mol%) with a purity of 99.9%. 0.5 mol%, Co 1.5 mol%, Al 0.005 mol%, K 0.05 mol%, Cr 0.1 mol%, Ca 0.1 mol%, Si 0.1%. The composition was added at a rate of 02 mol%. The internal electrode layer 2 is made of Pd and has an area of the overlapping portion 2a shown in Table 1.

Next, the obtained chip body (sintered body) is mixed with Li ₂ CO ₃ powder (average particle size: 3 μm) as an alkali metal compound in an enclosed rotating pot and mixed on the surface of the chip body. The amount of Li ₂ CO ₃ powder shown in 1 was deposited. The amount of Li ₂ CO ₃ powder introduced into the sealed rotating pot was in the range of 0.01 μg to 10 mg per chip body.

Next, the chip body to which a predetermined amount of Li ₂ CO ₃ powder was adhered was heat-treated in air at the temperature and time shown in Table 1.

  Thereafter, an Ag base electrode is formed by a normal method, and an Ni terminal film and a Sn / Pb plating film are formed on the surface of the base electrode by electroplating to form the external terminal electrode 3, and the multilayer chip varistor 10 is formed. Got.

  Using the obtained multilayer chip varistor samples, the relative permittivity εA, εB of each region A, B (see FIG. 2) and the ionic strength ratio of Li and Zn (Li / Zn) dA, dB The non-linear coefficient α, the capacitance C, and the ESD tolerance were measured. (ΕA / εB) and (dA / dB) were calculated, and the results are summarized in Table 1.

  The ionic strength ratio (Li / Zn) dA, dB was determined by averaging the values in each region by secondary ion mass spectrometry (SIMS).

The non-linear coefficient (α) indicates the relationship between the voltage and current applied between the electrodes of the multilayer chip varistor sample when the current flowing through the multilayer chip varistor sample is changed from 1 mA to 10 mA. . α = log (I ₁₀ / I ₁ ) / log (V10 / V1) = 1 / log (V10 / V1). V10 means a varistor voltage when a current of I ₁₀ = 10 mA is passed through the multilayer chip varistor sample, and V1 is a varistor voltage when a current of I ₁ = 1 mA is passed through the multilayer chip varistor sample. Means. The larger the nonlinear coefficient α, the better the varistor characteristics.

  Capacitance C was measured at 1 MHz. As a result, it was determined that the capacitance was sufficiently reduced to 2.0 pF or less.

For ESD tolerance, static electricity was measured based on a human body model conforming to the IEC61000-4-2 standard. As a result, it was judged that the ESD tolerance was 8 kV or more.

As shown in Table 1, Samples 1 and ₂ were not subjected to a heat treatment process by attaching Li ₂ CO ₃ powder. In such a case, if the area of the overlapping portion 2a of the internal electrode layer 2 is large, the ESD resistance is sufficient, but the capacitance C cannot be reduced. Conversely, when the area of the overlapping portion 2a is reduced, the capacitance C can be reduced, but the ESD tolerance is reduced.

Sample 3 includes the step of heat treatment with Li ₂ CO ₃ powder attached, but the heat treatment time was short. The vicinity of the surface ε mainly decreases, the effect of the present invention cannot be obtained, and the ESD resistance is sufficient, but the capacitance C cannot be reduced.

In Sample 6, the amount of Li ₂ CO ₃ powder deposited was increased and the heat treatment conditions were changed. In this case, Li diffused throughout the region A, and as a result, the entire region A became an insulator and did not exhibit varistor characteristics.

In contrast, in Samples 4 and 5, the amount of Li ₂ CO ₃ powder deposited and the heat treatment conditions are appropriately controlled. For this reason, Li diffuses from the surface of the chip body to the vicinity of the end of the overlapping portion 2a of the internal electrode layer 2 inside the chip body, and as a result, it is small while maintaining a sufficient ESD tolerance. It was confirmed that capacitance can be expressed.

Example 2
A device was fabricated under the same conditions as in Example 1 using Na ₂ CO ₃ , K ₂ CO ₃ , Rb ₂ CO ₃ , and Cs ₂ CO ₃ instead of Li ₂ CO ₃ , and the same evaluation was performed. . As a result, the same result as in Example 1 was obtained.

FIG. 1 is a schematic sectional view of a multilayer chip varistor according to an embodiment of the present invention. FIG. 2 is a schematic sectional view in which the multilayer chip varistor of FIG. 1 is divided into regions. FIG. 3 is a flowchart showing the manufacturing process of the multilayer chip varistor according to one embodiment of the present invention. FIG. 4 is a diagram illustrating the configuration of the total capacitance in the multilayer chip varistor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Interlayer voltage non-linear resistance layer 1a ... Outer voltage non-linear resistance layer 2 ... Internal electrode layer 2a ... Overlapping part 3 ... External terminal electrode 10 ... Multilayer chip varistor 12 ... Element main body

Claims (5)

A pair having an element body including a zinc oxide-based material layer and at least a pair of internal electrode layers and formed on the outer surface of the element body so as to be connected to any one of the pair of internal electrode layers. A multilayer electronic component having a terminal electrode of
The element body is formed between two internal electrode layers adjacent to each other in the stacking direction via the zinc oxide-based material layer and inside the end of the overlapping portion of the internal electrode layers when viewed in plan. Area A and area B other than area A,
The region A and the region B are composed of the same zinc oxide-based material layer,
In the region B, the alkali metal diffuses to the vicinity of the end of the overlapping portion of the internal electrode layers,
When the ionic strength ratio (alkali metal / Zn) between alkali metal and zinc in each region is defined as region A: dB and region B: dB, the relationship (dA / dB) <0.04 is satisfied,
A multilayer electronic component characterized by satisfying a relationship of (εA / εB)> 1.4 when the relative permittivity of each region is defined as region A: εA and region B: εB. The multilayer electronic component according to claim 1 , wherein the alkali metal is at least one of Li, Na, K, Rb, and Cs. 3. The multilayer electronic component according to claim 1 , wherein the zinc oxide-based material layer is a zinc oxide-based voltage nonlinear resistor layer, and the multilayer electronic component is a multilayer chip varistor. A method for producing a multilayer electronic component having an element body including a zinc oxide-based material layer and at least a pair of internal electrode layers,
A region A formed between the two internal electrode layers adjacent to each other in the stacking direction through the zinc oxide-based material layer and inside the end of the overlapping portion of the internal electrode layers when viewed in plan, Heat treatment in a state in which powder of an alkali metal compound is adhered to the surface of the element body composed of the region B other than the region A;
Diffusion of alkali metal from the surface of the element body to the vicinity of the end of the overlapping portion ,
When the relative dielectric constant of each region is defined as region A: εA and region B: εB, the relationship of (εA / εB)> 1.4 is satisfied,
When the ionic strength ratio (alkali metal / Zn) between alkali metal and zinc in each region is defined as region A: dB and region B: dB, the relationship (dA / dB) <0.04 is satisfied. A method of manufacturing a multilayer electronic component characterized by the above.   The external terminal electrode connected to the internal electrode layer is formed on the outer surface of the element body after diffusing alkali metal from the surface of the element body to the vicinity of the end of the overlapping portion. A method of manufacturing a multilayer electronic component.

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