JP4076842B2

JP4076842B2 - Method for manufacturing semiconductor device

Info

Publication number: JP4076842B2
Application number: JP2002333482A
Authority: JP
Inventors: 保彦竹村
Original assignee: Semiconductor Energy Laboratory Co Ltd
Current assignee: Semiconductor Energy Laboratory Co Ltd
Priority date: 1992-07-10
Filing date: 2002-11-18
Publication date: 2008-04-16
Anticipated expiration: 2023-04-16
Also published as: JP2003179074A

Description

【０００１】
【産業上の利用分野】
本発明は、絶縁基板上に絶縁ゲイト型半導体装置およびそれらが多数形成された集積回路を歩留りよく形成する方法、およびそのような方法によって形成された半導体装置に関する。本発明による半導体装置は、液晶ディスプレー等のアクティブマトリクスやイメージセンサー等の駆動回路、あるいはＳＯＩ集積回路や従来の半導体集積回路（マイクロプロセッサーやマイクロコントローラ、マイクロコンピュータ、あるいは半導体メモリー等）における薄膜トランジスタとして使用されるものである。
【０００２】
また、本発明は、広い意味でのアクティブマトリクス（配線がマトリクス状に配置され、その交点に選択のための１つ以上のトランジスタから成る回路が設けられている回路）とそれを駆動するための周辺回路を有する集積化された半導体装置に関する。具体的には、アクティブマトリクス液晶ディスプレー（ＡＭ−ＬＣＤ）や、ＤＲＡＭ、ＳＲＡＭ、ＥＰＲＯＭ、ＥＥＰＲＯＭ、マスクＲＯＭ等の半導体集積回路で、絶縁基板上に形成されたものである。
【０００３】
【従来の技術】
近年、絶縁基板上に絶縁ゲイト型半導体装置（ＭＯＳＦＥＴ）を形成する研究が盛んに成されている。このように絶縁基板上に半導体集積回路を形成することは回路の高速駆動の上で有利である。なぜなら、従来の半導体集積回路の速度は主として配線と基板との容量（浮遊容量）によって制限されていたのに対し、絶縁基板上ではこのような浮遊容量が存在しないからである。このように絶縁基板上に形成され、薄膜状の活性層を有するＭＯＳＦＥＴを薄膜トランジスタ（ＴＦＴ）という。従来の半導体集積回路においても、例えばＳＲＡＭの負荷トランジスタとしてＴＦＴが使用されている。
【０００４】
また、最近になって、透明な基板上に半導体集積回路を形成する必要のある製品が出現した。例えば、液晶ディスプレーやイメージセンサーというような光デバイスの駆動回路である。ここにもＴＦＴが用いられている。これらの回路は大面積に形成することが要求されるのでＴＦＴ作製プロセスの低温化が求められている。また、例えば、絶縁基板上に多数の端子を有する装置で、該端子を半導体集積回路に接続する必要がある場合にも、実装密度を低減するために、半導体集積回路の最初の方の段、あるいは半導体集積回路そのものを、同じ絶縁基板上にモノリシックに形成することも考えられている。
【０００５】
従来、ＴＦＴは、アモルファスもしくはセミアモルファス、あるいは微結晶の半導体被膜を４５０℃〜１２００℃の温度でアニールすることによって、結晶性を改善し、良質な（すなわち、移動度の十分に大きな）半導体被膜に改善することがなされてきた。半導体被膜にアモルファス材料を使用するアモルファスＴＦＴもあるが、移動度が５ｃｍ^２／Ｖｓ以下、通常は１ｃｍ^２／Ｖｓ程度と小さく、動作速度の点からで、また、Ｐチャネル型のＴＦＴが得られない点からその利用は大きく制限されている。移動度が５ｃｍ^２／Ｖｓ以上のＴＦＴを得るには、上記のような温度でのアニールが必要であった。また、このようなアニールによってＰチャネル型ＴＦＴ（ＰＴＦＴ）を形成することができた。あるいは、これらの熱的なアニール工程はレーザー光または強光を照射することによっても成された。
【０００６】
当該アニール工程において、例えば、ＫｒＦエキシマーレーザーのようなパルスレーザ光でなく、強光の照射によって行うアニール方法はＲＴＡ（ラピッドサーマルアニール）と呼ばれ、赤外光、特に１μｍ〜２μｍにピークを有する赤外光（好ましくはハロゲン光（１．３μｍ））を利用して、シリコン半導体を選択的に加熱する方法である。
【０００７】
ＲＴＡ（ラピッドサーマルアニール）法に関連する先行技術文献情報としては、例えば、特許文献１や特許文献２が知られている。
【０００８】
しかしながら、このようなＴＦＴにおいては、オフ状態での大きなリーク電流のため、アクティブマトリクスとして利用するには信頼性の点で問題があることが指摘されていた。このような背景のもと、本発明人等は特願平４−３４１９４もしくは同４−３０２２０に記述されるように、ゲイト電極をアルミニウム等の低抵抗の金属材料で構成するとともに、この表面を陽極酸化することによって酸化物で被覆し、このような金属／酸化物構成体を主たるマスクとして不純物の導入をおこなうことによってオフセット領域を形成する方法を提案した。この結果、リーク電流を削減するとともに、陽極酸化膜によって層間の絶縁が強化され、クロス部分でのショートを著しく減少せしめることが可能となった。
【０００９】
すなわち、陽極酸化物の被膜にはピンホールが少なく、また、耐圧性も非常に高い（７ＭＶ／ｃｍ以上）ので、層間を確実に絶縁できる。実際に特願平４−３４１９４もしくは同４−３０２２０の技術を採用することによって、配線間ショートによる不良を著しく低減させることができた。アクティブマトリクス領域では、配線が交差する箇所が非常に多いので特に重要であった。
【００１０】
【特許文献１】
特開平４−９４５３２号公報（第２頁「実施例」）
【００１１】
【特許文献２】
特開平３−１８００２６号公報（特許請求の範囲、第２頁「実施例」）
【００１２】
【発明が解決しようとする課題】
しかし、本発明人等がこの技術を用いて、アクティブマトリクスとその周辺駆動回路がモノリシックに形成されたデバイス（例えば、メモリーやＡＭ−ＬＣＤ）を作製しようとすると、技術的に非常に困難な課題があることが判明した。
【００１３】
一般に、周辺回路の構成・配線接続は複雑であり、金属電極を陽極酸化物によって被覆する構成を取ろうとしても、配線の複雑さのために電流を給電することができず、また、無理に陽極酸化のためだけに配線を形成すると、その配線を除去するためのフォトリソ工程が余分に必要となり、歩留りの低下を招く。また、このように余分な配線を設けて回路を構成すると、集積度を著しく低下させることとなった。
【００１４】
しかし、例えば、アクティブマトリクス回路部では、陽極酸化工程を採用し、周辺回路部等のその他の領域では陽極酸化工程を採用しないという方法も提案されたが、歩留りが著しく低かった。これは、主として、層間絶縁物が不完全なために、ピンホールが多く存在し、このようなピンホールを通して、上部の配線と下部の配線（ゲイト電極とその配線等）がショートしてしまうためであることが判明した。
【００１５】
特にこれは低融点の金属配線を使用する限りにおいて本質的な問題であった。ゲイト電極材料としてアルミニウムやその合金が優れていることは周知の事実であるが、この材料をゲイト電極として自己整合的に不純物元素を導入するという方法を採用すれば、熱アニールによる活性化は採用できず、必然的に不純物元素の活性化にはレーザーアニール等の低温活性化技術を採用しなければならなかった。また、４５０℃以上での層間絶縁膜の形成は利用できなかった。
【００１６】
例えば、基板温度を４５０℃以上にして、ＬＰＣＶＤ法やＡＰＣＶＤ法によって形成された酸化珪素等の層間絶縁材料では、ピンホールが極めて少なく配線間のショートもほとんどなかった。しかしながら、４５０℃以下の低温ではスパッタ法やプラズマＣＶＤ法しか採用できず、これらの方法では、成膜中に被膜にダストが多く降り注ぎ、結果的にピンホールが非常に多く、絶縁性に問題のある被膜となってしまった。周辺駆動回路部であっても配線の交差は存在し、したがって、歩留りの向上のために何らかの方法によって配線間のショートがないようにすることが望まれる。
さらに、基板としてガラス基板を用いた場合、ガラス基板に熱的なダメージを与えることなくシリコン膜に対するアニールを行うこと、数秒〜数分間の短い時間の照射で効果を上げることも望まれる。
【００１７】
【課題を解決するための手段】
本発明はこのような問題に鑑みて、最適な作製プロセスを提供せんとしてなされたものである。
本発明は、アクティブマトリクスとそれを駆動するための周辺回路を有する半導体装置の作製方法であって、前記周辺回路の薄膜トランジスタは、ガラス基板上にアモルファス状のシリコン膜を形成し、前記シリコン膜を加熱処理によって結晶化し、前記結晶化されたシリコン膜をパターニングすることによって複数の島状シリコン膜を形成し、前記複数の島状シリコン膜をパターニングすることによって複数の島状シリコン膜を形成し、前記複数の島状シリコン膜上にゲイト絶縁膜を形成し、厚さ１００ｎｍ以上の陽極酸化膜が上面のみに形成された金属膜でなるゲイト電極を前記ゲイト酸化膜上に形成した後、前記複数の島状シリコン膜に前記ゲイト電極をマスクとしてｎ型不純物として燐を導入し、前記燐が導入された島状シリコン膜のうち、Ｎチャネル型の薄膜トランジスタが形成される一部の上面にフォトレジストを形成し、前記フォトレジストが形成された状態で前記フォトレジストが形成されていない前記島状シリコン膜に前記フォトレジスト及び前記ゲイト電極をマスクとして前記ｎ型不純物のドーズ量よりも多いドーズ量でｐ型不純物として硼素を導入した後、前記複数の島状シリコン膜にパルスレーザー光を照射することによって作製されることを特徴とするものである。
【００１８】
また、特願平４−３４１９４もしくは同４−３０２２０のように陽極酸化物を設けることによって得られる最大の特徴は、明細書にも示されている通り、オフセットの効果によってゲイトに逆電圧が印加されたときのリーク電流を著しく低減できるということであった。このような特性は、画素の電圧を確実に保持する必要のあるダイナミックな動作をするアクティブマトリクス領域のＴＦＴには必要なことであった。あるいはフリップ・フロップ回路の待機時の消費電力を抑える上では必要なことであった。その意味で、このような構造のＴＦＴをＡＭ−ＬＣＤの画素トランジスタやＳＯＩ技術で形成されるＤＲＡＭの記憶ビットの選択トランジスタやＳＲＡＭ（特に完全ＣＭＯＳ型ＳＲＡＭ）の記憶ビットのインバータ回路を構成するトランジスタに用いることによって、大きな効果が得られた。
しかしながら、周辺回路においては、特にスタティックもしくは半スタティックな動作をおこなう回路であれば、リーク電流はそれほど問題とならない。したがって、少なくとも側面に陽極酸化物を設けなくても（オフセット構造としなくても）十分に回路は動作する。
【００１９】
しかし、ゲイト電極の上面に陽極酸化物等の緻密な被膜がないと配線間のリークによって歩留りが著しく低下してしまう。また、上記特許出願の明細書においても述べられたように、レーザーアニールを採用する場合には、ゲイト電極の上面に陽極酸化物が存在することによって、レーザーアニール工程によるダメージを最小とすることができた。
【００２０】
本発明人等の知見では、電子ビーム蒸着法によって形成された金属アルミニウム膜は表面が平坦で粒径がサブミクロン以下であるので、特に紫外線の反射が良好で、直接レーザー照射をおこなってもほとんどダメージは認められなかったが、スパッタ法等の方法で形成された粒径の大きな（〜１μｍ）被膜では、非常に大きなダメージが観測された。しかし、電子ビーム蒸着法は量産性に劣っているので、実用的にはスパッタ法によって作製することが望まれる。すなわち、周辺回路にとっては、ゲイト電極の側面の陽極酸化物は不要であるが、上面には必要である。
【００２１】
そこで本発明では、ゲイト電極の側面には陽極酸化物が実質的に存在せず、上面にのみ陽極酸化物等の緻密な被膜が存在する構造を有するＴＦＴをアクティブマトリクス領域のＴＦＴとともに形成することを提案する。そのような構造を有するＴＦＴおよびその集合体としてのデバイスの作製方法は以下のように行えばよい。
【００２２】
まず、島状の半導体領域およびゲイト絶縁膜上にアルミニウム等の金属被膜を形成する。そして、その表面に陽極酸化法によって酸化膜を形成する。本発明人等の知見によると酸化物の厚さは１００ｎｍ以下では組成が化学量論比と異なるために絶縁性が悪いので、絶縁物の厚さは１００ｎｍ以上であることが望ましかった。
【００２３】
その後、上記酸化物および金属被膜をエッチングして所望の形状のゲイト電極とすれば、ゲイト電極の上面には陽極酸化物を残し、側面には陽極酸化物のない構造とすることができる。
【００２４】
これらのエッチングには反応性イオンエッチング（ＲＩＥ）等の方向性エッチング方法が良い。これは、等方的なエッチング法では陽極酸化物と金属被膜のエッチングレートの違いによって、その界面付近に空孔（カスプ）が生じ、これをまたぐ上部の配線の断線が発生しやすくなるためである。しかし、材料によっては、全てのプロセスをＲＩＥ等で行えない場合も存在する。
【００２５】
例えば、金属材料がアルミニウムの場合には陽極酸化物は酸化アルミニウムであるが、これはＲＩＥによって除去できない。そこで、この場合には、まず、ウェットエッチングによって酸化アルミニウム膜をエッチングし、その後、残存した酸化アルミニウムをマスクとして、ＲＩＥによって金属アルミニウムをエッチングすればよい。
【００２６】
もし、金属アルミニウムのエッチングにＲＩＥを採用できず、ウェットエッチングにのみ頼る場合には、金属アルミニウム膜ができるだけ薄くすることが望まれる。具体的には酸化アルミニウム膜と金属アルミニウムの膜厚の比が１：３以下、好ましくは１：２以下であることが望まれる。
【００２７】
このようなＴＦＴを用いてモノリシックなマトリクス回路を構成しようとすれば、以下のように行えばよい。第１の方法は以下に示すプロセスから構成される。
▲１▼ 周辺回路にもマトリクス領域にも同じように金属被膜を形成する。
▲２▼ これを陽極酸化して、表面に陽極酸化物を形成する。
▲３▼ 不要な箇所の陽極酸化物をエッチングする。
▲４▼ 残存した陽極酸化物をマスクとして金属被膜をエッチングし、周辺回路部およびマトリクス部にゲイト電極を形成する。
▲５▼ マトリクス部にのみ電流を通じて、マトリクス部のゲイト電極のみに側面にも陽極酸化物を形成する。
【００２８】
この方法においては、マトリクス部に注目すると、最初に工程▲２▼で形成された陽極酸化物がゲイト電極上に残存したまま、工程▲５▼によって第２の陽極酸化をおこなうので、この最初の陽極酸化物とその後に形成される陽極酸化物の間で応力歪みが生じ、最初に形成された上部の陽極酸化物が剥離してしまうことがある。
【００２９】
これを解決するには、実施例１に示すように、工程▲４▼の後に、▲４▼’周辺回路部にのみマスクをして、マトリクス部の陽極酸化物を除去するという工程を付加すればよい。このような工程を経ることによって、マトリクス部のゲイト電極は金属材料が全面にわたって露出し、▲５▼によって、上面、側面に均一に陽極酸化物が形成される。マトリクス部のみをマスクすることは容易であり、この工程を追加することによって、歩留りが低下してしまうことはない。ただし、エッチャントの種類に依っては、この工程でゲイト絶縁膜までエッチングされてしまう。もし、半導体領域の表面が露出した場合には、歩留りの低下の原因となるので注意が必要である。また、いずれにしろ、少なくとも２回の陽極酸化工程が必要である。
【００３０】
第２の方法は、実施例２の方法であるが、主として以下のようなプロセスから構成される。
▲１▼ 周辺回路部には全体的に金属被膜を形成し、マトリクス部にはゲイト電極の形状のままに金属被膜を形成する。
▲２▼ 周辺回路部の金属被膜とマトリクス部のゲイト電極（とその配線）に電流を通じて、陽極酸化物を形成する。
▲３▼ 周辺回路部の陽極酸化物と金属被膜をエッチングして、周辺回路部のゲイト電極を形成する。
【００３１】
この方法では、陽極酸化工程は１回であるが、フォトリソグラフィーの工程が、（主として）マトリクス部のゲイト電極形成と周辺回路部のゲイト電極形成のために、少なくとも２回必要である。
【００３２】
【実施例】
〔実施例１〕基板（コーニング７０５９、３００ｍｍ×３００ｍｍもしくは１００ｍｍ×１００ｍｍ）１０１上に下地酸化膜１０２として厚さ１００〜３００ｎｍの酸化珪素膜を形成した。この酸化膜の形成方法としては、酸素雰囲気中でのスパッタ法やＴＥＯＳをプラズマＣＶＤ法で分解・堆積した膜を４５０〜６５０℃でアニールしてもよい。
【００３３】
その後、プラズマＣＶＤ法やＬＰＣＶＤ法によってアモルファス状のシリコン膜を３０〜１５０ｎｍ、好ましくは５０〜１００ｎｍ堆積し、さらに、プラズマＣＶＤ法によって、保護層として、厚さ２０〜１００ｎｍ、好ましくは２０〜４０ｎｍの酸化珪素または窒化珪素膜を形成した。その後、５５０〜６５０℃、好ましくは６００℃で７２時間アニールすることによって、アモルファスシリコン膜の結晶化をおこなった。このようにして結晶化されたシリコン膜の結晶性をラマン散乱分光法によって調べたところ、単結晶シリコンのピーク（５２１ｃｍ^−１）とは異なって、５１５ｃｍ^−１付近に比較的ブロードなピークが観測された。
【００３４】
次に保護層を除去して、シリコン層を露出せしめ、これを島状にパターニングして、周辺駆動回路のＴＦＴ領域１０３とマトリクス回路のＴＦＴ領域１０４を形成した。さらに、酸素雰囲気中でのスパッタ法によって、厚さ５０〜２００ｎｍのゲイト酸化膜１０５を形成した。その後、厚さ２００ｎｍ〜５μｍ、好ましくは２００〜６００ｎｍのアルミニウム膜１０６を電子ビーム蒸着法によって基板全面に形成した。そして、これを陽極酸化法によって酸化して、表面に厚さ１００〜３００ｎｍの陽極酸化物１０７を形成した。陽極酸化の条件は特願平４−３０２２０、同４−３８６３７および同４−５４３２２に示される条件を使用した。
【００３５】
さらに、図１（Ｂ）に示すように、陽極酸化物をフッ化水素酸を主体とするエッチャント（例えば１／１０バッファーＨＦ）によってエッチングしてから、残存した陽極酸化物をマスクとして、ＲＩＥによって金属アルミニウム膜１０６をエッチングした。さらに、周辺回路領域にはマスクを施して、マトリクス回路部のゲイト電極上の陽極酸化物がエッチングされた。こうして、周辺駆動回路部のゲイト電極１０８（ＮＴＦＴ用）と１０９（ＰＴＦＴ用）、さらにマトリクス回路部のゲイト電極１１０を得た（図１（Ｂ））。
【００３６】
その後、マトリクス回路部のゲイト電極にのみ電流を通じ、上記と同じ条件で厚さ２００〜３００ｎｍ、例えば２５０ｎｍの陽極酸化物１１１を該ゲイト電極の上面および側面に形成させた（図１（Ｃ））。
【００３７】
その後、イオンドーピング法によって、各ＴＦＴの島状シリコン膜中に、ゲイト電極部（すなわちゲイト電極とその周囲の陽極酸化膜）をマスクとして自己整合的に不純物を注入した。この際には、最初に全面にフォスフィン（ＰＨ3 ）をドーピングガスとして燐を注入し、その後、図の島状領域１０３の左側だけをフォトレジストで覆って、ジボラン（Ｂ2 Ｈ6 ）をドーピングガスとして、島状領域１０３および１０４に硼素を注入した。ドーズ量は、燐は２〜８×１０^１５ｃｍ^−２、硼素は４〜１０×１０^１５ｃｍ^−２とし、硼素のドーズ量が燐を上回るように設定した。
【００３８】
その後、ＫｒＦエキシマーレーザー（波長２４８ｎｍ、パルス幅２０ｎｓｅｃ）を照射して、上記不純物領域の導入によって、結晶性の劣化した部分の結晶性を改善させた。レーザーのエネルギー密度は２００〜４００ｍＪ／ｃｍ^２、好ましくは２５０〜３００ｍＪ／ｃｍ^２とした。この結果、周辺回路においてＮ型の領域１１２とＰ型の領域１１３、およびマトリクス回路のＰ型の領域１１４が形成された。これらの領域のシート抵抗は２００〜８００Ω／□であった。この工程において、ＫｒＦエキシマーレーザーのようなパルスレーザ光でなく、レーザー光の照射と同等の効果のある強光の照射によってもよい。この方法はＲＴＡ（ラピッドサーマルアニール）といわれ、赤外光、特に１μｍ〜２μｍにピークを有する赤外光（好ましくはハロゲン光（１．３μｍ））を利用して、シリコン半導体を選択的に加熱する方法である。
【００３９】
この方法によれば、上記不純物が導入された領域を１０００〜１２００度程度に加熱することができ、効果的なアニールを行うことができる。このような赤外光は、シリコン半導体に選択的に吸収されるので、ガラス基板に熱的なダメージを与えることなく、シリコン膜に対するアニールを行うことができる。また、数秒〜数分間の短い時間の照射で効果を上げることができることも特徴である。ここまでの様子を図１（Ｄ）に示す。
【００４０】
その後、全面に層間絶縁物１１５として、スパッタ法によって酸化珪素膜を厚さ３００ｎｍ形成した。これは、プラズマＣＶＤ法による酸化珪素膜や窒化珪素膜であってもよい。
【００４１】
その後、マトリクス部にスパッタ法によって形成したＩＴＯ膜をエッチングして、画素電極１１６を形成し、また、各ＴＦＴのソース／ドレインにコンタクトホールを形成し、スパッタ成膜とフォトリソグラフィー法で、図１（Ｅ）に示すように、クロム配線１１７〜１２１（いずれも厚さ８００ｎｍ）を形成した。この場合には、周辺回路領域のＮＴＦＴとＰＴＦＴでインバータ回路が形成されていることが示されている。最後に、水素中において３５０℃で２時間アニールして、シリコン膜のダングリングボンドを減らした。以上の工程によって周辺回路とアクティブマトリクス回路を一体化して形成できた。
【００４２】
〔実施例２〕本実施例を図２に示す。まず、基板（コーニング７０５９、３００ｍｍ×３００ｍｍもしくは１００ｍｍ×１００ｍｍ）２０１上に下地酸化膜２０２として厚さ１００〜３００ｎｍの酸化珪素膜を形成した。この酸化膜の形成方法としては、酸素雰囲気中でのスパッタ法やＴＥＯＳをプラズマＣＶＤ法で分解・堆積した膜を４５０〜６５０℃でアニールしてもよい。
【００４３】
その後、プラズマＣＶＤ法やＬＰＣＶＤ法によってアモルファス状のシリコン膜２０３を３０〜１５０ｎｍ、好ましくは５０〜１００ｎｍ堆積し、さらに、プラズマＣＶＤ法によって、保護層２０４として、厚さ２０〜１００ｎｍ、好ましくは５０〜７０ｎｍの酸化珪素または窒化珪素膜を形成した。そして、図２（Ａ）に示すようにＫｒＦエキシマーレーザー（波長２４８ｎｍ、パルス幅２０ｎｓｅｃ）を照射して、シリコン膜２０３の結晶性を改善させた。レーザーのエネルギー密度は２００〜４００ｍＪ／ｃｍ^２、好ましくは２５０〜３００ｍＪ／ｃｍ^２とした。このようにして形成されたシリコン膜２０３の結晶性をラマン散乱分光法によって調べたところ、単結晶シリコンのピーク（５２１ｃｍ^―１）とは異なって、５１５ｃｍ^―１付近に比較的ブロードなピークが観測された。このＫｒＦエキシマーレーザーの照射によるシリコン膜２０３の結晶化の後に、シリコン膜２０３に赤外光の強光を照射し、さらに結晶化を助長させることは有用である。赤外光は、シリコン半導体に選択的に吸収されるので、ガラス基板をそれ程加熱することなく、シリコン膜２０３の結晶化を効果的に助長させることができる。具体的には、欠陥や不対結合手を減少させることができる。また、強光の照射のみで結晶化を行ってもよい。その後、水素中において３５０℃で２時間アニールした。
【００４４】
次に保護層２０４を除去して、シリコン層２０３を露出せしめ、これを島状にパターニングして、実施例１と同様に周辺回路領域とアクティブマトリクス領域を形成した。さらに、酸素雰囲気中でのスパッタ法やＴＥＯＳをプラズマＣＶＤ法で分解・堆積した膜を４５０〜６５０℃でアニールする方法によって、ゲイト酸化膜を形成した。特に後者の方法を採用する場合には、本工程の温度によって、基板に歪みや縮みが生じ、後のマスク合わせが困難となる恐れがあるので大面積基板を扱う場合には十分に注意しなければならない。また、スパッタ法では基板温度は１５０℃以下にできるが、膜中のダングリングボンド等を減らして、固定電荷の影響を減らすために水素中で３００〜４５０℃程度のアニールをすることが望ましい。
【００４５】
その後、厚さ２００〜５００ｎｍのアルミニウム膜をスパッタ法によって形成して、これをパターニングし、図２（Ｂ）に示すように周辺回路領域を覆う金属アルミニウム被膜２０５とアクティブマトリクス領域のゲイト電極２０６を形成した。
【００４６】
さらに、図２（Ｃ）に示すように、基板を電解溶液に浸して上記アルミニウム被膜２０５およびゲイト電極２０６に電流を通じ、その表面あるいは周囲に陽極酸化物の層２０７、２０８を形成した。本実施例では陽極酸化膜の厚さは２００〜２５０ｎｍとした。また、この結果、残っている金属アルミニウムの厚さは１００〜４００ｎｍであった。
【００４７】
そして、次に図２（Ｄ）のように周辺回路領域のＴＦＴのゲイト電極２０９、２１０を形成した。最初にフッ化水素酸を主体とするエッチャント（例えば１／１０バッファーＨＦ）によって、ウェットエッチング法によって、陽極酸化物層をエッチングし、ついで、残存した陽極酸化物をマスクとして混酸によってアルミニウムをエッチングした。このようにしてゲイト電極を形成したが、図に示すようにこれらのゲイト電極の上には陽極酸化物が残されている。一方、アクティブマトリクス領域のＴＦＴのゲイト電極２１１はそのままである。
【００４８】
その後、イオンドーピング法によって、各ＴＦＴの島状シリコン膜中に、ゲイト電極部（すなわちゲイト電極とその周囲の陽極酸化膜）をマスクとして自己整合的に不純物を注入した。この際には、最初に全面にフォスフィン（ＰＨ3 ）をドーピングガスとして燐を注入し、その後、図の周辺回路領域の左側だけをフォトレジストで覆って、ジボラン（Ｂ2 Ｈ6 ）をドーピングガスとして、周辺回路領域の右側およびマトリクス領域だけに硼素を注入した。ドーズ量は、燐は２〜８×１０^１５ｃｍ^−２、硼素は４〜１０×１０^１５ｃｍ^−２とし、硼素のドーズ量が燐を上回るように設定した。
【００４９】
その後、ＫｒＦエキシマーレーザー（波長２４８ｎｍ、パルス幅２０ｎｓｅｃ）を照射して、上記不純物領域の導入によって、結晶性の劣化した部分の結晶性を改善させた。レーザーのエネルギー密度は２００〜４００ｍＪ／ｃｍ^２、好ましくは２５０〜３００ｍＪ／ｃｍ^２とした。またこの工程を強光（赤外光）の照射によるアニールで行ってもよい。
【００５０】
この結果、図２（Ｄ）に示すように、Ｎ型の領域２１２、およびＰ型の領域２１３、２１４が形成された。これらの領域のシート抵抗は２００〜８００Ω／□であった。その後、全面に層間絶縁物２１５として、スパッタ法によって酸化珪素膜を厚さ３００ｎｍ形成した。これは、プラズマＣＶＤ法による窒化珪素膜であってもよい。
【００５１】
その後、アクティブマトリクス部のＴＦＴには、透明導電材料（ＩＴＯ等）で画素電極２１６を形成した。そして、各ＴＦＴのソース／ドレインにコンタクトホールを形成し、クロム配線２１７〜２２１を形成した。この場合には、周辺回路領域のＮＴＦＴとＰＴＦＴでインバータ回路が形成されていることが示されている。さらに、最後に、水素中において３５０℃で２時間アニールして、シリコン膜のダングリングボンドを減らした。以上の工程によって周辺回路とアクティブマトリクス回路を一体化して形成できた。
【００５２】
【発明の効果】
本発明によって、ガラス基板に熱的なダメージを与えることなくシリコン膜に対するアニールを行うことができた。また、数秒〜数分間の短い時間の照射で効果を上げることができた。
さらに本発明によって、ＯＦＦ抵抗の大きなＴＦＴをアクティブマトリクス領域に形成し、また、構成の複雑な周辺回路領域も歩留り良く形成し、しかも両者を同一プロセスでモノリシックに形成することが出来た。したがって、例えばＡＭ−ＬＣＤに関しては、従来のようにＴＡＢ接続をおこなう場合に比べてコストを３０％以上削減することが出来た。従来のＴＦＴでは、移動度が高いＴＦＴでは、十分なＯＦＦ抵抗が得られないという問題があった。そのため、例えば高温プロセスによってマトリクスと周辺回路に同じ構造のＴＦＴを用いた場合には、いずれかの機能を犠牲にしなければならなかった。
【００５３】
これに対して、特願平４−３４１９４もしくは同４−３０２２０に記述される方法では、移動度が高くて、ＯＦＦ抵抗も大きいという理想的なＴＦＴが得られたので、例えば本発明人等の出願であるデジタル階調（例えば、特願平３−１６９３０６、同３−２０９８６９）のような高速動作と高いＯＮ／ＯＦＦ比が要求されるものであっても、何ら表示には差し支えないものであった。
【００５４】
しかしながら、特願平４−３４１９４もしくは同４−３０２２０で記述されるＴＦＴを回路の複雑な周辺駆動回路にまで適用しようとすると、作製上に大きな困難があった。本発明はこの矛盾に対して明解な回答を与えたものである。特に前記のデジタル階調表示は通常の表示方法に比して複雑な信号処理が要求されるので回路構成は極めて複雑である。そのため、従来は陽極酸化工程の困難という理由だけで、周辺駆動回路をＴＡＢ接続でＩＣに接続しなければならなかった。
【００５５】
本発明では、いかなる複雑な周辺回路もほとんどその能力を落とさずに形成できることとなった。もちろん、本発明はデジタル階調表示という方法だけに限らず、通常のアナログ階調表示方式を採用するＬＣＤにも有効であることは言うまでもない。特に、行数が１０００以上の高精彩ＬＣＤではその効果がいかんなく発揮される。また、実施例ではＡＭ−ＬＣＤについて記述されたが、広い意味でアクティブマトリクスと周辺駆動回路を有するデバイス（例えば、ＤＲＡＭやＳＲＡＭ等）全てに対しても本発明によって同様な効果が得られることは明らかであろう。このように本発明は工業上、極めて有益である。
【図面の簡単な説明】
【図１】本発明によるＴＦＴの作製方法を示す。
【図２】本発明によるＴＦＴの作製方法を示す。
【符号の説明】
１０１絶縁基板
１０２下地酸化膜
１０３半導体領域（周辺駆動回路用）
１０４半導体領域（アクティブマトリクス用）
１０５ゲイト絶縁膜
１０６金属被膜
１０７金属被膜の陽極酸化物
１０８ゲイト電極（周辺回路のＮＴＦＴ用）
１０９ゲイト電極（周辺回路のＰＴＦＴ用）
１１０ゲイト電極（アクティブマトリクス回路のＰＴＦＴ用）
１１１陽極酸化膜
１１２Ｎ型不純物領域
１１３、１１４Ｐ型不純物領域
１１５層間絶縁物
１１６画素電極（ＩＴＯ）
１１７〜１２１金属配線[0001]
[Industrial application fields]
The present invention relates to an insulating gate type semiconductor device on an insulating substrate, a method for forming an integrated circuit in which a large number of them are formed, and a semiconductor device formed by such a method. The semiconductor device according to the present invention is used as a thin film transistor in an active matrix such as a liquid crystal display or a drive circuit such as an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (such as a microprocessor, a microcontroller, a microcomputer, or a semiconductor memory). It is what is done.
[0002]
The present invention also provides an active matrix in a broad sense (a circuit in which wirings are arranged in a matrix and a circuit including one or more transistors for selection is provided at the intersection) and a driving circuit for driving the matrix. The present invention relates to an integrated semiconductor device having a peripheral circuit. Specifically, an active matrix liquid crystal display (AM-LCD), a semiconductor integrated circuit such as DRAM, SRAM, EPROM, EEPROM, mask ROM, etc., is formed on an insulating substrate.
[0003]
[Prior art]
In recent years, there has been much research on forming an insulated gate semiconductor device (MOSFET) on an insulating substrate. Forming a semiconductor integrated circuit on an insulating substrate in this way is advantageous for high-speed driving of the circuit. This is because the speed of the conventional semiconductor integrated circuit is mainly limited by the capacitance (stray capacitance) between the wiring and the substrate, whereas such a stray capacitance does not exist on the insulating substrate. A MOSFET formed on an insulating substrate and having a thin film active layer is called a thin film transistor (TFT). Also in a conventional semiconductor integrated circuit, for example, a TFT is used as a load transistor of an SRAM.
[0004]
Recently, products that require the formation of a semiconductor integrated circuit on a transparent substrate have appeared. For example, it is a drive circuit for an optical device such as a liquid crystal display or an image sensor. A TFT is also used here. Since these circuits are required to be formed in a large area, it is required to lower the temperature of the TFT manufacturing process. Further, for example, in a device having a large number of terminals on an insulating substrate, even when the terminals need to be connected to the semiconductor integrated circuit, in order to reduce the mounting density, the first stage of the semiconductor integrated circuit, Alternatively, it is also considered that the semiconductor integrated circuit itself is formed monolithically on the same insulating substrate.
[0005]
Conventionally, TFTs have improved crystallinity by annealing an amorphous, semi-amorphous, or microcrystalline semiconductor film at a temperature of 450 ° C. to 1200 ° C., so that a high-quality (ie, sufficiently large mobility) semiconductor film is obtained. Improvements have been made. Some amorphous TFTs use an amorphous material for the semiconductor coating, but the mobility is 5 cm.²/ Vs or less, usually 1cm²Its use is greatly limited from the viewpoint of operating speed, which is as small as / Vs, and from the point that a P-channel TFT cannot be obtained. Mobility is 5cm²In order to obtain a TFT of / Vs or higher, annealing at the above temperature was necessary. In addition, a P-channel TFT (PTFT) could be formed by such annealing. Alternatively, these thermal annealing steps were also performed by irradiating laser light or strong light.
[0006]
In the annealing step, for example, an annealing method performed by irradiation with strong light instead of pulsed laser light such as KrF excimer laser is called RTA (rapid thermal annealing), and has a peak at infrared light, particularly 1 μm to 2 μm. This is a method of selectively heating a silicon semiconductor using infrared light (preferably halogen light (1.3 μm)).
[0007]
For example, Patent Literature 1 and Patent Literature 2 are known as prior art literature information related to the RTA (Rapid Thermal Annealing) method.
[0008]
However, it has been pointed out that such a TFT has a problem in reliability when used as an active matrix because of a large leakage current in an off state. Against this background, the present inventors made the gate electrode with a low-resistance metal material such as aluminum as described in Japanese Patent Application No. 4-34194 or 4-30220, and formed this surface on the surface. A method has been proposed in which an offset region is formed by coating with an oxide by anodization and introducing impurities using such a metal / oxide structure as a main mask. As a result, the leakage current is reduced and the insulation between the layers is strengthened by the anodic oxide film, so that the short circuit at the cross portion can be remarkably reduced.
[0009]
That is, the anodic oxide film has few pinholes and has very high pressure resistance (7 MV / cm or more), so that the interlayer can be reliably insulated. By actually adopting the technique of Japanese Patent Application No. 4-34194 or 4-30220, defects due to short circuit between wirings can be remarkably reduced. In the active matrix region, there are a great number of places where wiring intersects, which is particularly important.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 4-94532 (2nd page "Example")
[0011]
[Patent Document 2]
Japanese Patent Laid-Open No. 3-180026 (Claims, page 2, “Example”)
[0012]
[Problems to be solved by the invention]
However, when the present inventors use this technique to produce a device (for example, a memory or an AM-LCD) in which the active matrix and its peripheral drive circuit are monolithically formed, it is a technically very difficult problem. Turned out to be.
[0013]
In general, the configuration of peripheral circuits and wiring connections are complex, and even if an attempt is made to cover metal electrodes with anodic oxide, current cannot be supplied due to the complexity of the wiring. If a wiring is formed only for anodization, an extra photolithography process for removing the wiring is required, resulting in a decrease in yield. In addition, when the circuit is configured by providing extra wiring in this way, the degree of integration is significantly reduced.
[0014]
However, for example, a method has been proposed in which an anodizing step is employed in the active matrix circuit portion and no anodizing step is employed in other regions such as the peripheral circuit portion, but the yield is remarkably low. This is mainly because the interlayer insulator is imperfect, so there are many pinholes, and the upper wiring and the lower wiring (gate electrode and its wiring, etc.) are short-circuited through such pinholes. It turned out to be.
[0015]
In particular, this is an essential problem as long as low melting point metal wiring is used. It is a well-known fact that aluminum and its alloys are excellent as gate electrode materials, but if this material is used as a gate electrode and an impurity element is introduced in a self-aligning manner, activation by thermal annealing is adopted. Inevitably, it was necessary to employ a low-temperature activation technique such as laser annealing to activate the impurity elements. Further, the formation of an interlayer insulating film at 450 ° C. or higher cannot be used.
[0016]
  For example, an interlayer insulating material such as silicon oxide formed by LPCVD or APCVD at a substrate temperature of 450 ° C. or higher has very few pinholes and almost no short circuit between wirings. However, only a sputtering method or a plasma CVD method can be employed at a low temperature of 450 ° C. or lower, and in these methods, a lot of dust falls on the film during film formation, resulting in a very large number of pinholes, which causes a problem in insulation. It became a certain film. Even in the peripheral drive circuit section, there is a crossing of wiring.Make sure there are no shorts between wiresIt is desirable to do.
  Furthermore, when a glass substrate is used as the substrate, it is also desired that annealing be performed on the silicon film without thermally damaging the glass substrate and that the effect be improved by irradiation for a short time of several seconds to several minutes.
[0017]
[Means for Solving the Problems]
  The present invention has been made in view of such problems as providing an optimal manufacturing process.
  The present invention is a method for manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, and the thin film transistor of the peripheral circuit is formed by forming an amorphous silicon film on a glass substrate, Crystallizing by heat treatment, forming a plurality of island-like silicon films by patterning the crystallized silicon film, forming a plurality of island-like silicon films by patterning the plurality of island-like silicon films, A gate insulating film is formed on the plurality of island-shaped silicon films, and has a thickness of 100 nm or moreanodizationAfter forming a gate electrode made of a metal film having a film formed only on the upper surface on the gate oxide film, the plurality of island-shaped silicon films are formed on the plurality of island-shaped silicon films.Using the gate electrode as a maskPhosphorus is introduced as an n-type impurity, and the island-like silicon film into which the phosphorus is introducedOf these, N-channel type thin film transistors are formed.A photoresist is formed on a part of the upper surface, and the island-like silicon film on which the photoresist is not formed in the state where the photoresist is formed is formed.Using the photoresist and the gate electrode as a maskIt is fabricated by irradiating the plurality of island-like silicon films with pulsed laser light after introducing boron as a p-type impurity with a dose amount larger than the dose amount of the n-type impurity. .
[0018]
  Further, as shown in the specification, the greatest feature obtained by providing an anodic oxide as in Japanese Patent Application No. 4-34194 or 4-30220 is that a reverse voltage is applied to the gate due to the effect of offset. In other words, the leakage current can be significantly reduced. Such a characteristic is necessary for a TFT in an active matrix region that performs a dynamic operation in which it is necessary to reliably hold the voltage of the pixel. Or it was necessary to suppress the power consumption of the flip-flop circuit during standby. In that sense, the TFT having such a structure is used as an AM-LCD pixel transistor, a DRAM storage bit selection transistor formed by SOI technology, or an SRAM (particularly a complete CMOS SRAM) storage bit inverter circuit. A great effect was obtained by using it.
  However, in the peripheral circuit, particularly in a circuit that performs a static or semi-static operation, the leakage current is not a problem. Therefore, the circuit operates satisfactorily even if an anodic oxide is not provided on at least the side surface (even if the offset structure is not used).
[0019]
However, if there is no dense coating such as anodic oxide on the upper surface of the gate electrode, the yield will be significantly reduced due to leakage between the wirings. In addition, as described in the specification of the above-mentioned patent application, when laser annealing is employed, the presence of anodic oxide on the upper surface of the gate electrode can minimize damage due to the laser annealing process. did it.
[0020]
According to the knowledge of the present inventors, the metal aluminum film formed by the electron beam evaporation method has a flat surface and a particle size of submicron or less. Although no damage was observed, very large damage was observed in a film having a large particle size (˜1 μm) formed by a method such as sputtering. However, since the electron beam evaporation method is inferior in mass productivity, it is desired to produce it practically by a sputtering method. That is, for the peripheral circuit, the anodic oxide on the side surface of the gate electrode is unnecessary, but it is necessary on the upper surface.
[0021]
  ThereforeBookThe invention proposes to form a TFT having a structure in which a anodic oxide substantially does not exist on the side surface of the gate electrode and a dense film such as an anodic oxide exists only on the upper surface together with the TFT in the active matrix region. To do. A method for manufacturing a TFT having such a structure and a device as an aggregate thereof may be performed as follows.
[0022]
First, a metal film such as aluminum is formed on the island-shaped semiconductor region and the gate insulating film. Then, an oxide film is formed on the surface by an anodic oxidation method. According to the knowledge of the present inventors, since the composition is different from the stoichiometric ratio when the thickness of the oxide is 100 nm or less, the insulating property is poor. Therefore, it is desirable that the thickness of the insulator is 100 nm or more.
[0023]
Thereafter, by etching the oxide and the metal film to form a gate electrode having a desired shape, a structure can be obtained in which the anodic oxide is left on the upper surface of the gate electrode and no anodic oxide is formed on the side surface.
[0024]
For these etchings, a directional etching method such as reactive ion etching (RIE) is preferable. This is because, in the isotropic etching method, a vacancy (cusp) is generated near the interface due to the difference in the etching rate of the anodic oxide and the metal film, and the disconnection of the upper wiring that crosses this is likely to occur. is there. However, depending on the material, there are cases where the entire process cannot be performed by RIE or the like.
[0025]
For example, when the metal material is aluminum, the anodic oxide is aluminum oxide, which cannot be removed by RIE. Therefore, in this case, first, the aluminum oxide film may be etched by wet etching, and then metal aluminum may be etched by RIE using the remaining aluminum oxide as a mask.
[0026]
If RIE cannot be employed for etching metal aluminum and only the wet etching is relied upon, it is desirable to make the metal aluminum film as thin as possible. Specifically, it is desired that the ratio of the thickness of the aluminum oxide film to the metal aluminum is 1: 3 or less, preferably 1: 2 or less.
[0027]
In order to construct a monolithic matrix circuit using such TFTs, the following may be performed. The first method includes the following processes.
(1) A metal film is similarly formed on the peripheral circuit and the matrix region.
{Circle around (2)} This is anodized to form an anodic oxide on the surface.
(3) Etch anodic oxide at unnecessary locations.
(4) The metal film is etched using the remaining anodic oxide as a mask to form gate electrodes in the peripheral circuit portion and the matrix portion.
(5) An anodic oxide is formed on the side surfaces of only the gate electrode of the matrix portion through the current only in the matrix portion.
[0028]
In this method, paying attention to the matrix portion, the second anodic oxidation is performed in the step (5) while the anodic oxide formed in the step (2) first remains on the gate electrode. Stress distortion may occur between the anodic oxide and the anodic oxide formed thereafter, and the upper anodic oxide formed first may peel off.
[0029]
In order to solve this, as shown in the first embodiment, after the step (4), a step of masking only the peripheral circuit portion (4) and removing the anodic oxide in the matrix portion is added. That's fine. Through such a process, the gate electrode in the matrix portion exposes the metal material over the entire surface, and anodic oxide is uniformly formed on the upper surface and side surfaces by (5). It is easy to mask only the matrix portion, and the yield is not reduced by adding this step. However, depending on the type of etchant, even the gate insulating film is etched in this step. If the surface of the semiconductor region is exposed, it may cause a decrease in yield, so care must be taken. In any case, at least two anodic oxidation steps are required.
[0030]
The second method is the method of the second embodiment, and mainly includes the following processes.
(1) A metal film is formed on the entire peripheral circuit portion, and a metal film is formed on the matrix portion while maintaining the shape of the gate electrode.
(2) An anodic oxide is formed by passing a current through the metal film in the peripheral circuit portion and the gate electrode (and its wiring) in the matrix portion.
(3) The anodic oxide and metal film in the peripheral circuit portion are etched to form a gate electrode in the peripheral circuit portion.
[0031]
In this method, the anodic oxidation step is performed once, but the photolithography step is required at least twice for (mainly) forming the gate electrode in the matrix portion and the gate electrode in the peripheral circuit portion.
[0032]
【Example】
Example 1 A silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 102 on a substrate (Corning 7059, 300 mm × 300 mm or 100 mm × 100 mm) 101. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere or a film obtained by decomposing and depositing TEOS by a plasma CVD method may be annealed at 450 to 650 ° C.
[0033]
Thereafter, an amorphous silicon film is deposited to a thickness of 30 to 150 nm, preferably 50 to 100 nm by plasma CVD or LPCVD, and further, a protective layer having a thickness of 20 to 100 nm, preferably 20 to 40 nm, is deposited by plasma CVD. A silicon oxide or silicon nitride film was formed. Thereafter, the amorphous silicon film was crystallized by annealing at 550 to 650 ° C., preferably 600 ° C. for 72 hours. When the crystallinity of the silicon film thus crystallized was examined by Raman scattering spectroscopy, the peak of single crystal silicon (521 cm) was observed.^-1Unlike) 515cm^-1A relatively broad peak was observed in the vicinity.
[0034]
Next, the protective layer was removed to expose the silicon layer, and this was patterned into an island shape to form the TFT region 103 of the peripheral drive circuit and the TFT region 104 of the matrix circuit. Further, a gate oxide film 105 having a thickness of 50 to 200 nm was formed by sputtering in an oxygen atmosphere. Thereafter, an aluminum film 106 having a thickness of 200 nm to 5 μm, preferably 200 to 600 nm, was formed on the entire surface of the substrate by electron beam evaporation. Then, this was oxidized by an anodic oxidation method to form an anodic oxide 107 having a thickness of 100 to 300 nm on the surface. The conditions shown in Japanese Patent Application Nos. 4-30220, 4-38637 and 4-54322 were used for the anodizing conditions.
[0035]
Further, as shown in FIG. 1B, after the anodic oxide is etched with an etchant (eg, 1/10 buffer HF) mainly composed of hydrofluoric acid, the remaining anodic oxide is used as a mask by RIE. The metal aluminum film 106 was etched. Further, the peripheral circuit region was masked, and the anodic oxide on the gate electrode of the matrix circuit portion was etched. Thus, gate electrodes 108 (for NTFT) and 109 (for PTFT) in the peripheral drive circuit portion, and gate electrode 110 in the matrix circuit portion were obtained (FIG. 1B).
[0036]
Thereafter, current was passed only through the gate electrode of the matrix circuit portion, and an anodic oxide 111 having a thickness of 200 to 300 nm, for example, 250 nm was formed on the upper surface and side surface of the gate electrode under the same conditions as above (FIG. 1C). .
[0037]
Thereafter, by ion doping, impurities were implanted into the island-like silicon film of each TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) as a mask. At this time, phosphorus is first implanted into the entire surface using phosphine (PH3) as a doping gas, and then only the left side of the island-like region 103 is covered with a photoresist, and diborane (B2 H6) is used as a doping gas. Boron was implanted into the island regions 103 and 104. Dose amount is 2-8x10 for phosphorus¹⁵cm^-2Boron is 4-10 × 10¹⁵cm^-2The boron dose was set to exceed that of phosphorus.
[0038]
Thereafter, KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to improve the crystallinity of the deteriorated portion by introducing the impurity region. Laser energy density is 200-400mJ / cm², Preferably 250-300 mJ / cm²It was. As a result, an N-type region 112 and a P-type region 113 and a P-type region 114 of the matrix circuit are formed in the peripheral circuit. The sheet resistance in these regions was 200 to 800 Ω / □. In this step, instead of pulsed laser light such as KrF excimer laser, irradiation with strong light having the same effect as laser light irradiation may be used. This method is called RTA (rapid thermal annealing) and selectively heats silicon semiconductors using infrared light, particularly infrared light having a peak at 1 to 2 μm (preferably halogen light (1.3 μm)). It is a method to do.
[0039]
According to this method, the region into which the impurities are introduced can be heated to about 1000 to 1200 degrees, and effective annealing can be performed. Since such infrared light is selectively absorbed by the silicon semiconductor, the silicon film can be annealed without causing thermal damage to the glass substrate. Another advantage is that the effect can be improved by irradiation for a short time of several seconds to several minutes. The state up to here is shown in FIG.
[0040]
Thereafter, a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulator 115 on the entire surface by sputtering. This may be a silicon oxide film or a silicon nitride film formed by plasma CVD.
[0041]
Thereafter, the ITO film formed by sputtering in the matrix portion is etched to form the pixel electrode 116, and contact holes are formed in the source / drain of each TFT. As shown in (E), chromium wirings 117 to 121 (all having a thickness of 800 nm) were formed. In this case, it is shown that an inverter circuit is formed by NTFT and PTFT in the peripheral circuit region. Finally, annealing was performed in hydrogen at 350 ° C. for 2 hours to reduce dangling bonds in the silicon film. Through the above steps, the peripheral circuit and the active matrix circuit can be integrally formed.
[0042]
Example 2 This example is shown in FIG. First, a silicon oxide film having a thickness of 100 to 300 nm was formed as a base oxide film 202 on a substrate (Corning 7059, 300 mm × 300 mm or 100 mm × 100 mm) 201. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere or a film obtained by decomposing and depositing TEOS by a plasma CVD method may be annealed at 450 to 650 ° C.
[0043]
Thereafter, an amorphous silicon film 203 is deposited to a thickness of 30 to 150 nm, preferably 50 to 100 nm by plasma CVD or LPCVD, and further, a thickness of 20 to 100 nm, preferably 50 to 100, is formed as a protective layer 204 by plasma CVD. A 70 nm silicon oxide or silicon nitride film was formed. Then, as shown in FIG. 2A, the crystallinity of the silicon film 203 was improved by irradiation with a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec). Laser energy density is 200-400mJ / cm², Preferably 250-300 mJ / cm²It was. When the crystallinity of the silicon film 203 formed in this manner was examined by Raman scattering spectroscopy, the peak of single crystal silicon (521 cm) was observed.^―1Unlike) 515cm^―1A relatively broad peak was observed in the vicinity. After crystallization of the silicon film 203 by irradiation with this KrF excimer laser, it is useful to irradiate the silicon film 203 with strong infrared light to further promote crystallization. Since infrared light is selectively absorbed by the silicon semiconductor, crystallization of the silicon film 203 can be effectively promoted without heating the glass substrate so much. Specifically, defects and dangling bonds can be reduced. Alternatively, crystallization may be performed only by irradiation with strong light. Thereafter, annealing was performed in hydrogen at 350 ° C. for 2 hours.
[0044]
Next, the protective layer 204 was removed to expose the silicon layer 203, which was patterned into an island shape to form a peripheral circuit region and an active matrix region as in the first embodiment. Further, a gate oxide film was formed by annealing at 450 to 650 ° C. using a sputtering method in an oxygen atmosphere or a film obtained by decomposing and depositing TEOS by a plasma CVD method. In particular, when using the latter method, due to the temperature of this process, the substrate may be distorted or shrunk, making it difficult to align the mask later. I must. Further, in the sputtering method, the substrate temperature can be set to 150 ° C. or lower, but it is desirable to perform annealing at about 300 to 450 ° C. in hydrogen in order to reduce dangling bonds in the film and reduce the influence of fixed charges.
[0045]
Thereafter, an aluminum film having a thickness of 200 to 500 nm is formed by sputtering, and this is patterned. As shown in FIG. 2B, a metal aluminum film 205 covering the peripheral circuit region and a gate electrode 206 in the active matrix region are formed. Formed.
[0046]
Further, as shown in FIG. 2C, the substrate was immersed in an electrolytic solution, and current was passed through the aluminum film 205 and the gate electrode 206 to form anodic oxide layers 207 and 208 on or around the surface. In this embodiment, the thickness of the anodic oxide film was 200 to 250 nm. As a result, the thickness of the remaining metal aluminum was 100 to 400 nm.
[0047]
Next, as shown in FIG. 2D, gate electrodes 209 and 210 of TFTs in the peripheral circuit region were formed. First, an anodic oxide layer was etched by wet etching with an etchant mainly composed of hydrofluoric acid (for example, 1/10 buffer HF), and then aluminum was etched with mixed acid using the remaining anodic oxide as a mask. . Although the gate electrodes were formed in this way, as shown in the figure, the anodic oxide was left on these gate electrodes. On the other hand, the gate electrode 211 of the TFT in the active matrix region remains unchanged.
[0048]
Thereafter, by ion doping, impurities were implanted into the island-like silicon film of each TFT in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) as a mask. In this case, first, phosphorus is implanted into the entire surface using phosphine (PH3) as a doping gas, and then only the left side of the peripheral circuit region in the figure is covered with a photoresist, and diborane (B2 H6) is used as a doping gas. Boron was implanted only on the right side of the circuit area and the matrix area. Dose amount is 2-8x10 for phosphorus¹⁵cm^-2Boron is 4-10 × 10¹⁵cm^-2The boron dose was set to exceed that of phosphorus.
[0049]
Thereafter, KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to improve the crystallinity of the deteriorated portion by introducing the impurity region. Laser energy density is 200-400mJ / cm², Preferably 250-300 mJ / cm²It was. Further, this step may be performed by annealing by irradiation with strong light (infrared light).
[0050]
As a result, as shown in FIG. 2D, an N-type region 212 and P-type regions 213 and 214 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. Thereafter, a silicon oxide film having a thickness of 300 nm was formed as an interlayer insulator 215 over the entire surface by sputtering. This may be a silicon nitride film formed by plasma CVD.
[0051]
Thereafter, a pixel electrode 216 was formed of a transparent conductive material (ITO or the like) on the TFT in the active matrix portion. Then, contact holes were formed in the source / drain of each TFT, and chrome wirings 217 to 221 were formed. In this case, it is shown that an inverter circuit is formed by NTFT and PTFT in the peripheral circuit region. Finally, annealing was performed in hydrogen at 350 ° C. for 2 hours to reduce dangling bonds in the silicon film. Through the above steps, the peripheral circuit and the active matrix circuit can be integrally formed.
[0052]
【The invention's effect】
  According to the present invention, the silicon film can be annealed without causing thermal damage to the glass substrate. Moreover, the effect could be improved by irradiation for a short time of several seconds to several minutes.
  furtherBookAccording to the invention, a TFT having a large OFF resistance can be formed in an active matrix region, and a peripheral circuit region having a complicated structure can be formed with a high yield, and both can be formed monolithically by the same process. Therefore, for example, with respect to the AM-LCD, the cost can be reduced by 30% or more compared to the case where the TAB connection is performed as in the prior art. A conventional TFT has a problem that a TFT having high mobility cannot obtain a sufficient OFF resistance. Therefore, for example, when TFTs having the same structure are used for the matrix and the peripheral circuit by a high temperature process, one of the functions must be sacrificed.
[0053]
On the other hand, in the method described in Japanese Patent Application No. 4-34194 or 4-30220, an ideal TFT having high mobility and high OFF resistance was obtained. Even if a high-speed operation and a high ON / OFF ratio are required, such as the digital gradation (for example, Japanese Patent Application Nos. 3-169306 and 3-209869), there is no problem with the display. there were.
[0054]
However, when the TFT described in Japanese Patent Application No. 4-34194 or 4-30220 is applied to a peripheral drive circuit having a complicated circuit, there is a great difficulty in manufacturing. The present invention provides a clear answer to this contradiction. In particular, the digital gradation display requires a complicated signal processing as compared with a normal display method, so that the circuit configuration is extremely complicated. Therefore, conventionally, the peripheral drive circuit had to be connected to the IC by TAB connection only because the anodizing process was difficult.
[0055]
In the present invention, any complicated peripheral circuit can be formed without substantially degrading its ability. Of course, the present invention is not limited to the method of digital gradation display, and it goes without saying that the present invention is also effective for an LCD employing a normal analog gradation display method. In particular, the effect is exerted on a high-definition LCD having 1000 or more rows. Also, in the embodiments, the AM-LCD has been described. However, the same effect can be obtained by the present invention for all devices (for example, DRAM, SRAM, etc.) having an active matrix and a peripheral drive circuit in a broad sense. It will be clear. Thus, the present invention is extremely useful in industry.
[Brief description of the drawings]
FIG. 1 shows a method for manufacturing a TFT according to the present invention.
FIG. 2 shows a method for manufacturing a TFT according to the present invention.
[Explanation of symbols]
101 Insulating substrate
102 Base oxide film
103 Semiconductor region (for peripheral drive circuit)
104 Semiconductor region (for active matrix)
105 Gate insulation film
106 Metal coating
107 Anodized metal coating
108 Gate electrode (for NTFT of peripheral circuit)
109 Gate electrode (for PTFT of peripheral circuit)
110 Gate electrode (for PTFT of active matrix circuit)
111 Anodized film
112 N-type impurity region
113, 114 P-type impurity region
115 Interlayer insulator
116 Pixel electrode (ITO)
117-121 metal wiring

Claims

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
Forming a gate oxide film on the plurality of island-like silicon films;
After forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface on the gate oxide film,
Introducing phosphorus as an n-type impurity into the plurality of island-shaped silicon films using the gate electrode as a mask ;
A photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In the state where the photoresist is formed, p-type impurities having a dose amount larger than the dose amount of the n-type impurity using the photoresist and the gate electrode as a mask on the island-like silicon film where the photoresist is not formed. After introducing boron as
A method for manufacturing a semiconductor device, wherein the plurality of island-shaped silicon films are manufactured by irradiating pulsed laser light.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
Forming a gate oxide film on the plurality of island-like silicon films;
After forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface on the gate oxide film,
Introducing phosphorus as an n-type impurity into the plurality of island-shaped silicon films using the gate electrode as a mask ;
A photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In the state where the photoresist is formed, p-type impurities having a dose amount larger than the dose amount of the n-type impurity using the photoresist and the gate electrode as a mask on the island-like silicon film where the photoresist is not formed. After introducing boron as
A method of manufacturing a semiconductor device, wherein the semiconductor device is manufactured by heating the plurality of island-shaped silicon films by an RTA (rapid thermal annealing) method.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
Forming a gate oxide film on the plurality of island-like silicon films;
After forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface on the gate oxide film,
Introducing phosphorus as an n-type impurity into the plurality of island-shaped silicon films using the gate electrode as a mask ;
A photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In the state where the photoresist is formed, p-type impurities having a dose amount larger than the dose amount of the n-type impurity using the photoresist and the gate electrode as a mask on the island-like silicon film where the photoresist is not formed. After introducing boron as
A method for manufacturing a semiconductor device, wherein the semiconductor device is manufactured by improving crystallinity of the plurality of island-shaped silicon films by an RTA (rapid thermal annealing) method.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
Forming a gate oxide film on the plurality of island-like silicon films;
After forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface on the gate oxide film,
Introducing phosphorus as an n-type impurity into the plurality of island-shaped silicon films using the gate electrode as a mask ;
A photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In the state where the photoresist is formed, p-type impurities having a dose amount larger than the dose amount of the n-type impurity using the photoresist and the gate electrode as a mask on the island-like silicon film where the photoresist is not formed. After introducing boron as
Irradiating the plurality of island-like silicon films with pulsed laser light,
A method for manufacturing a semiconductor device, wherein the semiconductor device is manufactured by annealing the plurality of island-shaped silicon films in hydrogen gas.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by irradiating the silicon film with a laser,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
Forming a gate oxide film on the plurality of island-like silicon films;
After forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface on the gate oxide film,
Introducing phosphorus as an n-type impurity into the plurality of island-shaped silicon films using the gate electrode as a mask ;
A photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In the state where the photoresist is formed, p-type impurities having a dose amount larger than the dose amount of the n-type impurity using the photoresist and the gate electrode as a mask on the island-like silicon film where the photoresist is not formed. After introducing boron as
Irradiating the plurality of island-like silicon films with pulsed laser light,
A method for manufacturing a semiconductor device, wherein the semiconductor device is manufactured by annealing the plurality of island-shaped silicon films in hydrogen gas.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
After forming a gate oxide film on the plurality of island-like silicon films,
Forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface above each of the plurality of island-shaped silicon films;
Introducing phosphorus as an n-type impurity using phosphine in the plurality of island-like silicon films using the gate electrode as a mask,
A mask made of a photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In a state where the mask made of photoresist is formed, the island-shaped silicon film where the mask made of photoresist is not formed using the gate electrode as a mask has a dose amount larger than the dose amount of the n-type impurity. After introducing boron as a p-type impurity using diborane,
A method for manufacturing a semiconductor device, wherein the plurality of island-shaped silicon films are manufactured by irradiating pulsed laser light.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
After forming a gate oxide film on the plurality of island-like silicon films,
Forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface above each of the plurality of island-shaped silicon films;
Introducing phosphorus as an n-type impurity using phosphine in the plurality of island-like silicon films using the gate electrode as a mask,
A mask made of a photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In a state where the mask made of photoresist is formed, the island-shaped silicon film where the mask made of photoresist is not formed using the gate electrode as a mask has a dose amount larger than the dose amount of the n-type impurity. After introducing boron as a p-type impurity using diborane,
A method of manufacturing a semiconductor device, wherein the semiconductor device is manufactured by heating the plurality of island-shaped silicon films by an RTA (rapid thermal annealing) method.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
After forming a gate oxide film on the plurality of island-like silicon films,
Forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface above each of the plurality of island-shaped silicon films;
Introducing phosphorus as an n-type impurity using phosphine in the plurality of island-like silicon films using the gate electrode as a mask,
A mask made of a photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In a state where the mask made of photoresist is formed, the island-shaped silicon film where the mask made of photoresist is not formed using the gate electrode as a mask has a dose amount larger than the dose amount of the n-type impurity. After introducing boron as a p-type impurity using diborane,
A method for manufacturing a semiconductor device, wherein the semiconductor device is manufactured by improving crystallinity of the plurality of island-shaped silicon films by an RTA (rapid thermal annealing) method.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by heat treatment,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
After forming a gate oxide film on the plurality of island-like silicon films,
Forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface above each of the plurality of island-shaped silicon films;
Introducing phosphorus as an n-type impurity using phosphine in the plurality of island-like silicon films using the gate electrode as a mask,
Of island silicon film in which the phosphorus is introduced, to form a mask made of photoresist on top surface of a portion of the N-channel type thin film transistor is formed,
In a state where the mask made of photoresist is formed, the island-shaped silicon film where the mask made of photoresist is not formed using the gate electrode as a mask has a dose amount larger than the dose amount of the n-type impurity. After introducing boron as a p-type impurity using diborane,
Irradiating the plurality of island-like silicon films with pulsed laser light,
A method for manufacturing a semiconductor device, wherein the semiconductor device is manufactured by annealing the plurality of island-shaped silicon films in hydrogen gas.

A method of manufacturing a semiconductor device having an active matrix and a peripheral circuit for driving the active matrix, wherein the thin film transistor of the peripheral circuit includes:
An amorphous silicon film is formed on a glass substrate,
Crystallizing the silicon film by irradiating the silicon film with a laser,
A plurality of island-shaped silicon films are formed by patterning the crystallized silicon film,
After forming a gate oxide film on the plurality of island-like silicon films,
Forming a gate electrode made of a metal film having an anodic oxide film having a thickness of 100 nm or more formed only on the upper surface above each of the plurality of island-shaped silicon films;
Introducing phosphorus as an n-type impurity using phosphine in the plurality of island-like silicon films using the gate electrode as a mask,
A mask made of a photoresist is formed on a part of the upper surface of the island-like silicon film into which phosphorus is introduced, on which an N-channel thin film transistor is formed ,
In a state where the mask made of photoresist is formed, the island-shaped silicon film where the mask made of photoresist is not formed using the gate electrode as a mask has a dose amount larger than the dose amount of the n-type impurity. After introducing boron as a p-type impurity using diborane,
Irradiating the plurality of island-like silicon films with pulsed laser light,
A method for manufacturing a semiconductor device, wherein the semiconductor device is manufactured by annealing the plurality of island-shaped silicon films in hydrogen gas.

11. The method for manufacturing a semiconductor device according to claim 1, wherein the amorphous silicon film is formed after a base oxide film is formed over the glass substrate.

12. The method for manufacturing a semiconductor device, wherein the semiconductor device according to claim 1 is an active matrix liquid crystal display.

12. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a semiconductor integrated circuit including a DRAM, an SRAM, an EPROM, an EEPROM, or a mask ROM.

In any one of claims 1 to 13, the dose at the time of introducing the boron, a method for manufacturing a semiconductor device which is a 4~10 × ¹⁰ 15 ^{cm -2.}