JP4075439B2 - Time division multi-channel amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a time division multichannel amplifying apparatus that amplifies a multichannel input signal by time division using a single amplifier (amplifier).
[0002]
[Prior art]
In an amplifying apparatus that handles signals of a plurality of channels, such as an audio apparatus for a home theater, an amplifier corresponding to the number of channels is usually provided as shown in FIG.
[0003]
In such an apparatus, there is no idea that each amplifier handles the signal of each channel independently and assigns the function of each amplifier to a plurality of channels.
[0004]
[Problems to be solved by the invention]
However, in audio devices that handle multi-channels, such as audio devices used in home theaters, it is rare that an input signal with a large input level is applied to each amplifier at the same time, and there are many channels with almost no signal at a certain moment. ing. For this reason, there are inconveniences that it is difficult to reduce the cost and the size of the amplifier because the efficiency of using the amplifier is poor and the amplifier is essential for each channel.
[0005]
An object of the present invention is to provide a time-division multi-channel amplifier capable of improving the efficiency of use of an amplifier by switching one amplifier in a time division manner and using it in each channel.
[0006]
[Means for Solving the Problems]
The present invention provides a sample hold circuit that samples and holds an input signal Vin (i) (i is a channel 1 to n) of each channel, and a level detection circuit that detects the level of each sampled and held input signal Vin (i). And an amplifier that linearly amplifies the input signal Vin (i) at a level up to a predetermined value VIc and amplifies the input signal Vin (i) at a level exceeding the predetermined value VIc at a maximum amplification factor, An input signal switching circuit that switches the signal Vin (i) at the switching time T (i) and inputs it to the amplifier, and an output signal that switches the output of the amplifier at the switching time T (i) to become an i-channel output signal. a switching circuit, determined by the highest frequency of the desired frequency band of the output signal, the input signal switching circuit and the switching of the output signal switching circuit A circuit for setting a change time T (i), and for a channel in which the level of each input signal Vin (i) detected by the level detection circuit reaches the predetermined value VIc, a time Tc that is always assigned to each channel is set. The total value of the time Tc of all channels is set to 1 / (2 × Fm), and the channel whose input level exceeds the predetermined value VIc has a linear relationship with (VI (i) −Vic). The required distribution time TL (i) is further set, and TL (i) = 0 is further set for the channel whose input level is equal to or lower than the predetermined value VIc, and the switching time T (i) is set.
T (i) = Tc + TL (i)
age,
When the total value of the distribution time TL (i) exceeds 1 / (2 × Fm), 1 / (2 × Fm), which is a distributable time, is prorated according to the level balance of each channel. The switching time T (i) is set to T (i) = Tc + { TL (i) / ΣTL (i)} × {1 / (2 × Fm)}
Where F is the highest frequency of the desired frequency band of the output signal, m is an arbitrary integer value ( > 1 ) , Tc is a time that is always assigned to each channel, and 1 / ( 2 × Fm × N ) , TL (I) is a value (time) corresponding to the input level VI (i) exceeding the predetermined value VIc, and N is the total number of channels.
And a control circuit that calculates as follows.
[0007]
In the present invention, when the input signal of each channel of CH1 to CHn is sampled and held and passed through one amplifier in a time division manner , the level detection circuit detects the switching time T (i) for each time division channel . For channels where the level of each input signal Vin (i) reaches the predetermined value VIc, the predetermined time Tc is set to the switching time T (i), and the level of the input signal Vin (i) exceeds the predetermined value VIc. For a channel, a time obtained by adding a fixed time Tc and a time TL (i) distributed according to the level of the input signal of the channel is set as the switching time T (i), and is set for all channels. When the total switching time T (i) is set to 1 / Fm or less and the total switching time T (i) set for all channels exceeds 1 / Fm, The channel level force signal Vin (i) exceeds the predetermined value VIc, the predetermined time Tc, the time and that proportionally dispensable time 1 / (2 × Fm) according to the level balance of the input signal of the channel , sets the time obtained by adding the switching time T (i). Therefore, it is possible to use the amplifier with high efficiency, Ru can be increased speaker output larger channels of the input level.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
(First embodiment)
FIG. 2 is a block diagram of a time division multi-channel amplifier according to an embodiment of the present invention.
[0009]
The sample hold circuit 1 samples and holds the input signals Vin (i) (i is channels 1 to n) of each channel of CH1 to CHn by a sampling clock of about several hundred kHz formed by the sampling clock circuit 2. The level of the input signal Vin (i) sampled and held by each sample and hold circuit 1 is sequentially detected by the level detection circuit 4 via the switching circuit 3 that is switched by a clock of about several MHz. The sampled and held input signal Vin (i) is input to the amplifier 6 via the input signal switching circuit 5, and the input signal of each channel is amplified in a time division manner.
[0010]
The amplifier 6 is a linear amplifier, and amplifies linearly with a constant gain until the input signal reaches a predetermined value VIc, and amplifies an input signal having a level exceeding VIc with a maximum gain.
[0011]
The output signal of the amplifier 6 is output as an output signal of 1 to n channels via the output signal switching circuit 7. The output signals of 1 to n channels are integrated by an integration circuit 8 including L and C, converted into an analog signal, and output to the speaker 9.
[0012]
The level of each input signal detected by the level detection circuit 4 is input to the arithmetic control circuit 10 where the switching timing signals of the switching circuits 5 and 7 are formed. This switching timing signal is input to the switching control circuit 11, and the switching circuits 5 and 7 are switched for each channel in synchronization. The operation control circuit 10 detects the level of each input signal in the level detection circuit 4 and forms the switching timing signal corresponding to each period, with the time for the switching circuits 5 and 7 to switch from CH1 to CHn as one period. Do.
[0013]
The arithmetic control circuit 10 calculates a period T (i) in which each channel is connected to the amplifier 6 according to the level and level balance of each channel, and forms a switching timing signal. That is, the arithmetic control circuit 10 lengthens the period T (i) as the level of each channel detected by the level detection circuit 4 is higher. For this reason, the time T (i) that passes through the amplifier 6 becomes longer as the level of the input signal is higher, and the power allocated to the channel becomes larger.
[0014]
As described above, by sequentially switching the channels by the switching circuits 5 and 7, one amplifier 6 can be driven in a time-sharing manner for each channel, and the driving power of the speaker 9 of the channel increases as the level of each channel increases. growing. Thereby, the amplifier 6 can be used with high efficiency. The integrating circuit 8 is for smoothing the signal that is time-division driven.
[0015]
Next, the calculation method of the period T (i) and the control procedure of the calculation control circuit 10 will be described in detail with reference to FIG.
[0016]
FIG. 3 is a flowchart showing a control procedure of the arithmetic control circuit 10.
[0017]
In the configuration shown in FIG. 2, the gain of the amplifier 6 is constant until the input is a predetermined value VIc. When the input is VIc, the output is the maximum value VOmax. However, when there is an input with a level exceeding VIc, the output is fixed at VOmax. The number of channels is N, and the highest frequency in the desired frequency band of the output signal is F. In order to realize linear amplification up to the maximum frequency F, the switching frequency of each channel of the input signal switching circuit 5 and the output signal switching circuit 7 is set to m times F (m is an integer of 2 or more, 4 to It is desirable to select from an integer of about 10. The sampling clock circuit 2 constantly supplies a sampling clock of about several hundreds of kHz to the sample hold circuit 1, and the sample hold circuit 1 of each channel always samples and holds the input signal Vin (i).
[0018]
In FIG. 3, first, the arithmetic control circuit 10 controls the input signal switching circuit 5 and the output signal switching circuit 7 to turn off all the channels, thereby bringing them into an unconnected state (ST1). Next, the level detection circuit 4 detects the level of the input signal Vin (i) of each channel that has been sampled and held. At this time, the switching circuit 3 switches with a signal of several MHz, which is sufficiently faster than the sampling frequency. The input level of channel i read by the level detection circuit 4 is VI (i).
[0019]
Next, the ON time T (i) of each channel of the input signal switching circuit 5 and the output signal switching circuit 7 is calculated based on VI (i) (ST3).
[0020]
The calculation method of T (i) is illustrated with reference to FIGS.
[0021]
The time of one cycle of the switching circuits 5 and 7 is 1 / Fm. Therefore, when F = 20 kHz and m = 5, the time required for the switching circuits 5 and 7 to return from CH1 to CH1 is 10 μsec. A time Tc that is always allocated is set for each channel. The total value of each channel of Tc is set to 1/2 of 1 / Fm (5 μsec), and the remaining half of 1 / (2 × Fm) (5 μsec) is set to the level or level balance of each channel. Distribute according to. The time distributed to each channel is represented by TL (i). As will be described later, as a result of the above distribution calculation, the total value of TL (i) may exceed 1 / (2 × Fm). In this case, 1 / (2 × Fm) is the level balance of each channel. According to the level of each channel, otherwise it is distributed according to the level of each channel. In this distribution, TL (i) = 0 when the input level is equal to or lower than a certain level VIc, and TL (i)> 0 when the input level exceeds VIc, and the channel whose input level exceeds VIc. Make sure that distribution is done only for. FIG. 5A shows an input level example for each input channel. FIG. 5B shows a state before distribution, and FIG. 6 shows a state after distribution. If the amplifier 6 can linearly amplify an input signal exceeding the predetermined value VIc, the output of the amplifier 6 should be as shown in FIG. 5B, but the maximum output of the amplifier 6 is VOmax. Therefore, the input channels 2, 3,..., N whose input level VI is greater than or equal to the predetermined value VIc are controlled so that the output is extended on the time axis as shown in FIG. That is, control is performed so that the hatched area in FIG. 5B is an output extended on the time axis.
[0022]
Therefore, in the example shown in FIGS. 5 and 6, since the input level of CH (1) is not more than VIc, TL (1) = 0. For CH (2), CH (2), ..., CH (n), the respective levels exceed VIc, so TL (2), TL (3) ,. , TL (n)> 0 and T (i)> Tc. Since the output level of the amplifier 6 is fixed at VOmax when the level of the input signal exceeds VIc, in the above example, T (i) is as shown in FIG. The relationship between the input signal level exceeding VIc (VI-VIc) and TL is a linear relationship as shown in FIG. The linearity characteristic can be appropriately determined in advance by measurement or simulation. However, when the level of the input signal is very high, the total value of TL (i) may exceed 1 / (2 × Fm). Therefore, in such a case, 1 / (2 × Fm) which is a distributable time is apportioned according to the level balance of each channel. FIG. 6 shows an example in which the total value of T (i) is 1 / Fm by dividing 1 / (2 × Fm). On the other hand, when the level of the input signal is very low, the total value of T (i) is 1 / Fm or less.
[0023]
A specific arithmetic expression of T (i) is as follows.
[0024]
T (i) = Tc + {TL (i) / ΣTL (i)} × {1 / (2 × Fm)}
However,
F is the highest frequency of the desired frequency band of the output signal,
m is an arbitrary integer value (> 1),
Tc is the time allotted to each channel, 1 / (2 × Fm × N),
When the input level VI (i) exceeds VIc, TL (i) is a value (time) corresponding to the excess level,
N is the total number of channels.
[0025]
In {TL (i) / ΣTL (i)} × {1 / (2 × Fm)} on the right side of the above equation, a value obtained by dividing 1 / (2 × Fm) according to the level balance of each channel is obtained. This is added to the constant value Tc to obtain T (i).
[0026]
As described above, the calculation control circuit 10 calculates T (i) (ST3), and the switching control circuit 11 connects the switching circuits 5 and 7 to the channel during the calculated T (i) period. (ST4).
[0027]
If F = 20 kHz and m = 5, 1 / Fm = 10 μsec. If the number of channels N is 5, Tc = 1/2 × 10 μsec × 1/5 = 1 μsec. 1 / (2 × Fm) allocated to each channel is 5 μsec.
[0028]
In ST4 of FIG. 3, the switching control circuit 11 sequentially controls the input signal switching circuit 5 and the output signal switching circuit 7 according to the calculated T (i). When the switching of CH (i) is completed, ST1 is again performed. Return to and repeat the above operation. The integrating circuit 8 demodulates the analog signal by smoothing the output signal shown in FIG. That is, when the input signal VI exceeds VIc, the amplifier 6 operates as a class D amplifier.
[0029]
In the above configuration, for example, when the number of all channels N is 5 and the amplifier 6 is 100 W, linearity of output power is guaranteed up to 10 W for each channel, and when MAX signals come simultaneously for 5 channels, Each channel output is 20 W × 5 channels. When only one channel is maximum, 60W + 10W × 4 channels are obtained, and when two channels are maximum, 35W × 2 channels + 10W × 3 channels are obtained. Thus, the speaker can be driven with the highest efficiency according to the level balance of each channel.
[0030]
Although the level detection circuit 4 is used in a time division manner, a level detection circuit may be prepared for each input channel, and each detection value may be input to the arithmetic control circuit 10.
[0031]
( Second Embodiment)
In the first embodiment, when the input signal is up to the predetermined value VIc, the amplifier 6 linearly amplifies the signal. When the signal exceeds VIc, the amplification operation is performed to change the T (i) by fixing the maximum value VOmax. Yes. Instead of this, it is also possible to perform an amplification operation in which the amplifier 6 is fixed at 100% and the maximum value VOmax and T (i) is varied. In this configuration, when the input level is up to the predetermined value VIc, the arithmetic control circuit 10 changes T (i) linearly,
T (i) = Tc (i)
Ask for. Tc (i) is a value determined according to the level of the input signal VI (i), and is obtained from the linear relationship shown in FIG. Tc (i) corresponding to the input level is always assigned to each channel i.
[0032]
For an input signal VI (i) having a level exceeding the predetermined value VIc, T (i) of the channel is set as follows.
T (i) = Tcmax + TL (i)
Ask for. Here, Tcmax is the maximum value of TC when the input level is VIc, and is obtained from the relationship of FIG. TL (i) is a time distributed in proportion to the level or level balance of each channel as in the first embodiment. The total distribution time, in the first embodiment was the 1 / (2 × Fm), in the present embodiment, a (1 / Fm-ΣTc (i )). However, ΣTc (i) is a value obtained by summing the time Tc (i) allocated to channel i (different for each channel) for all channels.
[0033]
Therefore, in this embodiment, T (i) is
T (i) = Tc (i) + {TL (i) / ΣTL (i)} × {1 / Fm−ΣTc (i)}
However,
F is the highest frequency of the desired frequency band of the output signal,
m is an arbitrary integer value (> 1)
Tc (i) is a time allocated to each channel (i) according to the input level, and a value corresponding to the input level (= <Tcmax)
Tcmax the Tc value when the input level exceeds VIc TL (i), when the input level VI (i) exceeds VIc, values corresponding to the exceeded amount (time)
N is the total number of channels.
FIG. 8 shows an input level example for each input channel. FIG. 9 shows a state after distribution. In the input channel (1), since the input level is VIc or less, TC (1) is TCmax or less. Input channel CH (2), CH (3 ), ···, the CH (n), since the input level exceeds VIc, TC (2), TC (3), ···, TC (n) Is a value obtained by adding TL (2), TL (3), ..., TL (n) to TCmax.
[0035]
In this embodiment as well, the speaker can be driven with the highest efficiency according to the level balance of each channel.
[0036]
In any of the above embodiments, since noise is generated at the switching timing of the switching circuits 5 and 7, known noise mute means including a capacitor or the like is provided to prevent this, and noise mute by this is provided. It is desirable to add the time Tα to the T (i).
[0037]
【The invention's effect】
According to the present invention, since only one amplifier is required, it is advantageous in improving space efficiency and reducing the cost of components. In addition, in order to optimally allocate the usage time of the amplifier according to the level balance of the input signal, 1 A plurality of speakers can be driven with high efficiency by one amplifier.
[Brief description of the drawings]
FIG. 1 is a block diagram of a conventional multi-channel amplifier. FIG. 2 is a block diagram of a time-division multi-channel amplifier according to an embodiment of the present invention. FIG. 5 is a diagram illustrating a calculation method. FIG. 5 is a diagram illustrating a calculation method. FIG. 6 is a diagram illustrating a linearity that determines TL according to the level balance of each channel. FIG. 9 is a diagram illustrating a calculation method according to another embodiment of the present invention. FIG. 9 is another diagram illustrating a calculation method according to another embodiment of the present invention. FIG. 10 determines TC according to the input level VI of each channel. Diagram showing linearity

Claims (1)

A sample and hold circuit that samples and holds the input signal Vin (i) (i is a channel 1 to n) of each channel;
A level detection circuit for detecting the level of each sampled and held input signal Vin (i);
An amplifier that linearly amplifies an input signal Vin (i) at a level up to a predetermined value VIc , and amplifies an input signal Vin (i) at a level exceeding the predetermined value VIc at a maximum amplification factor;
An input signal switching circuit for switching each sampled and held signal Vin (i) at a switching time T (i) and inputting the signal to the amplifier;
An output signal switching circuit for switching the output of the amplifier at the switching time T (i) to be an i-channel output signal;
A circuit for setting the switching time T (i) of the input signal switching circuit and the output signal switching circuit, which is determined by the highest frequency of a desired frequency band of the output signal ,
For channels where the level of each input signal Vin (i) detected by the level detection circuit is up to the predetermined value VIc, a time Tc that is always assigned to each channel is set, and the total value of the times Tc of all channels is set to 1. / (2 × Fm)
For a channel whose input level exceeds a predetermined value VIc, a distribution time TL (i) obtained from a linear relationship with (VI (i) −Vic) is further set,
For channels whose input level is less than or equal to the predetermined value VIc, TL (i) = 0 is further set,
The switching time T (i) is
T (i) = Tc + TL (i)
age,
When the total value of the distribution time TL (i) exceeds 1 / (2 × Fm), 1 / (2 × Fm), which is a distributable time, is prorated according to the level balance of each channel.
The switching time T (i) is set to T (i) = Tc + { TL (i) / ΣTL (i)} × {1 / (2 × Fm)}
Where F is the highest frequency of the desired frequency band of the output signal,
m is an arbitrary integer value ( > 1 ) ,
Tc is the time allotted to each channel, 1 / ( 2 × Fm × N ) ,
When the input level VI (i) exceeds a predetermined value VIc, TL (i) is a value (time) corresponding to the amount exceeding the input level VI (i),
N is the total number of channels
A control circuit that operates as
A time-division multichannel amplifying apparatus comprising:

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