JPH08107359A - Digital signal processing unit - Google Patents

Abstract

PURPOSE: To improve S/N by gradually decreasing a gain of a variable gain circuit when a digital signal indicates a non-signal input state to prevent noise components from being amplified in an analog amplifier even when a DSP (digital signal processor) processes a digitally zero signal in the ON mode. CONSTITUTION: A digital signal processing section 15 is made up of a DSP 11 and a DAC(D/A converter) 12. A digital signal Din receives prescribed arithmetic operation in the DSP 11 and is converted into an analog signal by the DAC 12. When the digital signal Din is zero digitally, a digital zero detection circuit 17 provides an output of a detection signal. A gain control circuit 18 decreases the gain of a variable gain circuit 16 gradually upon the receipt of the detection signal from the digital zero detection circuit 17. Furthermore, the gain control circuit 18 is made up of a time constant circuit or the like. Thus, only noise components are amplified in the digital zero state and the S/N is not deteriorated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing device, and particularly to an audio product.

[0002]

2. Description of the Related Art FIG. 10 shows a conventional digital signal processing device. This digital signal processing device is a DSP
The (digital signal processor) 11 has two modes, an OFF mode and an ON mode. These two modes are switched by the switch 14.

When the DSP 11 is in the OFF mode, the digital signal Din is directly converted into an analog signal by the DAC (digital-analog converter) 12. DA
The output signal of C12 is output via the analog amplifier 13.

When the DSP 11 is in the ON mode, the digital signal Din is input to the DSP 11 and given a predetermined processing by the DSP 11. In addition, the DSP 11 sets the level of the digital signal to 1 / n in order to prevent saturation when adding various effects to the digital signal.
A predetermined calculation is performed after narrowing down to (n is a number larger than 1).

When the DSP 11 is in the ON mode, the DSP
Since the level of the digital signal is reduced to 1 / n in 11,
The analog amplifier 13 adjusts the gain of the analog signal to match the level in the OFF mode.

[0006]

When the DSP 11 is in the ON mode, the analog amplifier 13 functions and the gain of the analog signal is adjusted. However, when digital zero, that is, when there is no signal input, such as between tracks or when paused, DA
Only the noise component is output from C12.

Therefore, when the DSP 11 is in the ON mode and the digital is zero, only the noise component is amplified by the analog amplifier 13, so that S /
There is a drawback that the N ratio deteriorates.

As described above, conventionally, when the DSP is in the ON mode, when the digital value becomes zero, only the noise component is amplified by the analog amplifier and the S / N ratio is deteriorated.

The present invention has been made to solve the above-mentioned drawbacks, and an object thereof is to prevent a noise component from being amplified by an analog amplifier even if the DSP becomes a digital zero in the ON mode and to improve the S / N ratio. To improve.

[0010]

In order to achieve the above object, a digital signal processing device of the present invention includes a digital signal processing unit for processing a digital signal and converting it into an analog signal, and the analog signal by adjusting a gain. And a means for gradually reducing the gain of the variable gain circuit when the digital signal indicates a no-signal input state.

The digital signal processing apparatus of the present invention includes a digital signal processing unit for processing a digital signal and converting it into an analog signal, a variable gain circuit for adjusting the gain and outputting the analog signal, the analog signal and a reference. A switch for selecting a voltage and outputting it to the variable gain circuit, and when the digital signal indicates a no-signal input state, gradually lowers the gain of the variable gain circuit and then outputs the reference voltage to the variable gain circuit. And means for controlling so as to do so.

The digital signal processing device of the present invention comprises a digital signal processing unit for processing a digital signal and converting it into an analog signal, a variable gain circuit for adjusting the gain and outputting the analog signal, and the variable gain circuit. A switch for selecting and outputting an output signal and a reference voltage, and means for controlling to output the reference voltage after gradually reducing the gain of the variable gain circuit when the digital signal indicates a no-signal input state. It has and.

The digital signal processing section may convert a digital signal into an analog signal, an arithmetic circuit for performing a predetermined arithmetic operation on the digital signal, and lead the digital signal to the DA converter via the arithmetic circuit. And a switch for selecting whether to directly lead the digital signal to the DA converter.

[0014]

According to the above-mentioned structure, the non-signal input state (digital zero) of the digital signal is detected by the above means, and the gain of the variable gain circuit (analog amplifier) in the no signal input state is gradually reduced.

Further, by the above means, it is possible to mute the variable gain circuit by gradually reducing the gain and then outputting the reference voltage. Therefore, even if the digital signal of the digital signal processing unit is in the non-signal input state, the noise component is not amplified, so that the S / N ratio can be improved.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The digital signal processing apparatus of the present invention will be described in detail below with reference to the drawings. [A] FIG. 1 shows a digital signal processing apparatus according to the first embodiment of the present invention.

The digital signal processing section 15 comprises a DSP 11 and a DAC 12. Digital signal Din
Is subjected to a predetermined calculation by the DSP 11 and converted into an analog signal by the DAC 12. In the digital signal processing unit 15, the level of the digital signal is narrowed down to 1 / n (n is a number larger than 1).

When the digital signal Din is so-called digital zero, the digital zero detection circuit 17 outputs a detection signal. The gain control circuit 18 is the digital zero detection circuit 1
When the detection signal 7 is received, the gain of the variable gain circuit (analog amplifier) 16 is gradually reduced.

The gain control circuit 18 can be composed of a time constant circuit (for example, a resistor and a capacitor). As a result, at the time of digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated.

2 and 3 show a specific example of the digital signal processing device of FIG. In the digital signal processing device of FIG. 2, the switch 14 switches between the OFF mode and the ON mode of the DSP.

That is, when the DSP 11 is in the OFF mode,
The digital signal Din is directly converted into an analog signal by the DAC 12, and the analog signal is output via the variable gain circuit 16.

Further, when the DSP 11 is in the ON mode,
When it is not digital zero, the digital signal Din is D
It is input to SP11 and is subjected to predetermined processing by DSP11. In the DSP 11, the digital signal level is 1 /
Since it is narrowed down to n, the gain of the analog signal is adjusted by the variable gain circuit 16 to match the level in the OFF mode.

Further, when the DSP 11 is in the ON mode,
When digital zero, digital signal Din is DSP
Is input to the DAC 12 via 11 and the DSP 1
It is also input to the digital zero detection circuit 17 via 1.

When the digital zero detection circuit 17 detects that it is a digital zero, it outputs a detection signal to the gain control circuit 1.
Output to 8. Upon receiving the detection signal of the digital zero detection circuit 17, the gain control circuit 18 gradually reduces the gain of the variable gain circuit 16.

Therefore, when the DSP 11 is in the ON mode and digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated. FIG.
In the digital signal processing device, the digital zero detection circuit 17 detects the digital zero based on the digital signal input to the DSP 11.

That is, when the DSP 11 is in the OFF mode,
The digital signal Din is directly converted into an analog signal by the DAC 12, and the analog signal is output via the variable gain circuit 16.

Further, when the DSP 11 is in the ON mode,
When it is not digital zero, the digital signal Din is D
It is input to SP11 and is subjected to predetermined processing by DSP11. In the DSP 11, the digital signal level is 1 /
Since it is narrowed down to n, the gain of the analog signal is adjusted by the variable gain circuit 16 to match the level in the OFF mode.

Further, when the DSP 11 is in the ON mode,
When digital zero, digital signal Din is DSP
It is input to the DAC 12 via 11 and also directly input to the digital zero detection circuit 17.

When the digital zero detecting circuit 17 detects that it is a digital zero, it outputs a detection signal to the gain control circuit 1.
Output to 8. Upon receiving the detection signal of the digital zero detection circuit 17, the gain control circuit 18 gradually reduces the gain of the variable gain circuit 16.

Therefore, when the DSP 11 is in the ON mode and the digital is zero, only the noise component is not amplified and the S / N ratio is not deteriorated.
[B] FIG. 4 shows a digital signal processing apparatus according to the second embodiment of the present invention.

The digital signal processing section 15 comprises a DSP 11 and a DAC 12. Digital signal Din
Is subjected to a predetermined calculation by the DSP 11 and converted into an analog signal by the DAC 12. In the digital signal processing unit 15, the level of the digital signal is narrowed down to 1 / n.

When the digital signal Din is so-called digital zero, the digital zero detection circuit 17 outputs a detection signal. The gain control circuit 18 is the digital zero detection circuit 1
When the detection signal 7 is received, the gain of the variable gain circuit (analog amplifier) 16 is gradually reduced. Also, the switch 20
Is switched to the side of the reference voltage generating circuit 19 after the gain of the variable gain circuit 16 is reduced to some extent, and is muted.

The switching timing of the switch 20 can be controlled by a delay circuit or the like. As a result, at the time of digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated.

5 and 6 show specific examples of the digital signal processing device of FIG. In the digital signal processing device of FIG. 5, the switch 14 switches the OFF mode and the ON mode of the DSP.

That is, when the DSP 11 is in the OFF mode, the digital signal Din is directly converted into an analog signal by the DAC 12, and the analog signal is output via the switch 20 and the variable gain circuit 16.

Further, when the DSP 11 is in the ON mode,
When it is not digital zero, the digital signal Din is D
It is input to SP11 and is subjected to predetermined processing by DSP11. In the DSP 11, the digital signal level is 1 /
Since it is narrowed down to n, the gain of the analog signal is adjusted by the variable gain circuit 16 to match the level in the OFF mode.

Further, when the DSP 11 is in the ON mode,
When digital zero, digital signal Din is DSP
It is input to the DAC 12 via 11. When the digital zero detection circuit 17 detects that it is a digital zero,
The detection signal is output to the gain control circuit 18 and the switch 20, respectively.

Upon receiving the detection signal of the digital zero detection circuit 17, the gain control circuit 18 gradually reduces the gain of the variable gain circuit 16. Further, the switch 20 is switched to the reference voltage generation circuit 19 side after the gain of the variable gain circuit 16 is reduced to some extent.

Therefore, even when the DSP 11 is in the ON mode and digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated. In the digital signal processing device of FIG. 6, the digital zero detection circuit 17 detects the digital zero based on the digital signal input to the DSP 11.

That is, when the DSP 11 is in the OFF mode,
The digital signal Din is directly converted into an analog signal by the DAC 12, and the analog signal is output via the variable gain circuit 16.

Further, when the DSP 11 is in the ON mode,
When it is not digital zero, the digital signal Din is D
It is input to SP11 and is subjected to predetermined processing by DSP11. In the DSP 11, the digital signal level is 1 /
Since it is narrowed down to n, the gain of the analog signal is adjusted by the variable gain circuit 16 to match the level in the OFF mode.

Further, when the DSP 11 is in the ON mode,
When digital zero, digital signal Din is DSP
It is input to the DAC 12 via 11. When the digital zero detection circuit 17 detects that it is a digital zero,
The detection signal is output to the gain control circuit 18 and the switch 20, respectively.

Upon receiving the detection signal from the digital zero detection circuit 17, the gain control circuit 18 gradually reduces the gain of the variable gain circuit 16. Further, the switch 20 is switched to the reference voltage generation circuit 19 side after the gain of the variable gain circuit 16 is reduced to some extent.

Therefore, when the DSP 11 is in the ON mode and digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated. [C] FIG. 7 shows a digital signal processing apparatus according to the third embodiment of the present invention.

The digital signal processing section 15 comprises a DSP 11 and a DAC 12. Digital signal Din
Is subjected to a predetermined calculation by the DSP 11 and converted into an analog signal by the DAC 12. In the digital signal processing unit 15, the level of the digital signal is narrowed down to 1 / n.

When the digital signal Din is so-called digital zero, the digital zero detection circuit 17 outputs a detection signal. The gain control circuit 18 is the digital zero detection circuit 1
When the detection signal 7 is received, the gain of the variable gain circuit (analog amplifier) 16 is gradually reduced.

The switch 20 normally selects and outputs the output signal of the variable gain circuit 16, but after the gain of the variable gain circuit 16 becomes small to some extent, it is switched to the side of the reference voltage generating circuit 19 and the reference voltage is generated. It will output voltage.

The switching timing of the switch 20 can be controlled by a delay circuit or the like. As a result, at the time of digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated.

8 and 9 show a specific example of the digital signal processing device of FIG. In the digital signal processing device of FIG. 8, the switch 14 switches between the OFF mode and the ON mode of the DSP.

That is, when the DSP 11 is in the OFF mode, the digital signal Din is directly converted into an analog signal by the DAC 12, and the analog signal is output via the switch 20 and the variable gain circuit 16.

When the DSP 11 is in the ON mode,
When it is not digital zero, the digital signal Din is D
It is input to SP11 and is subjected to predetermined processing by DSP11. In the DSP 11, the digital signal level is 1 /
Since it is narrowed down to n, the gain of the analog signal is adjusted by the variable gain circuit 16 to match the level in the OFF mode.

Further, when the DSP 11 is in the ON mode,
When digital zero, digital signal Din is DSP
It is input to the DAC 12 via 11. When the digital zero detection circuit 17 detects that it is a digital zero,
The detection signal is output to the gain control circuit 18 and the switch 20, respectively.

Upon receiving the detection signal from the digital zero detection circuit 17, the gain control circuit 18 gradually reduces the gain of the variable gain circuit 16. Further, the switch 20 is switched to the reference voltage generation circuit 19 side after the gain of the variable gain circuit 16 is reduced to some extent.

Therefore, even when the DSP 11 is in the ON mode and digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated. In the digital signal processing device of FIG. 9, the digital zero detection circuit 17 detects the digital zero based on the digital signal input to the DSP 11.

That is, when the DSP 11 is in the OFF mode,
The digital signal Din is directly converted into an analog signal by the DAC 12, and the analog signal is output via the variable gain circuit 16.

Further, when the DSP 11 is in the ON mode,
When it is not digital zero, the digital signal Din is D
It is input to SP11 and is subjected to predetermined processing by DSP11. In the DSP 11, the digital signal level is 1 /
Since it is narrowed down to n, the gain of the analog signal is adjusted by the variable gain circuit 16 to match the level in the OFF mode.

Further, when the DSP 11 is in the ON mode,
When digital zero, digital signal Din is DSP
It is input to the DAC 12 via 11. When the digital zero detection circuit 17 detects that it is a digital zero,
The detection signal is output to the gain control circuit 18 and the switch 20, respectively.

Upon receiving the detection signal of the digital zero detection circuit 17, the gain control circuit 18 gradually reduces the gain of the variable gain circuit 16. Further, the switch 20 is switched to the reference voltage generation circuit 19 side after the gain of the variable gain circuit 16 is reduced to some extent. Therefore, DSP11 is ON
In the mode and digital zero, only the noise component is not amplified and the S / N ratio is not deteriorated.

[0059]

As described above, the digital signal processing device of the present invention has the following effects. The digital zero detection circuit detects digital zero (no signal input state between songs or at pause), and gradually lowers the gain of the variable gain circuit (analog amplifier) at digital zero. In addition, the variable gain circuit is configured to output the reference voltage after gradually reducing the gain, and is muted. As a result, even if the DSP becomes digital zero in the ON mode, the noise component is not amplified, so that the S / N ratio can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal processing device according to a first embodiment of the invention.

FIG. 2 is a block diagram showing a specific example of the digital signal processing device of FIG.

FIG. 3 is a block diagram showing a specific example of the digital signal processing device of FIG.

FIG. 4 is a block diagram showing a digital signal processing device according to a second embodiment of the invention.

5 is a block diagram showing a specific example of the digital signal processing device of FIG.

6 is a block diagram showing a specific example of the digital signal processing device of FIG.

FIG. 7 is a block diagram showing a digital signal processing device according to a third embodiment of the invention.

8 is a block diagram showing a specific example of the digital signal processing device of FIG.

9 is a block diagram showing a specific example of the digital signal processing device of FIG.

FIG. 10 is a block diagram showing a conventional digital signal processing device.

[Explanation of symbols]

11 ... DSP (digital signal processor), 12 ... DAC (digital-analog converter), 13 ... Analog amplifier, 14 ... Switch, 15 ... Digital signal processing section, 16 ... Variable gain circuit (analog amplifier), 17 ... Digital zero detection circuit , 18 ... Gain control circuit, 19 ... Reference voltage generating circuit, 20 ... Switch.

Claims (4)

[Claims] 1. A digital signal processing unit for processing a digital signal and converting it into an analog signal, a variable gain circuit for adjusting a gain and outputting the analog signal, and a digital signal indicating a no-signal input state, And a means for gradually reducing the gain of the variable gain circuit. 2. A digital signal processing unit for processing a digital signal and converting it into an analog signal, a variable gain circuit for adjusting the gain and outputting the analog signal, and a variable gain circuit for selecting the analog signal and a reference voltage. A switch for outputting to the gain circuit; and means for controlling the reference voltage to be output to the variable gain circuit after gradually reducing the gain of the variable gain circuit when the digital signal indicates a no-signal input state. A digital signal processing device comprising: 3. A digital signal processing unit for processing a digital signal and converting it into an analog signal, a variable gain circuit for adjusting the gain and outputting the analog signal, and an output signal of the variable gain circuit and a reference voltage are selected. And a means for controlling the output of the reference voltage after gradually reducing the gain of the variable gain circuit when the digital signal indicates a no-signal input state. And a digital signal processing device. 4. The digital signal processing section, a DA converter for converting a digital signal into an analog signal, an arithmetic circuit for performing a predetermined arithmetic operation on the digital signal, and a digital signal to the DA converter via the arithmetic circuit. 4. The digital signal processing device according to claim 1, further comprising a switch for selecting whether to directly guide the digital signal to the DA converter.