WO2007010742A1

WO2007010742A1 - Class d power amplifier

Info

Publication number: WO2007010742A1
Application number: PCT/JP2006/313289
Authority: WO
Inventors: Hiroyuki Ishihara; Minoru Yoshida; Yasunori Suzuki
Original assignee: Pioneer Corporation
Priority date: 2005-07-21
Filing date: 2006-07-04
Publication date: 2007-01-25
Also published as: JPWO2007010742A1; JP4688175B2

Abstract

A small-sized class D power amplifier in which the nonlinear distortion caused when switching is carried out is adequately prevented. In order to correct the nonlinear distortion caused when switching is carried out, the class D power amplifier (100) calculates the error signal between a PWM signal before switching and the PWM signal after the switching, directly varies the phase of a base clock signal according to the variation of the calculated error signal each time the PCM value is updated or varies the phase of the base clock signal relatively to the PCM value of the PCM signal by correcting the PCM value. The class D power amplifier (100) carries out pulse width modulation of the PCM signal with the relatively varied base clock signal.

Description

Specification

Class D power amplifier

Technical field

[0001] The present invention belongs to a technical field of a power amplifying apparatus that performs nonlinear distortion correction.

Background art

[0002] In recent years, there has been a demand for a specification that can reproduce 5.1 channels in a stereo system that integrates speakers, amplifiers, CD players, etc., called mini-components. On the other hand, mini-components are required to be miniaturized due to design problems, and miniaturization of each circuit is required. In particular, miniaturization of power amplifying devices is required.

Recently, due to the demand for downsizing of such a power amplifying device, for example, a signal input to a power amplifying device such as a PCM (Pulse Code Modulation) signal is applied to pulse width modulation (PWM). The signal is amplified after being converted to a digitally modulated signal by performing modulation processing such as pulse density modulation (PDM) and output to the analog signal via a low-pass filter. Power amplifiers using Class D power amplification are becoming popular.

[0004] A power amplifying apparatus using this class D power amplifying method (hereinafter referred to as "class D power amplifying apparatus").

) Theoretically because the signal is amplified by turning on and off the switching elements in the output stage of the amplifying part located in front of the low-pass filter based on the digital modulation signal generated based on the input signal. 100% power efficiency can be obtained, and this high efficiency can reduce the size of the power amplifier.

[0005] Conventionally, as a power amplifying apparatus using such a class D power amplifying method, one that corrects nonlinear distortion by adjusting the width of an edge of a pulse signal input based on a reference signal. Are known.

[0006] Specifically, this power amplifying device generates a predetermined trapezoidal wave signal as a reference signal and changes the slice level in order to correct nonlinear distortion in the switching element. By adjusting the edge width of the input pulse signal, negative feedback control is performed (for example, Patent Document 1).

Patent Document 1: Special Table 2001—517393 (International Publication W098Z44626 Pamphlet b)

Disclosure of the invention

Problems to be solved by the invention

[0007] However, in the conventional class D power amplifier, in order to accurately correct the edge width adjustment of the pulse signal, it is necessary to generate a highly accurate trapezoidal wave signal as a reference signal. In order to generate the high-accuracy trapezoidal wave signal, the scale of the generation circuit becomes large, which may affect the miniaturization of the power amplifying device.

[0008] Further, in this class D power amplifying device, the edge width is adjusted based on the slice level, and therefore depends on the slope of the edge in the generated trapezoidal wave. Therefore, this class D power amplifying device ensures a sufficient amount of correction for edge width correction because the slope of the edge becomes steep when the clock frequency becomes high, and the generated trapezoidal wave becomes close to a rectangular wave. I can't.

[0009] The present invention solves an example of the above-mentioned problem by accurately preventing nonlinear distortion that occurs when switching processing is performed, and is applicable to high frequencies and can be downsized. It is to provide a class D power amplifier.

Means for solving the problem

[0010] In order to solve the above-mentioned problem, the invention according to claim 1 is a class D power amplifying device that performs pulse width modulation on a sound signal, amplifies the pulse-modulated sound signal, and outputs the amplified sound signal to a speaker. Receiving means for receiving a sound signal which is a digital signal; first generating means for pulse-modulating the received sound signal based on the clock signal to generate a pulse width modulated signal; and the generated pulse A second generation means for switching a power supply voltage in accordance with the width modulation signal and amplifying the signal level of the pulse width modulation signal to generate a voice signal; and an error between the generated pulse width modulation signal and the voice signal A detection means for detecting an error signal indicating a difference between the phase of the clock signal used by the first generation means and the received sound signal based on the detected error signal. Make And a phase change means.

Brief Description of Drawings

FIG. 1 is a block diagram showing a configuration in a first embodiment of a class D power amplifier according to the present application.

FIG. 2 is a block diagram showing a configuration of a phase conversion circuit in the first embodiment.

FIG. 3 is a block diagram showing a configuration of a PCMZPWM conversion unit in the first embodiment.

FIG. 4 is a flowchart showing the operation of main processing in the shift amount control circuit of the first embodiment.

FIG. 5 is a flowchart (I) showing an operation of shift amount determination processing in the shift amount control circuit of the first embodiment.

FIG. 6 is a flowchart showing an operation of shift amount determination processing in the shift amount control circuit of the first embodiment (11).

FIG. 7 is a flowchart (III) showing an operation of shift amount determination processing in the shift amount control circuit of the first embodiment.

FIG. 8 is a flowchart showing an operation of correction value determination processing in the shift amount control circuit of the first embodiment.

FIG. 9 is a flowchart showing an operation of a total shift amount calculation process in the shift amount control circuit of the first embodiment.

FIG. 10 is a flowchart showing an operation of PCMZPWM conversion processing in the PCMZPWM conversion unit of the first embodiment.

FIG. 11 is a timing chart (I) showing switching between the output PWM signal and the shift clock signal in the PCMZPWM converter of the first embodiment.

FIG. 12 is a timing chart (Π) showing switching between the output PWM signal and the shift clock signal in the PCMZPWM converter of the first embodiment.

FIG. 13 is a block diagram showing a configuration of a phase conversion circuit in a second embodiment.

FIG. 14 is a block diagram showing a configuration of a PCMZPWM conversion unit in the second embodiment.

FIG. 15 is a flowchart showing the operation of the PCMZPWM conversion process in the PCMZPWM converter of the second embodiment. [FIG. 16] Output PWM signal and shift clock 1 in the PCMZPWM converter of the second embodiment

A timing chart showing switching between the 1 signal and the shift clock 2 signal.

Yes

Explanation of symbols

… Class D power amplifier

101… Oversampling processor

102… Noise shaving circuit

103… Clock signal generator

105… Correction processing section

106… Shift amount control circuit

108… Switching amplifier circuit

109… LPF

110… Amplifier

111… Error signal calculator

112… Voltage detector

113… Shift amount information generator

200… Phase conversion circuit

201, 211… Input distributor

202, 212… Main delay circuit

203, 213… 1st selector

204… Sub delay circuit

205… 2nd selector

206, 219… Control unit

207… 3rd selector

208… Sub delay circuit

209… 4th selector

300… PCMZPWM converter

301… Start counter

302, 401… Up counter 303… Contortor

304, 406… RS—FF circuit

402… Down counter

403… Start indication circuit

404… 1st comparator

405… 2nd comparator

SP… Speaker

BEST MODE FOR CARRYING OUT THE INVENTION

Next, embodiments suitable for the present application will be described with reference to the drawings.

In the embodiment described below, a PCM signal read from a recording medium recorded as a digital signal such as a CD (Compact Disc) is input, and the signal of the input PCM signal is input. This is an embodiment in which the class D power amplifying apparatus of the present application is applied to a class D amplifying apparatus that amplifies the level and outputs it to a speaker. The following description is also applicable to a class D power amplifying apparatus that uses a lch class D power amplifying apparatus, a stereo, a 5. lch or a 7. lch multi-channel speaker.

[First Embodiment]

First, a first embodiment of a class D power amplifier according to the present application will be described with reference to FIGS.

First, the configuration of the class D power amplifying apparatus in the present embodiment will be described using FIG. 1 and FIG. FIG. 1 is a block diagram showing the configuration of the class D power amplifying apparatus of the present embodiment, and FIG. 2 is a block diagram showing the configuration of the phase conversion circuit in the present embodiment.

[0017] The class D power amplifying apparatus 100 of the present embodiment performs pulse width modulation on a PCM signal input based on a predetermined base clock signal to generate a PWM signal. A process for switching the power supply voltage in accordance with the generated PWM signal (hereinafter referred to as “switching process”) is executed to output a PWM signal whose signal level is amplified to the SP force SP. .

[0018] In particular, the class D power amplifying apparatus 100 according to the present embodiment performs the switching process. In order to correct the generated nonlinear distortion, as described later, an error signal between the PWM signal before the switching process and the PWM signal after the switching process is calculated. The base clock signal phase is changed directly every time the PCM signal value (hereinafter referred to as “PCM value”) is updated or the PCM value is corrected according to the change. The phase of the signal is changed relative to the PCM value of the PCM signal. The class D power amplifying apparatus 100 performs pulse width modulation on the PCM signal based on the base clock signal that is relatively changed.

This class D power amplifying apparatus 100 includes an oversampling processing unit 101 and a noise shaving circuit 102 that perform over-sampling processing and noise-shaping pink processing as preprocessing on an input PCM signal, A clock signal generator 103 that generates a base clock signal as a reference during operation, a phase conversion circuit 200 that changes the phase of the generated base clock signal, and a correction that corrects each PCM value of the preprocessed PCM signal The phase conversion circuit 200 and the correction processing unit 105 are controlled based on the processing unit 105 and a phase amount calculated every time the PCM value is updated (hereinafter also referred to as “shift amount”), as will be described later. And a PCMZPWM conversion unit 300 that generates a PWM signal by performing pulse width modulation on the corrected PCM signal under the control of the phase conversion circuit 200. Ru Te.

[0020] In addition, the class D power amplifying apparatus 100 performs switching processing based on the generated PWM signal, and a switching amplifier circuit 108 that amplifies the signal level of the PWM signal by k times. A low-pass filter (hereinafter referred to as “LPF”) 109 that performs filtering on the amplified PWM signal to generate a loud sound signal, an amplifier 110 that multiplies the signal level of the loud sound signal by 1 Zk, and is multiplied by lZk. And an error signal calculation unit 111 for calculating an error signal between the loudspeaker signal and the PWM signal output from the PCMZPWM conversion unit 300.

Furthermore, this class D power amplifying apparatus 100 includes a voltage detection unit 112 that detects a voltage value of an error signal that has been converted to a DC voltage (DC value), and a shift amount according to a change in the detected voltage value. Shift amount information generating section 113 for generating shift amount information (hereinafter referred to as “shift amount information”) each time the PCM value is updated based on the calculated shift amount. Yes is doing.

[0022] Note that, for example, the phase conversion circuit 200, the correction processing unit 105, and the shift amount control circuit 106 of the present embodiment constitute phase change means of the present invention, and the PCMZPWM conversion unit 300 includes the reception means of the present invention. Configure the first generation means. Further, for example, the switching amplifier circuit 108 of the present embodiment constitutes the second generation means of the present invention, and the voltage detection unit 112 and the shift amount information generation unit 113 constitute the detection means of the present invention.

[0023] The PCM signal is input to the oversampling processing unit 101 via the input terminal T, and the base clock signal generated by the clock signal generation unit 103 is input via the phase conversion circuit 200. The oversampling processing unit 101 performs oversampling processing on the input PCM signal based on the base clock signal, and the PCM signal subjected to the oversampling processing is subjected to noise shaping. One bing circuit 102 outputs the signal.

[0024] For example, the oversampling processing unit 101 of the present embodiment executes processing for sampling an input PCM signal, such as 4 times or 8 times, at a sampling frequency that is a predetermined multiple of the sampling frequency of the PCM signal. It is supposed to be.

[0025] The noise shaving circuit 102 is supplied with the oversampled PCM signal and the base clock signal generated by the clock signal generation unit 103 via the phase conversion circuit 200. Based on the base clock signal, the noise shaving circuit 102 reduces the number of quantization bits from the input PCM signal to a predetermined number of bits (N bits), and shifts the quantization noise to a high frequency band. A pink treatment is applied. In addition, the noise shaving circuit 102 outputs a PCM signal that has been subjected to noise shear pink processing to a correction processing unit 105.

The clock signal generation unit 103 generates a base clock signal based on a clock frequency of a predetermined base signal (hereinafter referred to as “base signal”), and the generated base clock The signal is output to the phase conversion circuit 200 and the oversampling processing unit 101, the noise shaving circuit 102, and the PCMZPWM conversion unit 300 via the phase conversion circuit 200.

Note that the relationship between the base signal and the base clock signal is as follows. Is determined by the step amount of the phase interval. For example, when the phase interval step is 90 degrees as shown in Figure 2, the base clock signal is 1Z2 of the base signal, and when the phase interval step is 180 degrees, the base clock frequency is Same as signal.

[0028] The base clock signal generated by the clock signal generation unit 103 is input to the phase conversion circuit 200. The phase conversion circuit 200 changes the phase of the base clock signal. Therefore, as will be described later, based on the shift amount set by the shift amount control circuit 106, the phase of the input base clock signal is converted or not converted, and the phase is converted or the phase is not converted. A base clock signal (hereinafter referred to as a “shift clock signal”, and a signal whose phase is not converted is also referred to as a shift clock signal for convenience) is output to the PCMZPWM converter 300 together with a base clock signal whose phase is not changed. It is like that.

Specifically, the phase conversion circuit 200 controls the phase of the input base clock signal within the range of “+270” degrees to “270” degrees under the control of the shift amount control circuit 106. Then, the converted shift clock signal is output to the PCMZPWM conversion unit 300 together with the base clock signal without changing the phase.

For example, as shown in FIG. 2, the phase conversion circuit 200 according to the present embodiment includes an input distributor 201 that distributes an input base clock to a plurality of degrees, from “+270” degrees to “−270” degrees.複数 Multiple main delay circuits 202 that change the phase of the base clock signal at a phase interval of “90” degrees, a first selector 203 that controls the output of each main delay circuit 202, and “0” degrees to Within the range of “90” degrees, under the control of a plurality of sub-delay circuits 204 that give a predetermined phase difference, the second selector 205 that controls the output of each sub-delay circuit 204, and the shift amount control circuit 106, The shift amount determined by the shift amount control circuit 106 is set, and the control unit 206 controls the first selector 203 and the second selector 205 based on the set shift amount, and the input base Change the phase of the clock signal In addition to the base clock signal distributed by the input distributor, a shift clock signal is generated, and the generated shift clock signal is output to the PCMZPWM converter 300 together with the base clock signal. RU It should be noted that the phase conversion circuit 200 of the present embodiment outputs a base clock signal to the PCMZPWM conversion unit 300 together with the shift clock signal for use in generating a PWM signal by the PCMZPWM conversion unit 300. Thus, the base clock signal is output to the oversampling processing unit 101 and the noise shaving circuit 102 which are connected by the PCM ZPWM conversion unit 300 alone.

In addition, for example, the control unit 206 of the present embodiment changes the phase of the shift clock signal at the rising edge of the PWM signal in conjunction with the PCMZPWM conversion unit 300, as will be described later. Based on the shift amount determined in step 1, the switching control of the first selector 203 and the second selector 205 is performed in synchronization with “0” of the start counter 301 in the PCMZP WM conversion unit 300 described later. The

[0033] Further, the phase interval in the main delay circuit 202 may be set at an arbitrary phase interval of not only "90" degrees but also 45 degrees, for example! /.

[0034] The correction processing unit 105 receives a PCM signal that has been subjected to noise-shaping pink processing. The correction processing unit 105 is provided in the shift amount control circuit 106 as described later. Based on the determined correction value, a predetermined correction process is performed on each PCM value of the input PCM signal and the result is output to the PCMZPWM conversion unit 300.

Specifically, as will be described later, the correction processing unit 105 converts each PCM value of the input PCM signal under the control of the shift amount control circuit 106 based on the generated shift amount information. On the other hand, correction processing for adding “1” or subtracting “1” is performed.

In the present embodiment, the correction processing unit 105 adds “0” to the PCM value and outputs the PCM signal to the PCMZPWM conversion unit 300 when no correction processing is performed. It has become.

[0037] As will be described later, the shift amount control circuit 106 includes the phase information flag value (F) generated as shift amount information in the shift amount information generation unit 113 and the PCM signal output from the noise shaving circuit 102. That is, the PCM value in the PCM signal is input. The shift amount control circuit 106 uses the total shift amount (hereinafter referred to as “total shift amount”) based on the control based on the input shift amount information and the previous PCM value. b) The previous shift amount (hereinafter referred to as “previous shift amount”) and the input P Each time the PCM value is updated based on the PCM value of the CM signal, the PCMZPWM converter 300 changes the phase of the base clock signal relative to the input PCM signal to generate the shift clock signal. In order to generate the data, that is, to cause the phase conversion circuit 200 to execute at least one of the phase change of the base clock signal and the correction processing unit 105 to execute the PCM value correction processing, the shift amount is determined. A predetermined process (hereinafter referred to as “main process”) is performed.

Specifically, the shift amount control circuit 106 calculates and calculates a shift amount in the current PCM value (hereinafter referred to as “shift update amount”) based on the input shift amount information. A process for determining the current shift amount (hereinafter simply referred to as “phase shift amount”) based on the previous shift update amount and the previous shift amount set previously (hereinafter referred to as “shift amount determination process”). And the determined phase shift amount is set in the phase conversion circuit 200.

Further, the shift amount control circuit 106 uses the value of a flag for performing correction (to be described later) (hereinafter referred to as “correction flag value (H)”) for each total shift amount (b). Each time the PCM value is updated, a calculation process (hereinafter referred to as “total shift amount calculation process”) is performed.

Further, the shift amount control circuit 106 uses a correction value “0”, “one 1” or “+1” for correcting the PCM value input by the correction processing unit 105. The correction processing is performed (hereinafter referred to as “correction value determination processing”), and the determined correction value is set in the correction processing unit 105. For example, when the calculated total shift amount (b) is a value of “+270” degrees or more, the shift amount control circuit 106 determines the correction value as “+1” and also determines the total shift amount (b) When the value is greater than “−270” degrees, the correction value is determined as “—1”, and the total shift amount (b) is larger than “—270” degrees and smaller than “+270” degrees. When it is a value, the total shift amount (b) is determined to be “0”.

Note that this shift amount control circuit 106 has a minimum or maximum PCM value in the input PCM signal, and the phase information flag value (F) output from the shift amount information generation unit 113 is a predetermined value. In the case of the above information, the PCMZPWM converter 300 is not connected to the PCMZPWM converter 300 due to the destruction or malfunction of the device due to the followability of the switching element in the switching amplifier circuit 108. Thus, neither phase difference control nor correction processing control in the correction processing unit 105 is performed. Then, the shift amount control circuit 106 temporarily stores the input phase information flag value (F), the calculated total shift amount (b), and the set phase shift amount in an internal memory. It becomes.

[0042] Details of main processing including shift amount determination processing, total shift amount calculation processing, and correction value determination processing in the shift amount control circuit 106 of the present embodiment will be described later.

[0043] The PCMZPWM converter 300 is inputted every time the PCM signal power PCM value is updated. The PCMZPWM converter 300 receives an input based on the base clock signal and the shift clock signal. The PCM signal is subjected to pulse width modulation to generate a PWM signal and output it to the switching amplifier circuit 108 and the error signal calculation unit 111.

[0044] The configuration and operation of the PCMZPWM conversion unit 300 of the present embodiment will be described later in detail.

The switching amplifier circuit 108 is inputted with a pulse width modulated PWM signal. The switching amplifier circuit 108 is, for example, a MOS (Metal Oxide Semiconductor) transistor, a field effect transistor (hereinafter referred to as “FET: Field Effect Transistor J”) FET, and a driving voltage for driving the speaker SP. A DC power supply for applying a voltage, and performs predetermined control such as switching control of the input PWM signal, and amplifies the signal level of the PWM signal to k times, that is, to the predetermined signal level. The switching amplifier circuit 108 outputs the amplified PWM signal to the LPF 109 and the amplifier 110.

[0046] The PWM signal amplified to a predetermined level is input to the LPF 109, and the LPF 109 is configured to block high frequency with respect to the input PWM signal in order to remove high frequency noise. A loudspeaker signal is generated by processing, and the generated loudspeaker signal is output to the speaker SP.

[0047] A PWM signal amplified to a predetermined signal level is input to the amplifier 110. The amplifier 110 calculates one signal when calculating an error signal, that is, a PC MZPWM converter. Input for consistency with PWM signal output directly from 300 The amplified PWM signal level is amplified by (lZk) times, and the PWM signal whose signal level is amplified by (lZk) times is output to the error signal calculation unit 111.

[0048] The error signal calculation unit 111 receives the PWM signal output from the switching amplifier circuit 108 and the PWM signal output from the PCMZPWM conversion unit 300. The error signal calculation unit 111 111 calculates an error signal based on each input signal, and outputs the calculated error signal to the voltage detection unit 112.

Specifically, the error signal calculation unit 111 of the present embodiment is configured by a subtracter, and subtracts the PWM signal output from the PCMZPWM conversion unit 300 from the PWM signal output from the switching amplifier circuit 108. Then, an error signal is generated! /

[0050] The voltage detection unit 112 is configured to receive the error signal whose DC value has been input by the integrator 112. The voltage detection unit 112 detects the voltage value of the input error signal. Then, the detected voltage value is output to the shift amount information generation unit 113.

[0051] The shift amount information generation unit 113 receives the voltage value detected by the voltage detection unit 112, and the shift amount information generation unit 113 receives the voltage value based on the input voltage value. A predetermined phase information flag value (F) is determined each time the PCM value is updated, and the determined phase information flag value (F) is output to the shift amount control circuit 106 as shift amount information. Yes.

Specifically, the shift amount information generation unit 113 sets the input voltage value to a value smaller than a predetermined first threshold (hereinafter referred to as “first threshold (−Ve) ^”). There is a force that is greater than or equal to the first threshold and less than “0”, a force that is “0” and a value that is greater than “0” and less than or equal to the second threshold (hereinafter referred to as “second threshold (Ve)”). And whether the value is larger than the second threshold value. When the voltage value is smaller than the first threshold, the shift amount information generating unit 113 sets the phase information flag value (F) for providing a phase difference of “−90” degrees to the first threshold or higher. When the value is smaller than “0”, a negative phase difference (one D) based on the voltage value is calculated, and the phase information flag value (F) for providing the phase difference is output to the shift amount control circuit 106. It ’s like that. In addition, as a result of the determination based on the input voltage value, the shift amount information generation unit 113 determines that the positive value based on the voltage value is greater than “0” and equal to or less than the second threshold value. A phase information flow for calculating the phase difference (+ D) and providing the phase difference. When the lag value (F) is larger than the second threshold, the movement information flag value (F) for providing a phase difference of “+90” degrees is output to the shift amount control circuit 106. The

For example, the shift amount information generation unit 113 of the present embodiment outputs the phase information flag value (F) as 3-bit data and calculates the phase difference when the phase difference is calculated. When the voltage value is less than the first threshold, the value is “011”. When the value is greater than “000” “0” and less than or equal to the second threshold value, the values “101” and “+ D”, and when greater than the second threshold value, each flag information “111” and a predetermined value This information is output to the shift amount control circuit 106 as shift amount information.

Note that the shift amount information generation unit 113 has a configuration that can appropriately calculate the phase difference “± D” in association with the phase difference given by the phase conversion circuit 200. For example, lnsec to 6nse The phase difference of c can be calculated.

Next, the configuration and operation of the PCMZPWM conversion unit 300 of this embodiment will be described using FIG. FIG. 3 is a block diagram showing the configuration of the PCMZPWM conversion unit 300 in this embodiment.

[0056] The PCMZPWM conversion unit 300 of the present embodiment operates based on a base clock signal, and starts a counter 301 that counts based on an input PCM signal, and an up counter that counts up based on a shift clock signal 302, a comparator 303 that compares the PCM value in the input PCM signal with the output of the up counter 302, and a synchronous flip-flop circuit that generates a PWM signal based on the outputs of the start force counter 301 and the comparator 303 And “RS-FF circuit”.) 304.

The base clock signal generated by the clock signal generation unit 103 is input to the start counter 301 via the phase conversion circuit 200. The start counter 301 is input to the start counter 301. Based on the clock signal, for example, when the number of output bits of the noise shaving circuit 102 is 6, the count from “0” to “63” is repeated, and when “0” is output, the RS-FF circuit In addition to outputting a signal instructing the rising edge of the PWM signal to 304, a signal instructing the count start in the up counter 302, that is, a signal for setting the counter of the up counter 302 to “0” is output. Become The

[0058] The up counter 302 is supplied with the shift clock signal output from the phase conversion circuit 200 and the start instruction output from the start counter 301. The up counter 302 is based on the start instruction. Thus, the shift clock is counted from “0”, and the counted value (hereinafter “count value”) is output to the comparator 303 as data.

[0059] The comparator 303 compares the PCM value of the input PCM signal with the count value output from the up counter 302, and when the PCM value and the count value become the same value, the RS-FF circuit A signal to instruct the PWM signal to fall is output to 304.

[0060] The RS-FF circuit 304 is supplied with a signal indicating the rising edge of the PWM signal from the start counter 301 and a signal indicating the falling edge of the PWM signal from the comparator 303. The RS-FF circuit 304 raises the PWM signal that is output when a signal that instructs rising is input, and also causes the PWM signal that is output to decrease when a signal that instructs to decrease is input. It has become.

Note that details of the operation of the PCMZPWM conversion unit 300 according to this embodiment for converting the PCM signal into a PWM signal (hereinafter referred to as “PCMZPWM conversion process”) will be described later.

Next, main processing in the shift amount control circuit 106 in the present embodiment will be described with reference to FIG. FIG. 4 is a flowchart showing the main processing in the shift amount control circuit 106 in the present embodiment.

In this operation, the shift amount control circuit 106 is interlocked with the noise shaving circuit 102, the PCMZPWM conversion unit 300, the correction processing unit 105, and the phase conversion circuit 200 based on the base clock signal. Note that the clock signal generator 103 generates a base clock signal when the process of generating the PWM signal is started.

[0064] First, generation of a PWM signal is started based on a predetermined instruction such as an instruction from an operator. When the shift amount control circuit 106 detects this start (step Sl l), the shift amount control circuit 106 clears the values set in the phase conversion circuit 200 and the correction processing unit 105, Each value is initialized (step S12). Specifically, the shift amount control circuit 106 sets the values of the phase information flag value (F), the total shift amount (b), and the phase shift amount (S) to “0” as an initial setting.

Next, the shift amount control circuit 106 reads the values of the phase information flag value (F), the total shift amount (b), and the phase shift amount (S) from an internal memory not shown (step) S 13).

Next, the shift amount control circuit 106 performs shift amount determination processing for determining the shift update amount and the phase shift amount (S), and sets the value in the phase conversion circuit 200 (step S 14). . Specifically, the shift amount control circuit 106 determines the shift update amount, the shift amount, and the total shift amount (b) based on the read phase information flag value (F), and the phase information flag value ( Set the correction flag value (H) based on F).

Note that details of the operation of the shift amount determination process in the shift amount control circuit 106 of the present embodiment will be described later. The correction flag value (H) is a flag value for determining conditions in the correction value determination process and the total shift amount calculation process.

Next, the shift amount control circuit 106 determines a value to be used for the correction process in the correction processing unit 105 based on the correction flag value (H) set in the process of step S 13. And set the correction processing unit 105 (step S15). Specifically, the shift amount control circuit 106 determines the correction value as “0”, “−1” or “1” based on the correction flag value (H), and corrects the determined correction value. Set to part 105.

Note that details of the operation of the correction value determination process in the shift amount control circuit 106 of the present embodiment will be described later.

Next, the shift amount control circuit 106 performs a total shift amount calculation process for calculating the total shift amount (b) based on the correction flag value (H) set in the process of step S 13, The determined total shift amount (b) is stored in the internal memory (step S16).

The details of the operation of the total shift amount calculation process in the shift amount control circuit 106 of the present embodiment will be described later.

[0072] Next, the shift amount control circuit 106 determines whether or not there is an input of a PCM value in the next PCM signal, including detection of the end in the process of generating the PWM signal (step S17), and If there is a PCM value input in the PCM signal, the process in step S13 If the PCM value is not entered, the operation is terminated.

[0073] It should be noted that the shift amount control circuit 106 in the process of generating a PWM signal based on an instruction indicating the presence or absence of the PCM value in the input PCM signal, such as the control unit 206 (not shown), in the process of step S16 When the end is detected, it is detected that there is no PCM value input in the next PCM signal.

As described above, when the shift amount and the correction value are determined and each value is set in the phase conversion circuit 200 and the correction processing unit 105, the phase conversion circuit 200 generates P every time the PCM value is updated. Based on the phase shift amount (S) set in conjunction with the start counter 301 in the CMZPWM converter 300, the first selector 203 and the second selector 205 are switched to generate a shift clock signal, and the correction processor 105 Each time the PCM value is updated, the PCM value in the PCM signal that has been subjected to the oversampling process and the noise shaving process is corrected based on the set correction value and output to the PCMZPWM converter 300. Then, each time the PCM value is updated, the PCMZPWM converter 300 generates a PWM signal based on the relatively changed shift clock signal, and the generated PWM signal is passed through the switching amplifier circuit 108. Output to speaker SP.

Next, a shift amount determination process in the shift amount control circuit 106 of the present embodiment will be described with reference to FIGS. 5 to 7 are flowcharts showing the shift amount determination process in the shift amount control circuit 106 of the present embodiment.

This shift amount determination process is a process executed during the main process, and is a process for determining the shift update amount and the phase shift amount (S).

[0077] First, the shift amount control circuit 106 determines whether or not the input PCM value is a predetermined minimum value (min) (step S101), and the input PCM value is determined in advance. When it is determined that the input value is the minimum value, the process proceeds to step S102, and when it is determined that the input PCM value is not the predetermined minimum value, the process proceeds to step S103.

Next, when the shift amount control circuit 106 determines that the PCM value is a predetermined minimum value in the process of step S101, the phase information flag value (F) read out during the main process is determined. Determine whether the power is “111” or “101” (step S102) When it is determined that the phase information flag value (F) is neither “111” nor “101”, the process proceeds to step S105, and when it is determined that it is “111” or “101”, step S Move to 120 processing.

Next, when the shift amount control circuit 106 determines that the PCM value is not a predetermined minimum value in the process of step S101, the input PCM value is determined to be a predetermined maximum value (max ) (Step S103), and if it is determined that the input PCM value is a predetermined maximum value, the process proceeds to step S104, and the input PCM value is If it is determined that the value is not the predetermined maximum value, the process proceeds to step S1 05.

Next, when the shift amount control circuit 106 determines that the input PCM value is the predetermined maximum value in the process of step S103, the phase information flag value ( F) is a force of “011” or “001” (step S104), and the phase information flag value (F) is neither “011” nor “001”! / When it is determined, the process proceeds to step S111, and when it is determined that it is “011” or “001”, the process proceeds to step S120.

Next, the shift amount control circuit 106 determines that the phase information flag value (F) is neither “111” nor “101” in the process of step S102, or in the process of step S103. When it is determined that the input PCM value is not the predetermined maximum value, it is determined whether or not the phase flag value is “011” (step S105), and it is determined that the phase flag value is not “011”. If it is determined, it is determined whether or not the total shift amount (b) is “+270” degrees (step S 106).

Note that when the shift amount control circuit 106 determines that the phase flag value is not “011”, the shift amount control circuit 106 proceeds to the process of step S 111.

Next, when the shift amount control circuit 106 determines that the total shift amount (b) is not “+270” degrees in the process of step S106, the correction flag value (H) is set to “100”. Then, the data is stored in the memory (step S 107), the shift update amount is determined to be “+90” degrees (step S 108), and the process proceeds to step S 121.

On the other hand, the shift amount control circuit 106 performs a total shift amount ( When b) is determined to be “+270” degrees, the correction flag value (H) is set to “101” and stored in the memory (step S 109), and the phase shift amount (S) is set to “0”. (Step S110), and the process proceeds to step S122.

Next, the shift amount control circuit 106 determines that the phase information flag value (F) is neither “011” nor “001” in the process of step S 104, or performs the process of step S 105. If the phase flag value is not “011”, it is determined whether the phase flag value is “11 1” (step S111), and it is determined that the phase flag value is not “111”. If so, it is determined whether or not the total shift amount (b) is “−270” degrees (step S 112).

Note that when the shift amount control circuit 106 determines that the phase flag value is not “111”, the process proceeds to step S116.

Next, the shift amount control circuit 106 sets the correction flag value (H) to “110” when determining that the total shift amount (b) is not “−270” degrees in the process of step S112. Then, the data is stored in the memory (step S 113), the shift update amount is determined to be “−90” degrees (step S 114), and the process proceeds to step S 121.

On the other hand, the shift amount control circuit 106 sets the correction flag value (H) to “111” when determining that the total shift amount (b) is “1270” degrees in the process of step S112. Are stored in memory (step S115), the shift amount is determined to be “0” (step S110), and the process proceeds to step S122.

Next, when the shift amount control circuit 106 determines in the process of step S111 that the phase flag value is not “111”! /, The shift amount control circuit 106 determines whether or not the phase flag value is “001”. (Step S116) When it is determined that the phase flag value is “001”, the shift update amount is determined to be the “+ D” degree calculated by the shift amount information generation unit 113 (Step S117). ), The process proceeds to step S121.

On the other hand, when determining that the phase flag value is not “001”, the shift amount control circuit 106 determines whether or not the phase flag value is “101” (step S118), and the phase flag value is When it is determined that it is “101”, the shift update amount is determined as “−D” degree calculated by the shift amount information generation unit 113 (step S 119), and the process proceeds to step S 121.

Note that when the shift amount control circuit 106 determines that the phase flag value is not “101”, The process proceeds to step S120.

Next, when the shift amount control circuit 106 determines that the phase flag value is “111” or “101” in the process of step S102, the phase flag value is “011” in the process of step S104. Alternatively, when it is determined that it is “001”, or when it is determined that the phase flag value is not “101” in the processing of step S118, the shift update amount is determined to be “0” (step S120). .

Next, when each shift update amount is determined in the processing of steps S108, S114, S117, S119, and SI 20, the shift amount control circuit 106 calculates the determined shift update amount and the previous shift amount. Addition is performed to calculate the phase shift amount (S) (step S121).

Next, the shift amount control circuit 106 uses the phase shift amount (S) set in step S 110, that is, “0” or the phase shift amount (S) calculated in step S 121. The phase shift amount (S) at the PCM value is determined (step S122).

Finally, the shift amount control circuit 106 sets the determined phase shift amount (S) in the phase conversion circuit 200 (step S123), and ends this operation.

Next, shift amount determination processing in the shift amount control circuit 106 of the present embodiment will be described with reference to FIG. FIG. 8 is a flowchart showing correction value determination processing in the shift amount control circuit 106 of this embodiment.

This correction value determination process is a process executed during the main process, and the correction processing unit 105 uses the correction flag value (H) determined in the shift amount determination process described above. This process determines the correction amount of the PCM value to be corrected.

First, the shift amount control circuit 106 reads the correction flag value (H) from the memory, and determines whether the read correction flag value (H) is “101” or “111”. (Step S201). When the shift amount control circuit 106 determines that the correction flag value (H) is either “101” or “111”, the shift amount control circuit 106 proceeds to the process of step S202, and the correction flag value (H) is “ If it is determined that neither “101” nor “111” is determined, the process proceeds to step S205.

Next, when the shift amount control circuit 106 determines that the correction flag value (H) is either “101” or “111” in the process of step S201, the correction flag value (H ) Is “101” (Step S202), and when the correction flag value (H) is “101”, the correction value is determined as “+1” (Step S203). The process proceeds to S206.

On the other hand, when determining that the correction flag value (H) force S is not “101” in the process of step S203, the shift amount control circuit 106 determines the correction value as “−1” (step S204), The process proceeds to step S206.

On the other hand, when the shift amount control circuit 106 determines that the correction flag value (H) force S is neither “101” nor “111” in the process of step S201, it sets the correction value to “0”. Determine (step S203) and proceed to step S206.

Finally, the shift amount control circuit 106 sets the determined correction value in the correction processing unit 105 (step S206), and ends this operation.

Next, the total shift amount calculation processing in the shift amount control circuit 106 of the present embodiment will be described with reference to FIG. FIG. 9 is a flowchart showing the total shift amount calculation processing in the shift amount control circuit 106 of this embodiment.

[0104] This total shift amount calculation process is a process executed during the main process, and the shift amount determination process is performed using the correction flag value (H) determined in the shift amount determination process described above.

This is the process of determining the total shift amount (b) to be used.

First, the shift amount control circuit 106 reads the correction flag value (H) from the memory, and determines whether the read correction flag value (H) is “100” or “110”. (Step S301). The shift amount control circuit 106 has a correction flag value (H) of “100” or “11”.

If it is determined that the value is “0”, the process proceeds to step S302, and the correction flag value

When it is determined that (H) is neither “100” nor “110”, the process proceeds to step S305.

Next, when the shift amount control circuit 106 determines that the correction flag value (H) is either “100” or “110” in the process of step S301, the correction flag value (H) is It is determined whether or not the force is “110” (step S302), and when it is determined that the correction flag value (H) is “110”, the total shift amount (b) stored in the memory is “+90” degrees. Is added to calculate a new total shift amount (b) (step S303), and this operation is terminated. On the other hand, when the shift amount control circuit 106 determines that the correction flag value (H) force S is not “110” in the process of step S303, the shift amount control circuit 106 sets “1” to the total shift amount (b) stored in the memory. ”Is added to calculate a new total shift amount (b) (step S304), and this operation is terminated.

On the other hand, when the shift amount control circuit 106 determines that the correction flag value (H) force S is neither “100” nor “110” in the process of step S301, the shift amount control circuit 106 stores the memory stored in the memory. The tall shift amount (b) is set to “0” (step S305), and this operation ends.

Next, the PC MZPWM conversion process in the PCMZPWM conversion unit 300 according to the present embodiment will be described with reference to FIGS. 10 to 12. FIG. 10 is a flowchart showing the PCMZPWM conversion processing in the PCMZPWM conversion unit 300 of the present embodiment. FIGS. 11 and 12 show this implementation when the number of output bits of the noise shaving circuit 102 is 6 bits. 5 is a timing chart showing switching of the output PWM signal and shift clock signal in the PCMZPWM converter 300 of the embodiment.

[0110] In this operation, the PCMZPWM conversion unit 300 is linked to the shift amount control circuit 106, the correction processing unit 105, and the phase conversion circuit 200 based on the base clock signal, and the base clock signal and the shift clock signal are linked. The following processing is performed based on

[0111] Note that the clock signal generation unit 103 generates a base clock signal when the PWM signal generation process is started, and therefore, when the PWM signal generation process is started, the base clock signal and the shift signal are generated. Clock 1 signal is input. The number of output bits of the noise squeezing circuit 102 is 6 bits.

[0112] First, generation of a PWM signal is started based on a predetermined instruction such as an operator instruction. When the PCMZPWM converter 300 detects this start (step S401), a start force counter 301 and an up counter 302 are detected. Clears the predetermined value and performs the initial setting (step S402).

[0113] Next, the comparator 303 reads the PCM value of the input PCM signal (step S403).

[0114] Next, the start counter 301 starts counting based on the base clock signal (step S404), and outputs a start instruction to the RS-FF circuit 304. The circuit 304 is caused to output a “High” signal as a PWM signal (step S405). When the count is started, the start counter 301 repeats the count from “0” to “63” based on the base clock signal.

Next, up-counter 302 starts counting based on the shift clock signal, and outputs the count value to comparator 303 as needed (step S406).

[0116] Next, the comparator 303 detects whether the value of the counter output from the up counter 302 is the same as the PCM value read in the processing of step S403 (step S407). If it is not the same as the SPCM value, the process of step S407 is repeated until the counter value output by the up counter 302 is the same as the PCM value read in the process of step S403.

On the other hand, when the comparator 303 detects that the value PCM value of the counter output from the up counter 302 is the same, it outputs a predetermined signal to the RS-FF circuit 304, and the RS-FF circuit The 304 is caused to output a “Low” signal as a PWM signal (step S40 8).

[0118] When the processing in step S409 is completed, the present operation proceeds to processing in step S403, and the PCMZPWM conversion processing in the PCMZPWM conversion unit 300 of the present embodiment performs circuit operation according to a predetermined instruction such as turning off the power. Repeats the process until is stopped

As described above, the PCMZPWM conversion unit 300 of this embodiment outputs “High” of the PWM signal based on the base clock signal, and outputs “Low” of the PWM signal based on the shift clock signal. Therefore, if the phase of the shift clock signal is changed by the shift amount set by the shift amount control circuit 106 described above, or the shift amount control circuit 106 When the set correction value of the correction processing unit 105 is calculated, a PWM signal in which nonlinear distortion generated when the switching process is performed is output.

Further, in the present embodiment, when the phase of the shift clock signal is directly changed, the shift clock signal is changed to the shift clock signal whose phase has been changed when the start counter 301 is “0”. It comes to switch. For example, in the case where the PCM value is “2” and a phase difference of “+90” degrees is provided, in this embodiment, as shown in FIG. It is launched when is 0. However, when the start counter 301 is “0”, the phase is changed to the shift clock signal, and the PWM signal is lowered by the changed shift signal. Therefore, the width of the PWM signal must be increased. Can do.

[0122] Further, in the case where the PCM value is "2" and a phase difference of "-90" is provided, in this embodiment, as shown in FIG. Raised when 301 is “0”. However, when the start counter 301 is “0”, the phase is changed to the shift clock signal, and the PWM signal is lowered based on the changed shift clock signal. The signal width can be shortened.

11 and 12 are timing charts when the n-th PCM value is switched to the “n + 1” -th PCM value, and the top signal on the timing chart is the base clock. This is the base signal used to generate the signal and shift clock 1 signal.

[0124] As described above, the class D power amplifying apparatus 100 of the present embodiment is the class D power amplifying apparatus 100 that performs pulse modulation on the PCM signal, amplifies the pulse modulated PCM signal, and outputs the amplified signal to the speaker SP. PCMZPWM conversion unit 300 that receives the PCM signal, modulates the received PCM signal based on the base clock signal, and generates a pulse width modulation signal, and supplies power according to the generated pulse width modulation signal. A switching amplifier circuit 108 that switches voltage and amplifies the signal level of the pulse width modulation signal to generate a loud sound signal, and an error that calculates an error signal indicating an error between the generated pulse width modulation signal and the loud sound signal Based on the signal calculation unit 111 and the calculated error signal, the phase of the base clock signal used by the PCMZPWM conversion unit 300 is changed relative to the received PCM signal. It has a configuration comprising a conversion circuit 200, a.

[0125] With this configuration, the class D power amplifying apparatus 100 of the present embodiment receives the phase of the base clock signal used by the PCMZPWM conversion unit 300 based on the calculated error signal! / Change relative to.

Therefore, the class D power amplifying apparatus 100 of the present embodiment is connected to the switching amplifier circuit 108. Therefore, the phase of the base clock signal can be changed based on the error signal generated, that is, the shift clock signal can be generated, so that the received signal can be received using the shift clock signal. PCM signal power can also generate a PWM signal, and the pulse width of the PWM signal amplified by the switching amplifier circuit 108 can be varied.

As a result, the class D power amplifying apparatus 100 of the present embodiment has a nonlinear distortion that occurs when the switching processing is performed by the switching amplifier circuit 108, that is, the DC power is turned on by the switching amplifier circuit 108. Non-linear distortion caused by switching off can be accurately prevented, and it can be applied to high frequencies, and it requires a dedicated circuit with high accuracy to make the pulse width of the PWM signal variable. Can also be reduced.

Further, in the class D power amplifying apparatus 100 of the present embodiment, the phase conversion circuit 200 converts the phase of the clock signal used by the PCMZPWM conversion unit 300 to the PCM value when the pulse width modulation signal is generated. Since it is changed relatively, nonlinear distortion can be corrected for each PWM signal, and noise when output from the speaker SP can be accurately removed.

In addition, in the class D power amplifying apparatus 100 of the present embodiment, the phase conversion circuit 200 directly changes the phase of the clock signal based on the calculated error signal or receives the PCM signal. It has a configuration in which the phase of the clock signal is changed relative to the received PCM signal by at least one of changing the timing of the hour.

Accordingly, the class D power amplifying apparatus 100 of the present embodiment can perform a shift clock signal within a predetermined range, for example, −270 degrees to +270 degrees, Can be simplified.

[0131] In addition, the class D power amplifying apparatus 100 of the present embodiment is configured so that the error signal calculation unit 111 calculates the error signal based on the output of the PCMZPWM conversion unit 300 and the output of the switching amplifier circuit 108. The error signal calculation unit 111 may calculate the error signal based on the output of the PCMZPWM conversion unit 300 and the output of the LPF 109. In this case, the high-frequency cutoff processing similar to LPF109 is applied to the output of the PCMZPWM converter 300, based on the applied signal! Now calculate the error signal! / Speak. [Second Embodiment]

Next, a second embodiment of the class D power amplifying device according to the present application will be described with reference to FIGS.

In this embodiment, in place of the fact that the PWM modulation method is the single sided method in the first embodiment, the double sided method in which the harmonic distortion is reduced compared to the single sided method, ie, the single sided method. This is characterized in that PWM modulation is performed by controlling the width of the PWM signal from both the rising and falling edges of the signal, and the other points are the same as in the first embodiment, and the same parts are the same. The description is omitted. In addition, the main process in the shift amount control circuit 106 of the present embodiment is the same as that of the first embodiment, and thus the description thereof is omitted.

Note that in this embodiment, each shift clock signal output from the phase conversion circuit 200, that is, the shift clock 1 signal and the shift clock 2 signal are output separately to the PCMZP WM conversion unit. It has become.

First, the phase conversion circuit in the present embodiment will be described with reference to FIG. FIG. 13 is a block diagram showing an example of the configuration of the phase conversion circuit in the present embodiment.

[0136] The phase conversion circuit 200 of the present embodiment changes the phase of the input base clock signal, generates a shift clock 1 signal and a shift clock 2 signal in addition to the base clock signal, and generates each generated The shift clock signal is output to the PCM / PWM converter 300 together with the base clock signal.

For example, as shown in FIG. 13, the phase conversion circuit 200 according to the present embodiment includes an input distributor 211 that distributes an input base clock to a plurality of times, and “+270” degrees to “−270” degrees. In addition, a plurality of main delay circuits 212 that change the phase of the base clock signal at a phase interval of “90” degrees, and a first selector 213 that controls the shift clock 1 signal among the outputs of each main delay circuit 212. Within the range of “0” to “90” degrees, the outputs of the multiple first sub-delay circuits 214 that give a predetermined phase difference for one shift clock signal and the output of each first sub-delay circuit 204 are controlled. The second selector 215 that controls the shift clock 2 signal out of the outputs of each main delay circuit 212 and the shift clock 2 signal within the range of “0” to “90” degrees. , Predetermined phase difference (shift described later) The information generating unit 113 you, Te A plurality of second sub-delay circuits 217 that give the calculated phase difference “D”), a fourth selector 218 that controls the output of each second sub-delay circuit 217, and a shift amount control circuit 106 under the control of the shift A control unit 219 that sets the shift amount determined by the amount control circuit 106 and controls the first selector 213, the second selector 215, the third selector 216, and the fourth selector 218 based on the set shift amount; Consists of

Note that the shift clock 2 signal is supplied to the third selector 206 and the fourth selector 209 based on a value obtained by multiplying the total shift amount calculated by the shift amount control circuit 106, which will be described later, by 11 in the control unit 206. It is generated by controlling. In other words, if the shift amount of the shift clock 1 signal is +90 degrees out of phase with the base clock signal, the shift clock is 90 degrees out of phase with the base clock signal. Two signals are output. However, the phase interval in the main delay circuit 202 may be set at an arbitrary phase interval such as 45 degrees in addition to the above “90” degrees.

Further, for example, as will be described later, the control unit 219 of the present embodiment interlocks with the PCMZPWM conversion unit 300 to rise the PWM signal with the shift clock 1 signal and to generate the PWM signal with the shift clock 2 signal. In order to change the fall, based on the shift amount determined by the shift amount control circuit 106, the first selector 213 and the first selector 213 are synchronized with “0” of the start counter 301 in the PCM / PWM converter 300 described later. Switching control of the 2 selector 215, the third selector 216, and the fourth selector 218 is performed.

[0140] Next, the configuration of the PCMZPWM conversion unit 300 of the present embodiment will be described using FIG. FIG. 14 is a block diagram showing a configuration of the PCMZPWM conversion unit 300 in the present embodiment.

[0141] The PCMZPWM conversion unit 300 of the present embodiment operates based on a base clock signal, an up counter 401 that counts up based on a shift clock 2 signal, a down counter 402 that counts down based on a shift clock 1 signal. The start instruction circuit 403 that outputs the start instruction output of the up counter 401 and the down counter 402, the first comparator 404 that compares the PCM value in the input PCM signal with the output of the up counter 401, and the input Comparing PCM value in PCM signal and output of down counter 402 And a RS-FF circuit 406 that outputs a PWM value based on the outputs of the first comparator 404 and the second comparator 405.

[0142] The up counter 401 receives the shift clock 2 signal output from the phase conversion circuit 200 and the start instruction from the start instruction counter circuit 403, and the up counter 401 receives the start instruction. Based on this, the shift clock is counted from “0”, and the count value indicating the counted value is output to the first comparator 404 as data.

[0143] The down counter 402 receives the shift clock 1 signal output from the phase conversion circuit 200 and the start instruction from the start instruction circuit 403. The down counter 402 receives the start instruction. Based on this, the PCM value power counts down for the shift clock 1 signal, and the count value is output to the second comparator 405 as data.

[0144] The base clock signal generated by the clock signal generation unit 103 is input to the start instruction circuit 403 via the phase conversion circuit 200. The start instruction circuit 403 is input to the start instruction circuit 403. Based on the base clock signal, for example, when the number of output bits in the noise shaving circuit 102 is 6 bits, the count from “0” to “127” is repeated, and when “0” is counted, A signal to instruct the start of the down counter 402 is output. When counting “64”, the up counter 401 is instructed to start force counting.

[0145] The first comparator 404 compares the PCM value of the input PCM signal with the count value output from the up counter 401, and when the PCM value and the count value become the same value, the RSM — Outputs a signal to the FF circuit 406 to instruct the PWM signal to fall.

[0146] The second comparator 405 compares the PCM value of the input PCM signal with the count value output from the down counter 402, and when the PCM value and the count value become the same value, the RSM — Outputs a signal to the FF circuit 406 to instruct the rise of the PWM signal.

[0147] The RS-FF circuit 406 has a signal instructing the rising edge of the PWM signal from the second comparator 405 and a signal instructing the falling edge of the PWM signal from the first comparator 404. This RS-FF circuit 406 raises the PWM signal that is output when a signal that instructs rising is input, and also receives a signal that instructs falling. At this time, the PWM signal to be output is lowered.

Next, the PCMZPWM conversion process in the PCMZPWM conversion unit 300 of the present embodiment will be described with reference to FIG. FIG. 15 is a flowchart showing a PCMZPWM conversion process in the PCMZPWM conversion unit 300 of this embodiment.

[0149] In this operation, the PCMZPWM conversion unit 300 is linked to the shift amount control circuit 106, the correction processing unit 105, and the phase conversion circuit 200 based on the base clock signal, and the base clock signal and the shift clock 1 signal. The following processing is performed based on the shift clock 2 signal. The clock signal generation unit 103 generates a base clock signal when the PWM signal generation process is started. Therefore, when the PWM signal generation process is started, the base clock signal, the shift clock 1 signal, and the Shift clock 2 signal is input

[0150] First, generation of a PWM signal is started based on a predetermined instruction such as an operator instruction. When the PCMZPWM conversion unit 300 detects this start (step S501), an up counter 401, a down counter 402, and The start instruction circuit 403 clears a predetermined value and performs initial setting (step S502).

Next, the first comparator 404, the second comparator 405, the up counter 401, and the down counter 402 read the PCM value of the input PCM signal (step S503).

Next, start instruction circuit 403 starts counting based on the base clock signal (step S504), and outputs a signal to start counting to down counter 402.

[0153] Next, the down counter 402 starts counting based on the shift clock 1 signal, and outputs the value of the power count to the second comparator 405 as needed (step S505). When the count is started, the down force counter 402 repeatedly counts from the PCM value read in the process of step S503 to “0” based on the shift clock 1 signal.

Next, the second comparator 405 detects whether the value of the counter output from the down counter 402 is the same as the PCM value read in the process of step S503 (Step S When the value of the down counter 402 is not the same as the PCM value, the down counter 4002 repeats the process of step S506 until the counter value becomes the same as the PCM value.

On the other hand, when the second comparator 405 has the same value as the PCM value of the counter, the second comparator 405 outputs a predetermined instruction to the RS-FF circuit 406 and outputs a “High” PWM signal to the RS-FF circuit 406 as a PWM signal. Output a signal (step S507).

[0156] Next, the start instruction circuit 403 detects whether the value of the start instruction counter is 64 or not.

(Step S508), the process of Step S508 is repeated until it is detected that the counter is “64”.

Next, when starting instruction circuit 403 detects that the counter has reached “64”, it outputs a signal to start counting to up counter 401 (step S509).

[0158] Next, the up counter 401 starts counting based on the shift clock 2 signal, and outputs the value of the power count to the first comparator 404 as needed (step S510). When counting starts, the up counter 401 repeatedly counts from “0” to the PCM value read in step S503 based on the shift clock 2 signal.

[0159] Next, the first comparator 404 detects whether the counter value output from the up counter 401 is the same as the PCM value read in the processing of step S503 (step S511), and outputs from the up counter 401. The process of step S511 is repeated until the counter value thus read becomes the same as the PCM value read in the process of step S503.

On the other hand, when the counter value output from up-counter 401 is the same as the PCM value, first comparator 404 outputs a predetermined instruction to RS-FF circuit 406, and to RS-FF circuit 406. A “Low” signal is output as the PWM signal (step S 512).

[0161] When the processing in step S512 is completed, the operation proceeds to the processing in step S503, and the PCMZPWM conversion processing in the PCMZPWM conversion unit 300 of the present embodiment is performed according to a predetermined instruction such as turning off the power. Repeats the process until is stopped

As described above, the PCMZPWM conversion unit 300 of the present embodiment outputs “High” of the PWM signal based on the shift clock 1 signal and outputs the PWM signal based on the shift clock 2 signal! / "L ow ”is output, so that the phase of each shift clock is changed by the shift amount set by the shift amount control circuit 106 described above, or the shift amount control circuit 106 When the correction value of the correction processing unit 105 set in the above is calculated, a PWM signal in which nonlinear distortion generated when the switching process is performed is output.

[0163] In this embodiment, when the phase of each shift clock signal is directly changed, each shift clock signal whose phase has been changed when the start counter 301 is "0" is used as the shift clock signal. Switch to the signal.

For example, when the PCM value is “2” and a phase difference of “+ Dnsec” is provided, in this embodiment, as shown in FIG. 16, the start instruction counter 403 is “0”. At this time, the shift clock 1 signal and the shift clock 2 signal whose phases are changed are switched, and the PWM signal is started by the switched shift clock 1 signal and is started by the switched shift clock 2 signal. Since it can be lowered, the width of the PWM signal can be reduced from both sides.

FIG. 16 is a timing chart for the nth PCM value when the noise shaper output has 6 bits. The top signal on the timing chart is the base clock signal and Shift clock 1 and shift clock 2 signals.

[0166] As described above, the class D power amplifying apparatus 100 of the present embodiment performs pulse modulation on the PCM signal, amplifies the pulse-modulated PCM signal, and outputs the PCM signal to the speaker SP, as in the first embodiment. A class D power amplifier 100 that receives a PCM signal, and based on the base clock signal, modulates the received PCM signal to generate a pulse width modulation signal, and a PCMZPWM converter 300 A switching amplifier circuit 108 that switches the power supply voltage in accordance with the generated pulse width modulation signal, amplifies the signal level of the pulse width modulation signal, and generates a loud sound signal, and the generated pulse width modulation signal and the loud sound signal. The error signal calculation unit 111 that calculates an error signal indicating an error, and the phase of the clock signal used by the PCMZPWM conversion unit 300 based on the calculated error signal is relative to the received PCM signal. It has a phase conversion circuit 200 for changing the configuration with. [0167] With this configuration, the class D power amplifying apparatus 100 according to the present embodiment receives the phase of the base clock signal used by the PCMZPWM converter 300 based on the calculated error signal! / Change relative to.

[0168] Therefore, the class D power amplifying apparatus 100 of the present embodiment can change the phase of the base clock signal based on the error signal generated by the switching amplifier circuit 108, that is, Since the shift clock 1 signal and the shift clock 2 signal can be generated, the received PCM signal power can also generate the PWM signal by using the shift clock 1 signal and the shift clock 2 signal. The pulse width of the PWM signal amplified by can be varied.

As a result, the class D power amplifying apparatus 100 of the present embodiment has a nonlinear distortion that occurs when the switching process is performed by the switching amplifier circuit 108, that is, the DC power source is turned on by the switching amplifier circuit 108. Non-linear distortion caused by switching off can be accurately prevented, and a dedicated circuit with high accuracy for making the pulse width of the PWM signal variable can be reduced in size.

Claims

The scope of the claims

[1] A class D power amplifying apparatus that pulse-modulates a sound signal, amplifies the pulse-modulated sound signal, and outputs the amplified sound signal to a speaker.

Receiving means for receiving a sound signal which is a digital signal;

First generation means for pulse-modulating the received sound signal based on the clock signal to generate a pulse width modulation signal; and

Second generating means for switching a power supply voltage according to the generated pulse width modulation signal and amplifying the signal level of the pulse width modulation signal to generate a loudspeaker signal;

Detecting means for detecting an error signal indicating an error between the generated pulse width modulation signal and the loud sound signal;

Phase change means for changing the phase of the clock signal used by the first generation means relative to the received sound signal based on the detected error signal;

A class D power amplifying device characterized by comprising:

[2] In the class D power amplifying device according to claim 1,

Class D power amplification characterized in that the phase change means relatively changes the phase of the clock signal used by the first generation means for each predetermined interval when generating the pulse width modulation signal. apparatus.

[3] In the class D power amplifying device according to claim 1 or 2,

The phase changing means changes the phase of the clock signal directly based on the detected error signal, or changes the timing at the time of reception of the sound signal, A class D power amplifying apparatus, wherein the phase of the clock signal is changed relative to the received sound signal.

[4] In the class D power amplifying device according to any one of claims 1 to 3,

When the sound signal is a PCM (Pulse Code Modulation) signal,

The phase changing means relatively changes the phase of the clock signal in association with a PCM value that is the value of the received PCM signal, and the first generating means has a PCM corresponding to the PCM value. Based on a clock signal that changes relatively from signal to signal, A class D power amplifying apparatus characterized by pulse-modulating the PCM signal to generate a pulse width modulation signal.

The class D power amplifying device according to claim 4,

When the phase change means relatively changes the phase of a clock signal used for modulation of a PCM signal having an arbitrary PCM value, it is received before the detected error signal and the signal having the arbitrary PCM value. Relative to the phase of the clock signal used when performing pulse modulation of the PCM signal having the arbitrary PCM value based on the phase change of the clock signal used when modulating the modulated PCM signal. Class D power amplification device characterized by changing to