JP2004172715A - Class-d amplifier - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly efficient class-D amplifier in which distortion in an output signal due to fluctuations in power supply voltage supplied to a power switch circuit is substantially reduced as compared to a conventional amplifier and a distortionless maximum output level is not so reduced, even if the power supply voltage varies in a relatively wide range. <P>SOLUTION: In the class D amplifier including a switching means 3 for switching an DC power supply voltage, on the basis of an input signal subjected to pulse width modulation, and a feedback correcting means 2 for correcting the pulse width of the input signal supplied to the switching means, according to the amplitude of a feedback signal generated from an output of the switching means, an operation means 11 is provided for adjusting the amplitude of the feedback signal to be supplied to the means 2, according to a value of the power supply voltage. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a class D amplifier used for power amplification of an audio signal and the like.
[0002]
[Prior art]
2. Description of the Related Art Class D amplifiers have been conventionally used to perform power amplification of audio signals with high efficiency and low loss, thereby enabling downsizing of devices. Further, in the class D amplifier, a digital audio signal is directly converted into a pulse width modulation (PWM) signal and guided to a power switch circuit, and a re-quantizing means used for performing the PWM conversion is used. A configuration for reducing a rounding error by using delta-sigma modulation is known (for example, see Japanese Patent Application Laid-Open Nos. 11-261347 and 2001-29240).
[0003]
[Patent Document 1]
JP-A-11-261347 [Patent Document 2]
Japanese Patent Application Laid-Open No. 2001-29240
[Problems to be solved by the invention]
The above-mentioned known configuration makes it possible to obtain an accurate pulse width modulation signal. By reflecting the pulse width modulation signal on the output of the power switch circuit with high accuracy, a high-quality audio signal can be obtained as an amplifier output. However, when the power supply voltage supplied to the power switch circuit fluctuates, there is a problem that the output signal is distorted. If a constant voltage is always supplied to the power switch circuit via the constant voltage circuit, it is possible to reduce the distortion of the output signal, but the power consumed by the power switch circuit is relatively large. In this case, another problem arises in that the power amplification of the audio signal cannot be performed with high efficiency and low loss.
[0005]
The present invention has been made in view of the above problem, and distortion of an output signal due to fluctuation of a power supply voltage supplied to a power switch circuit is significantly reduced as compared with the related art, and the power supply voltage can be reduced in a relatively wide range. It is an object of the present invention to provide a highly efficient class D amplifier in which the distortion-free maximum output level does not decrease so much even if it changes.
[0006]
[Means for Solving the Problems]
The object is to switch a DC power supply voltage in accordance with a pulse width modulated input signal, and to change a pulse width of an input signal supplied to the switch to an amplitude of a feedback signal generated from an output of the switch. And a feedback correction means for correcting the amplitude of the feedback signal supplied to the feedback correction means in accordance with the value of the power supply voltage. Achieved by a class D amplifier.
[0007]
The above object is also achieved by a switch means for switching a DC power supply voltage in accordance with a pulse width modulated input signal, and a pulse width of an input signal supplied to the switch means, the amplitude of a feedback signal generated from an output of the switch means. A feedback correction means for correcting the input signal according to the first integration means, based on the feedback signal and the DC component of the power supply voltage. A second integrating means for integrating a difference from the generated reference voltage; and a comparing means for comparing outputs of the first and second integrating means. An output of the comparing means is supplied to the switching means. This is achieved by a class D amplifier.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a class D amplifier according to Embodiment 1 of the present invention. This class D amplifier includes a pulse modulation means 1, a correction circuit 2, a power switch circuit 3, a feedback circuit 4, a low-pass filter 5, a speaker 6, a first constant voltage circuit 7, a second constant voltage circuit 8, a DC output It includes a reference signal generation unit 10 and a calculation unit 11. The class D amplifier is supplied with a power supply voltage Vcc from an external power supply via a power supply terminal 9.
[0009]
The pulse modulating means 1 generates a binary pulse signal (hereinafter, referred to as a PWM signal) pulse-width-modulated with an audio signal, and the power switch circuit 3 converts the value of the binary pulse signal corrected by the correction circuit 2 into a value. In response, a switching operation for connecting a power supply (or ground) to an output is performed, and power can be supplied to a load (speaker 6) connected to an amplifier output.
[0010]
The low-pass filter 5 removes high-frequency components from the output of the power switch circuit 3, demodulates an audio signal, and supplies the demodulated audio signal to the speaker 6 to reproduce audio. The feedback circuit 4 attenuates the output of the power switch circuit 3 to an appropriate level and provides the output to the correction circuit 2.
[0011]
The pulse modulating means 1 includes a delta-sigma modulator 101 for performing delta-sigma modulation on a digitized audio signal and a PWM converter 102 for converting a delta-sigma-modulated audio signal into a PWM signal.
[0012]
The DC output reference signal generator 10 includes a low-pass filter 201 and a level adjuster 202, and the calculator 11 includes a subtractor 203 and an adder 204.
[0013]
The first constant voltage circuit 7 is mainly composed of a logic circuit, stabilizes a power supply voltage supplied from an external power supply via a terminal 9 to a constant value, and supplies the same to the pulse modulation means 1. The second constant voltage circuit 8 is also mainly composed of a logic circuit, stabilizes the power supply voltage supplied from the external power supply via the terminal 9 to a constant value, and supplies the same to the correction circuit 2.
[0014]
In FIG. 1, the power switch circuit 3 is directly connected to the terminal 9, but in practice, it is generally connected via a low-pass filter composed of an inductor and a capacitor. However, this is for removing high-frequency noise included in the power supply voltage and, unlike a constant voltage circuit, does not have the effect of suppressing low-frequency voltage fluctuation in the audio frequency band. As described above, if a constant voltage circuit is used to stabilize the voltage supplied to the power switch circuit 3 requiring a relatively large amount of power, there is a disadvantage that a large power loss occurs in this portion. This is also because the cost for mounting this circuit increases. In the present embodiment, a correction circuit 2 that performs feedback correction is used as an alternative to the constant voltage circuit.
[0015]
The internal configuration of the correction circuit 2 is shown in the block diagram of FIG. The correction circuit 2 includes a first subtractor 20, a first integrator 21, a gain adjuster 22, a second subtractor 23, a second integrator 24, and a comparator 25. The first subtractor 20, the first integrator 21, and the gain adjuster 22 constitute an integrating means having means for negatively feeding back the output to the input. The integrating means integrates the pulse modulated signal from the pulse modulating means 1 to emphasize its low-frequency component, and moderately suppresses the low-frequency gain by negative feedback through the gain adjuster 22, so that the integrated output becomes the operation of the circuit. An operation for preventing the range from being exceeded is performed.
[0016]
Further, the second subtractor 23 and the second integrator 24 perform integration by subtracting the output of the gain adjuster 22 from the feedback signal output from the calculating means 11, and provide a feedback signal, that is, a power switch circuit. Has the effect of enhancing the low-frequency components included in the output of. The comparator 25 compares the outputs of the first integrator 21 and the second integrator 24, and outputs the difference to the power switch circuit 3 as a binary pulse signal (compensated PWM signal).
[0017]
FIG. 3 shows a signal waveform of each part of the correction circuit 2. In FIG. 3, reference numeral 30 denotes a PWM signal waveform output from the pulse modulation means 1. Assuming that the amplitude of the PWM signal is Vsig, and the first integrator 21 operates around Vsig / 2, the output waveform of the first integrator 21 is as shown in FIG. Further, assuming that the gain of the feedback circuit 4 is 1 / K and the output voltage of the power switch circuit 3 is Vsw, the amplitude of the feedback signal Vfb is Vsw / K if there is no correction for the output voltage Vsw of the calculating means 11. Become. Assuming that the amplitude Vsw / K is substantially equal to Vsig and the second integrator 24 operates at about Vsig / 2, the output waveform of the second integrator 24 is as shown in FIG.
[0018]
Therefore, the output waveform of the comparator 25 is as shown in 33. Further, the feedback signal Vfb has a waveform as shown at 34 whose output 33 of the comparator 25 is mainly delayed by the delay δ in the power switch circuit 3 and whose amplitude is attenuated by the feedback circuit 4 by a substantially constant amount.
[0019]
As described above, a compensated PWM signal output is generated based on a comparison between the PWM signal output from the pulse modulation unit 1 and the feedback signal output from the power switch circuit 3 and input through the feedback system. A series of feedback operation is performed in which the signal returns to the feedback signal via the feedback system.
[0020]
The waveform shown in FIG. 3 is a case where the PWM signal and the feedback signal have substantially the same amplitude, and the power switch circuit 3 has only a time delay δ and no waveform distortion occurs. The signal 33 has a similar waveform. However, when the power supply voltage supplied to the power switch circuit 3 becomes larger than the specified value and the amplitude of the feedback signal becomes larger than the amplitude of the PWM signal, the level of the output of the second integrator 24 increases. Then, the waveform 32 moves upward. In this case, the period in which the waveform 31 exceeds the waveform 32, that is, the period in which the output of the comparator 25 is "H" is shortened. At this time, if the gain of the second integrator 24 for the low-frequency component is sufficiently large, The output of the comparator 25, that is, the pulse width of the compensated PWM signal, decreases until the low-frequency component of the feedback signal becomes substantially equal to the low-frequency component of the PWM signal, and the power supply voltage supplied to the power switch circuit 3 increases. Will be compensated for.
[0021]
Conversely, when the power supply voltage supplied to the power switch circuit 3 becomes smaller than the specified value and the amplitude of the feedback signal becomes smaller than the amplitude of the PWM signal, the output level of the second integrator 24 decreases, and FIG. Then, the waveform 32 moves downward. In this case, the period in which the waveform 31 exceeds the waveform 32, that is, the period in which the output of the comparator 25 is "H" becomes longer. At this time, if the gain of the second integrator 24 for the low-frequency component is sufficiently large, The output of the comparator 25, that is, the pulse width of the compensated PWM signal increases until the low-frequency component of the feedback signal becomes substantially equal to the low-frequency component of the PWM signal. Compensation will be provided.
[0022]
As described above, the correction circuit 2 performs an operation of transmitting the PWM signal to the output while performing the correction (pulse width correction) based on the difference between the feedback signal and the low frequency component to the PWM signal.
[0023]
FIG. 4 shows an example of a specific circuit configuration of the correction circuit 2. In this example, the correction circuit 2 includes resistors 50 to 53, capacitors 54 and 55, operational amplifiers 56 and 57, and a comparator 58. In FIG. 4, a PWM signal is applied to the inverting input of the operational amplifier 56 as a virtual ground through a resistor 50, and the output of the operational amplifier 56 is further applied to the inverting input of the operational amplifier 56. Operation is realized. The operation of the gain adjuster 22 is realized by adjusting the ratio between the resistors 50 and 51. In addition, the operation of the first integrating means 21 is realized by accumulating electric charges in the capacitor 54 connected to the inverting input and the output of the operational amplifier 56.
[0024]
Similarly, the output of the operational amplifier 56 is applied to the inverting input of the operational amplifier 57 as a virtual ground through the resistor 52, and the feedback signal is further applied to the inverting input of the operational amplifier 57 through the resistor 53. Is realized. The operation of the gain adjuster 22 is realized by adjusting the ratio of the resistors 53 and 52. In addition, the operation of the second integration means 24 is realized by accumulating electric charge in the capacitor 55 connected to the inverting input and output of the operational amplifier 57.
[0025]
The comparator 58 in FIG. 4 corresponds to the comparator 25 in FIG. 2. However, the positive and negative signs of the outputs of the operational amplifiers 56 and 57 are the same as those of the first integrator 21 and the second integrator 24. Because of the opposite relationship, the output of the operational amplifier 56 is given to the inverting input of the comparator 58, and the output of the operational amplifier 57 is given to the non-inverting input of the comparator 58.
[0026]
As described above, both the PWM signal input from the pulse modulation means 1 to the correction circuit 2 and the PWM signal output from the power switch circuit 3 and after being appropriately attenuated and input to the correction circuit 2 as a feedback signal are both DC components. , And the correction circuit 2 performs the correction including the DC component. The reason is that although the DC component is included, the PWM signal is basically a binary signal, and the voltage value to be taken in the two states “H” and “L” is predetermined in each part of the circuit. This is because, for example, conventional means in an analog circuit such as blocking a DC component by a capacitor and separately setting only a DC operating point cannot be used, and the correction circuit 2 includes an integrator having a high DC gain inside. This is because it is practical to stabilize the operating point of the circuit by DC feedback.
[0027]
Even if the feedback correction is performed including the DC potential as described above, no particular problem occurs when the fluctuation of the power supply voltage is small. However, a problem arises when the power supply voltage greatly changes. For example, equipment mounted on an automobile is required to operate normally even if the power supply voltage changes in a range of 11 V to 16 V. Therefore, when the design center is 13.2 V, the power supply voltage is almost +/- It is necessary to guarantee that the operation can be performed without any problem even if the fluctuation is in the range of 20%. Under the above conditions, when the above-described correction is performed to suppress the distortion of the output signal, the problem that the maximum distortion-free audio signal output is rapidly reduced particularly when the power supply voltage is reduced as described below. Occurs.
[0028]
For example, in the feedback system including the correction circuit 2, when the power supply voltage is 13.2 V, which is the design center, when the PWM signal from the pulse modulation means 1 is not modulated, in other words, when the pulse duty ratio is 50% It is assumed that the gain is adjusted so that the DC potential of the amplifier output becomes 6.6 V, which is の of the power supply voltage. In this case, even if the power supply voltage changes over the range of 11 V to 16 V, the amplifier output DC potential when the PWM signal is not modulated (hereinafter, simply referred to as the unmodulated amplifier output potential) is approximately 6 due to feedback correction. .6V. In this adjustment, when the power supply voltage is 13.2 V, which is the center of design, and the pulse duty ratio of the PWM signal output from the pulse modulation means 1 is about 80%, the DC output potential of the amplifier reaches 11 V. However, even if the power supply voltage drops from 13.2 V to 11 V, the amplifier output DC potential reaches 11 V when the pulse duty ratio of the PWM signal is about 80% due to feedback correction. That is, when the power supply voltage is reduced to 11 V, it means that the amplifier output is saturated when the pulse duty ratio of the PWM signal exceeds about 80%.
[0029]
FIG. 5 illustrates this situation with signal waveforms. Reference numeral 40 denotes an output signal in a distortion-free maximum output state when the power supply voltage drops to 11 V with the amplifier output potential set to 6.6 V during no modulation. 2 shows a waveform (sine wave). The level of the distortion-free maximum output signal is (11−6.6) × 2 = 8.8 Vpp. Here, if the amplifier output potential at the time of non-modulation is shifted to 5.5 V which is の of the power supply voltage (11 V) at this time, the waveform (sine wave) of the output signal in the distortion-free maximum output state is 41. It will be shown. In this case, the level of the distortion-free maximum output signal increases to 5.5 × 2 = 11 Vpp.
[0030]
As described above, when the power supply voltage changes in a relatively wide range, in order to maximize the distortion-free maximum output, the correspondence between the PWM signal pulse duty ratio and the amplifier output DC potential is determined according to the power supply voltage at each time. It is desirable to change, specifically, to change the setting of the feedback system so that the output potential of the amplifier at the time of non-modulation always becomes 1/2 of the power supply voltage. Therefore, the present embodiment includes a DC output reference signal generation unit 10 and a calculation unit 11. Hereinafter, these means will be described.
[0031]
The DC output reference signal generation means 10 generates a reference signal used to maintain the amplifier output potential at the time of non-modulation at a target value. As described above, the target value of the non-modulated amplifier output potential is 1/2 of the current value of the power supply voltage Vcc supplied to the power switch circuit 3. For this reason, in the present embodiment, the DC output reference signal generation means 10 controls the input voltage, that is, the power supply voltage Vcc to Vcc by the internal level adjuster 202 having a gain of 1 / 2K with respect to the gain 1 / K of the feedback circuit 4. / (2 · K). Since the AC fluctuation component included in the power supply voltage is removed by the low-pass filter 201 of the DC output reference signal generation means 10, the generated reference signal is not affected by the AC fluctuation.
[0032]
The calculating means 11 subtracts the DC output reference signal output from the DC output reference signal generating means 10 from the output of the feedback circuit 4 by the subtractor 203, and further adds the fixed potential Vsig / 2 by the adder 12. Here, assuming that the DC component included in the output of the power switch circuit 3 is Vsw, the output Vfb of the calculating unit 11 is
Vfb = Vsw / K−Vcc / (2 · K) + Vsig / 2 (1)
It can be expressed as.
[0033]
Here, when the PWM signal is not modulated, the correction circuit 2 operates so that the low-frequency component included in the feedback signal, that is, Vfb, becomes equal to the low-frequency component Vsig / 2 included in the PWM signal. Therefore, when the relationship of Vfb = Vsig / 2 is applied to the equation (1), Vsw = Vcc / 2. Since the low-pass filter 5 generates an amplifier output from Vsw, it is clear that the above-described configuration provides a desired operation.
[0034]
In the present embodiment, the subtraction and addition of the DC potential by the arithmetic means 11 are performed on the signal passed through the feedback circuit 4, but this is directly performed on the output of the power switch circuit 3 and the result is fed back. It is also possible to adopt a configuration in which attenuation is performed through the circuit 4. In this case, it goes without saying that the signal to be subtracted should be Vcc / 2 and the signal to be added should be K · Vsig / 2. In addition, the order of the subtraction and the addition may be changed.
[0035]
Embodiment 2 FIG.
FIG. 6 is a block diagram showing a configuration of a class D amplifier according to the second embodiment of the present invention. The second embodiment differs from the first embodiment in that the second embodiment does not include the calculating means 11 and uses a correction circuit 13 instead of the correction circuit 2.
[0036]
The correction circuit 13 basically performs the same operation as the correction circuit 2 in the first embodiment, but has a function of receiving an output from the DC output reference signal generating means 10 and controlling the amplifier output potential at the time of no modulation. Is included. FIG. 7 shows a circuit configuration of the correction circuit 13.
[0037]
As shown in the figure, in the correction circuit 13, the output of the DC output reference signal generating means is applied through a resistor 60 to a non-inverting input of a differential input type operational amplifier 57 constituting a second integrator. This non-inverting input is different from the configuration of the correction circuit 2 in that the non-inverting input is further connected to a fixed potential point for applying the DC potential Vc1 through the resistor 59.
[0038]
When an integrator having a very large DC gain is inserted in the signal feedback path as in the illustrated circuit configuration, the DC operating point determined by the feedback operation is substantially determined by the operation of the integrator. Specifically, the second integrator formed by the operational amplifier 57 has the gain of the operational amplifier 57 in a substantially non-feedback state with respect to the DC signal. No matter how the potential of the DC output from amplifier 56 changes, the resulting difference between the differential inputs will be small. In other words, the DC operating point of the related part is determined so that this condition is satisfied.
[0039]
The impedance of the inverting input and the non-inverting input of the operational amplifier 57 is made sufficiently larger than the resistance values of the resistors 52, 53, 59 and 60 connected to the inverting input and the non-inverting input. And 60, there is no practical difficulty in sufficiently lowering the output impedance of each element that provides a signal.
[0040]
Here, for convenience of explanation, the resistors 52 and 59 have the same resistance value R3, and the resistors 53 and 60 have the same resistance value R4. Assuming that the output from the DC output reference signal generating means 10 is Vcc / (2 · K) as in the first embodiment, the DC potential Vp of the non-inverting input of the operational amplifier 57 is
Vp = (Vc1 · R4 + Vcc · R3 / (2 · K)) / (R3 + R4) (2)
It becomes.
[0041]
Further, when the DC potential of the inverting input of the operational amplifier 57 is Vn, the impedance of the capacitor 55 is infinite for the DC component, so that the influence can be neglected.
Vn = (Vt0 · R4 + Vfb · R3) / (R3 + R4) (3)
It becomes. Vt0 is a DC potential output from the operational amplifier 56.
[0042]
Assuming that the non-modulated DC potential of the input PWM signal is Vsig / 2, and the value of Vt0 at this time is Vt00,
Vt00 = Vc0 · (R1 + R2) / R1−Vsig · R2 / (2 · R1)
It becomes. Here, the resistance of the resistor 50 is R1, and the resistance of the resistor 51 is R2.
[0043]
As shown in this equation, the value of Vt00 is a fixed value determined by the DC potential of the PWM signal, the fixed potential Vc0 applied to the non-inverting input of the operational amplifier 56, and the resistance values of the resistors 50 and 51. Therefore, if the fixed potential Vc1 is set to be equal to Vt00, the first term on the right side of the equations (2) and (3) when the PWM signal is not modulated becomes equal.
[0044]
As described above, when the correction circuit 13 is operating normally, Vp and Vn expressed by the equations (2) and (3) become substantially equal. In this case, the right side of the equations (2) and (3) The second term is also equal. That is, Vfb = Vcc / (2 · K). This indicates that the feedback operation is performed so that the DC potential of the feedback signal becomes equal to the DC output reference signal when the PWM signal is not modulated.
[0045]
In addition, when the DC component of the power switch circuit 3 is Vsw and Vfb = Vsw / K, a feedback operation is performed so that Vsw becomes １ ／ of the power supply voltage Vcc, that is, a desired operation is performed. It is shown that.
[0046]
As a setting condition, it is also possible to set R1 to R4 to all the same resistance value R and set the fixed potential Vc0 to Vsig / 2. In this case, Vt00 = Vsig / 2, and the fixed potential Vc1 is set to the same value. Since Vsig / 2 can be set, the circuit configuration is simplified.
[0047]
In the circuit configuration described above, the resistors 52 and 59 have the same resistance value, and the resistors 53 and 60 have the same resistance value. However, the same effect can be obtained even if they have different configurations.
[0048]
Further, although the configuration is slightly complicated, instead of providing the output of the DC output reference signal generating means 10 to the non-inverting input of the differential amplifier 57 constituting the second integrator, means for inverting this signal, that is, It is also possible to provide a means for reversing the direction of the increase / decrease of the DC output reference signal with respect to the increase / decrease of the power supply voltage, and to provide the inverted signal to the inverting input of the differential amplifier 57 via a resistor. In this case, since the potential of the non-inverting input of the differential amplifier is fixed, it is easy to realize this amplifier.
[0049]
Although the class D amplifier described above has a single-ended output stage, the present invention is not limited thereto, and includes two output stages that output audio signals that are 180 degrees out of phase with each other. It is also applicable to a so-called BTL configuration. In other words, by additionally applying the correction circuit having the above-described configuration to each output stage having the BTL configuration, the above-described distortion improving effect can be similarly obtained.
[0050]
【The invention's effect】
According to the present invention, the distortion of the output signal due to the fluctuation of the power supply voltage supplied to the power switch circuit is greatly reduced as compared with the related art, and the distortion-free maximum is obtained even when the power supply voltage changes in a relatively wide range. A high-efficiency class D amplifier is provided that does not significantly reduce the output level.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a class D amplifier according to Embodiment 1 of the present invention.
FIG. 2 is a block diagram showing a configuration of a correction circuit of the class D amplifier according to the first embodiment.
FIG. 3 is a diagram showing signal waveforms at various parts of the class D amplifier according to the first embodiment.
FIG. 4 is a circuit diagram of a correction circuit of the class D amplifier according to the first embodiment.
FIG. 5 is a diagram showing an output waveform of the class D amplifier according to the first embodiment.
FIG. 6 is a block diagram showing a configuration of a class D amplifier according to Embodiment 2 of the present invention.
FIG. 7 is a circuit diagram of a correction circuit of the class D amplifier according to the second embodiment.
[Explanation of symbols]
Reference Signs List 1 pulse modulating means, 2 correction circuit, 3 power switch circuit, 4 feedback circuit, 5 low-pass filter, 6 speaker, 7 first constant voltage circuit, 8 second constant voltage circuit, 9 power supply terminal, 10 DC output reference Signal generating means, 11 arithmetic means, 13 correction circuit, 20 first subtractor, 21 first integrator, 22 gain adjuster, 23 second subtractor, 24 second integrator, 25 comparator.

Claims (5)

Switch means for switching a DC power supply voltage in accordance with a pulse width modulated input signal; and a pulse width of an input signal supplied to the switch means is corrected in accordance with an amplitude of a feedback signal generated from an output of the switch means. Class D amplifier including feedback correction means,
A class D amplifier, comprising: arithmetic means for adjusting the amplitude of the feedback signal supplied to the feedback correction means according to the value of the power supply voltage. The arithmetic means includes subtraction means for subtracting a reference voltage generated based on the DC component of the power supply voltage from the feedback signal, and addition means for adding a fixed DC voltage to an output of the subtraction means, 2. The class D amplifier according to claim 1, wherein the output of the class D amplifier is supplied to the feedback correction means. Switch means for switching a DC power supply voltage in accordance with a pulse width modulated input signal; and a pulse width of an input signal supplied to the switch means is corrected in accordance with an amplitude of a feedback signal generated from an output of the switch means. Class D amplifier including feedback correction means,
First integration means for integrating the input signal, feedback integration means for integrating a difference between the feedback signal and a reference voltage generated based on a DC component of the power supply voltage, A class D amplifier, comprising: comparing means for comparing outputs of the first and second integrating means, wherein an output of the comparing means is supplied to the switching means. The second integrator includes the feedback signal applied to an inverting input via a first resistor, and the reference voltage and the fixed voltage being non-inverting via a second and third resistor, respectively. The class D amplifier of claim 3, including a differential amplifier applied to the input. The second integrating means applies the feedback signal and the inverted reference voltage to an inverting input via a first resistor and a second resistor, respectively, and applies the fixed voltage to a third resistor. 4. The class D amplifier of claim 3, including a differential amplifier applied to the non-inverting input via the input.

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