JP4169124B2 - Class D amplifier - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a class D amplifier used for power amplification of an audio signal.
[0002]
[Prior art]
A class D amplifier has been conventionally used in order to perform power amplification of an audio signal with high efficiency and low loss, thereby enabling downsizing of the device. Further, in the class D amplifier, a configuration in which a digitized audio signal is directly converted into a pulse width modulation (PWM) signal and led to a power switch circuit, and also by a requantization means used for performing this PWM conversion A configuration for reducing the rounding error by using delta-sigma modulation is known (see, for example, Japanese Patent Laid-Open Nos. 11-261347 and 2001-29240).
[0003]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-261347 [Patent Document 2]
Japanese Patent Laid-Open No. 2001-29240
[Problems to be solved by the invention]
With the above known configuration, it is possible to obtain a pulse width modulation signal with high accuracy, and it is possible to obtain a high-quality audio signal as an amplifier output by reflecting it with high accuracy in the output of the power switch circuit. However, when the power supply voltage supplied to the power switch circuit varies, there is a problem that distortion occurs in the output signal. Although it is possible to reduce the distortion of the output signal by always supplying a constant voltage to the power switch circuit via the constant voltage circuit, the power consumed by the power switch circuit is relatively large. As a result, the power loss of the audio signal becomes large, which causes another problem that the power amplification of the audio signal cannot be performed with high efficiency and low loss.
[0005]
The present invention has been made in view of the above problems, and distortion of an output signal caused by fluctuation of a power supply voltage supplied to a power switch circuit is greatly reduced as compared with the conventional one, and the power supply voltage is within a relatively wide range. An object of the present invention is to provide a high-efficiency class D amplifier whose distortion-free maximum output level does not decrease so much even if it changes.
[0006]
[Means for Solving the Problems]
The object is to switch the DC power supply voltage according to a pulse width modulated input signal, and to change the pulse width of the input signal supplied to the switch means to the amplitude of the feedback signal generated from the output of the switch means. depending a class D amplifier comprising a feedback correction means for correcting, subtracting means for subtracting the reference voltage generated on the basis of the feedback signal to the DC component of the power supply voltage, a fixed DC voltage output of the subtraction means It is achieved by a class D amplifier, characterized in that it comprises an adding means for adding and an arithmetic means for supplying the output of the adding means to the feedback correction means .
[0007]
The above object is also achieved by switching means for switching a DC power supply voltage in accordance with a pulse width modulated input signal, and the pulse width of the input signal supplied to the switching means, the amplitude of the feedback signal generated from the output of the switching means. And a feedback correction unit that corrects the input signal according to the first correction unit that integrates the input signal, the feedback signal, and a DC component of the power supply voltage. A second integrating means for integrating the difference from the generated reference voltage; and a comparing means for comparing the outputs of the first and second integrating means, and the output of the comparing means is supplied to the switching means. This is achieved by a class D amplifier.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
The block diagram of FIG. 1 shows the configuration of a class D amplifier according to Embodiment 1 of the present invention. This class D amplifier includes a pulse modulation means 1, a correction circuit 2, a power switch circuit 3, a feedback circuit 4, a low-pass filter 5, a speaker 6, a first constant voltage circuit 7, a second constant voltage circuit 8, a DC output. Reference signal generation means 10 and calculation means 11 are included. The class D amplifier is supplied with a power supply voltage Vcc from an external power supply via a power supply terminal 9.
[0009]
The pulse modulation means 1 generates a binary pulse signal (hereinafter referred to as a PWM signal) that is pulse-width modulated with an audio signal, and the power switch circuit 3 sets the value of the binary pulse signal corrected by the correction circuit 2. Accordingly, a switching operation for connecting the power source (or ground) and the output is performed, and power supply to the load (speaker 6) connected to the amplifier output is enabled.
[0010]
The low-pass filter 5 demodulates the audio signal by removing a high frequency component from the output of the power switch circuit 3 and applies it to the speaker 6 to reproduce the audio. The feedback circuit 4 attenuates the output of the power switch circuit 3 to an appropriate level and gives it to the correction circuit 2.
[0011]
The pulse modulation means 1 includes a delta-sigma modulator 101 that delta-sigma-modulates a digitized audio signal and a PWM converter 102 that converts the delta-sigma-modulated audio signal into a PWM signal.
[0012]
The DC output reference signal generation means 10 includes a low pass filter 201 and a level adjuster 202, and the calculation means 11 includes a subtractor 203 and an adder 204.
[0013]
The first constant voltage circuit 7 is mainly composed of a logic circuit, stabilizes the power supply voltage supplied from the external power supply via the terminal 9 to a constant value, and supplies it to the pulse modulation means 1. The second constant voltage circuit 8 is also mainly composed of a logic circuit, which stabilizes the power supply voltage supplied from the external power supply via the terminal 9 to a constant value and supplies it to the correction circuit 2.
[0014]
In FIG. 1, the power switch circuit 3 is directly connected to the terminal 9, but in practice it is generally connected via a low-pass filter composed of an inductor and a capacitor. However, this is for removing high-frequency noise contained in the power supply voltage, and unlike the constant voltage circuit, it does not have the effect of suppressing low frequency voltage fluctuations in the audio frequency band. As described above, when a constant voltage circuit is used to stabilize the voltage supplied to the power switch circuit 3 that requires relatively large power, there is a disadvantage that a large power loss occurs in this portion. This is because the cost for mounting this circuit also increases. In the present embodiment, a correction circuit 2 that performs feedback correction is used as an alternative to the constant voltage circuit.
[0015]
The internal configuration of the correction circuit 2 is shown in the block diagram of FIG. The correction circuit 2 includes a first subtracter 20, a first integrator 21, a gain adjuster 22, a second subtracter 23, a second integrator 24, and a comparator 25. The first subtractor 20, the first integrator 21 and the gain adjuster 22 constitute an integrating means including means for negatively feeding back the output to the input. The integrating means integrates the pulse modulated signal from the pulse modulating means 1 to emphasize the low frequency component and moderately suppress the low frequency gain by negative feedback through the gain adjuster 22 so that the integrated output operates as a circuit. An operation that prevents the range from being exceeded is performed.
[0016]
The second subtractor 23 and the second integrator 24 perform integration by subtracting the output of the gain adjuster 22 from the feedback signal output from the computing means 11, and the feedback signal, that is, the power switch circuit. It has the effect of emphasizing the low-frequency component included in the output of. The comparator 25 compares the outputs of the first integrator 21 and the second integrator 24 and outputs the difference to the power switch circuit 3 as a binary pulse signal (compensated PWM signal).
[0017]
FIG. 3 shows signal waveforms at various parts of the correction circuit 2. In FIG. 3, reference numeral 30 denotes a PWM signal waveform output from the pulse modulation means 1. The amplitude of the PWM signal is Vsig, and if the first integrator 21 operates around Vsig / 2, the output waveform of the first integrator 21 is as shown at 31. If the gain of the feedback circuit 4 is 1 / K and the output voltage of the power switch circuit 3 is Vsw, the amplitude of the feedback signal Vfb is Vsw / K when there is no correction to the output voltage Vsw of the computing means 11. Become. If the amplitude Vsw / K is substantially equal to Vsig and the second integrator 24 operates about Vsig / 2, the output waveform of the second integrator 24 is as shown in 32.
[0018]
For this reason, the output waveform of the comparator 25 is as shown at 33. The feedback signal Vfb is delayed from the output 33 of the comparator 25 mainly by the delay δ in the power switch circuit 3 and has a waveform as shown by 34 whose amplitude is attenuated by a substantially constant amount by the feedback circuit 4.
[0019]
Thus, a compensated PWM signal output is generated based on a comparison between the PWM signal output from the pulse modulation means 1 and the feedback signal output from the power switch circuit 3 and input through the feedback system. A series of feedback operations are performed in which a feedback signal is obtained again via a feedback system.
[0020]
Note that the waveforms shown in FIG. 3 are those in which the amplitudes of the PWM signal and the feedback signal are substantially equal, and the power switch circuit 3 has only a time delay δ and no waveform distortion occurs. The waveform is similar to that of the signal 33. However, when the power supply voltage supplied to the power switch circuit 3 becomes larger than the specified value and the amplitude of the feedback signal becomes larger than the amplitude of the PWM signal accordingly, the output level of the second integrator 24 increases, and FIG. Then, the waveform 32 moves upward. In this case, the period in which the waveform 31 exceeds the waveform 32, that is, the period in which the output of the comparator 25 is “H” is shortened. At this time, if the gain for the low frequency component of the second integrator 24 is sufficiently large, The output of the comparator 25, that is, the pulse width of the compensation PWM signal, decreases until the low frequency component of the feedback signal becomes substantially equal to the low frequency component of the PWM signal, and the power supply voltage supplied to the power switch circuit 3 increases. Will be compensated for.
[0021]
Conversely, when the power supply voltage supplied to the power switch circuit 3 becomes smaller than the specified value and the amplitude of the feedback signal becomes smaller than the amplitude of the PWM signal, the output level of the second integrator 24 decreases, and FIG. Then, the waveform 32 moves downward. In this case, a period in which the waveform 31 exceeds the waveform 32, that is, a period in which the output of the comparator 25 is “H” becomes long. At this time, if the gain for the low frequency component of the second integrator 24 is sufficiently large, The output of the comparator 25, that is, the pulse width of the compensation PWM signal increases until the low frequency component of the feedback signal becomes substantially equal to the low frequency component of the PWM signal, and the power supply voltage supplied to the power switch circuit 3 is reduced. Compensation will be performed.
[0022]
As described above, the correction circuit 2 performs an operation of transmitting the PWM signal to the output while applying correction (pulse width correction) based on the difference of the low frequency component from the feedback signal to the PWM signal.
[0023]
FIG. 4 shows an example of a specific circuit configuration of the correction circuit 2. In this example, the correction circuit 2 includes resistors 50 to 53, capacitors 54 and 55, operational amplifiers 56 and 57, and a comparator 58. In FIG. 4, a PWM signal is applied to the inverting input of the operational amplifier 56 as a virtual ground through a resistor 50, and an output of the operational amplifier 56 is further applied through a resistor 51, whereby the first subtracter 20 is applied. Is realized. The operation of the gain adjuster 22 is realized by adjusting the ratio of the resistors 50 and 51. Further, the operation of the first integrating means 21 is realized by accumulating charges in the capacitor 54 connected to the inverting input and output of the operational amplifier 56.
[0024]
Similarly, the output of the operational amplifier 56 is applied to the inverting input of the operational amplifier 57 as a virtual ground through the resistor 52, and the feedback signal is further applied through the resistor 53, whereby the operation of the second subtractor 23 is performed. Is realized. The operation of the gain adjuster 22 is realized by adjusting the ratio of the resistors 53 and 52. Further, the operation of the second integrating means 24 is realized by accumulating charges in the capacitor 55 connected to the inverting input and output of the operational amplifier 57.
[0025]
The comparator 58 in FIG. 4 corresponds to the comparator 25 in FIG. 2, but the signs of the outputs of the operational amplifiers 56 and 57 are the same as those of the first integrator 21 and the second integrator 24. Because of the reverse relationship, the output of the operational amplifier 56 is given to the inverting input of the comparator 58, and the output of the operational amplifier 57 is given to the non-inverting input of the comparator 58.
[0026]
As described above, both the PWM signal input from the pulse modulation means 1 to the correction circuit 2 and the PWM signal output from the power switch circuit 3 and appropriately input after being attenuated are input to the correction circuit 2 as DC components. The correction circuit 2 performs correction including this DC component. The reason is that although a DC component is included, the PWM signal is basically a binary signal, and the voltage value to be taken in the two states “H” and “L” is predetermined in each part of the circuit. This is because, for example, conventional means in an analog circuit in which a DC component is blocked by a capacitor and only a DC operating point is set separately cannot be used, and the correction circuit 2 includes an integrator having a high DC gain. This is because it is practical to stabilize the operating point of the circuit by DC feedback.
[0027]
Thus, even if feedback correction is performed including the DC potential, no particular problem occurs when the fluctuation of the power supply voltage is small. However, problems arise when the power supply voltage changes significantly. For example, in a device mounted on an automobile, it is usually required to operate without any trouble even if the power supply voltage changes in the range of 11V to 16V. Therefore, when the design center is 13.2V, the power supply voltage is almost +/−. It is necessary to ensure that it operates without trouble even if it fluctuates within a range of 20%. Under such conditions, when the above correction is performed to suppress distortion of the output signal, the maximum undistorted audio signal output is rapidly reduced particularly when the power supply voltage is lowered, as will be described below. Occurs.
[0028]
For example, in the feedback system including the correction circuit 2, when the power supply voltage is 13.2V, which is the design center, the PWM signal from the pulse modulation means 1 is not modulated, in other words, the pulse duty ratio is 50%. Assume that the gain is adjusted so that the DC potential of the amplifier output is 6.6 V which is ½ of the power supply voltage. In this case, even if the power supply voltage changes over a range of 11V to 16V, for example, the amplifier output DC potential when the PWM signal is not modulated (hereinafter simply referred to as the unmodulated amplifier output potential) is approximately 6 by feedback correction. .6V will be maintained. In this adjustment, when the power supply voltage is 13.2 V, which is the design center, the DC output potential of the amplifier reaches 11 V when the pulse duty ratio of the PWM signal output from the pulse modulation means 1 is about 80%. However, even if the power supply voltage decreases from 13.2V to 11V, the amplifier output DC potential reaches 11V when the pulse duty ratio of the PWM signal is about 80% by feedback correction. That is, when the power supply voltage drops to 11 V, it means that the amplifier output is saturated when the pulse duty ratio of the PWM signal exceeds about 80%.
[0029]
FIG. 5 illustrates this situation with a signal waveform. Reference numeral 40 denotes an output signal in an undistorted maximum output state when the power supply voltage is lowered to 11 V while the amplifier output potential is set to 6.6 V during no modulation. The waveform (sine wave) is shown. The level of the undistorted maximum output signal is (11−6.6) × 2 = 8.8 Vpp. Here, when the unmodulated amplifier output potential is shifted to 5.5V, which is 1/2 of the power supply voltage (11V) at this time, the waveform (sine wave) of the output signal in the undistorted maximum output state is 41. It will be shown. In this case, the level of the undistorted maximum output signal increases to 5.5 × 2 = 11 Vpp.
[0030]
In this way, when the power supply voltage changes in a relatively wide range, in order to maximize the undistorted maximum output, the correspondence between the PWM signal pulse / duty ratio and the amplifier output DC potential depends on the power supply voltage at that time. Specifically, it is desirable to change the setting of the feedback system so that the unmodulated amplifier output potential is always ½ of the power supply voltage. Therefore, in this embodiment, the DC output reference signal generation means 10 and the calculation means 11 are provided. These means will be described below.
[0031]
The DC output reference signal generating means 10 generates a reference signal used for maintaining the amplifier output potential at the time of no modulation at a target value. Here, as described above, the target value of the unmodulated amplifier output potential is ½ of the current value of the power supply voltage Vcc supplied to the power switch circuit 3. Therefore, in the present embodiment, the DC output reference signal generating means 10 supplies the input voltage, that is, the power supply voltage Vcc to Vcc by the internal level adjuster 202 having the gain 1 / 2K with respect to the gain 1 / K of the feedback circuit 4. Attenuate to / (2 · K). Since the AC fluctuation component included in the power supply voltage is removed by the low-pass filter 201 of the DC output reference signal generating means 10, the generated reference signal is not affected by the AC fluctuation.
[0032]
The calculating means 11 subtracts the DC output reference signal output from the DC output reference signal generating means 10 from the output of the feedback circuit 4 by the subtractor 203, and further adds the fixed potential Vsig / 2 by the adder 12. Here, if the DC component included in the output of the power switch circuit 3 is Vsw, the output Vfb of the computing means 11 is
Vfb = Vsw / K-Vcc / (2.K) + Vsig / 2 (1)
It can be expressed as.
[0033]
Here, when the PWM signal is not modulated, the correction circuit 2 operates so that the low frequency component included in the feedback signal, that is, Vfb is equal to the low frequency component Vsig / 2 included in the PWM signal. Therefore, when the relationship of Vfb = Vsig / 2 is applied to the equation (1), Vsw = Vcc / 2. Since the low-pass filter 5 generates an amplifier output from Vsw, it is clear that a desired operation can be obtained by the above configuration.
[0034]
In the present embodiment, the subtraction and addition of the DC potential by the calculation means 11 is performed on the signal that has passed through the feedback circuit 4, but this is performed directly on the output of the power switch circuit 3, and the result is fed back. It is also possible to employ a configuration that attenuates through the circuit 4. In this case, it goes without saying that the signal to be subtracted should be Vcc / 2 and the signal to be added should be K · Vsig / 2. Further, the order of subtraction and addition may be changed.
[0035]
Embodiment 2. FIG.
The block diagram of FIG. 6 shows the configuration of a class D amplifier according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the arithmetic unit 11 is not provided and a correction circuit 13 is used instead of the correction circuit 2.
[0036]
The correction circuit 13 performs basically the same operation as the correction circuit 2 in the first embodiment, but has a function of receiving the output from the DC output reference signal generating means 10 and controlling the non-modulation amplifier output potential. Is included. The circuit configuration of the correction circuit 13 is shown in FIG.
[0037]
As shown in the figure, in the correction circuit 13, the output of the DC output reference signal generating means is applied to the non-inverting input of the differential input type operational amplifier 57 constituting the second integrator through a resistor 60. The non-inverting input is further different from the configuration of the correction circuit 2 in that it is connected through a resistor 59 to a fixed potential point that provides a DC potential Vc1.
[0038]
When an integrator having a very large DC gain is inserted in the signal feedback path as in the illustrated circuit configuration, the DC operating point determined by the feedback operation is substantially determined by the operation of the integrator. Specifically, since the second integrator constituted by the operational amplifier 57 has the gain of the operational amplifier 57 in a substantially non-feedback state with respect to the DC signal, the calculation is performed as a result of the feedback operation. Regardless of how the potential of the DC output output from the amplifier 56 changes, the difference between the differential inputs caused by the potential is small. In other words, the DC operating point of the relevant part is determined so that this condition is satisfied.
[0039]
The impedance of the inverting input and the non-inverting input of the operational amplifier 57 is made sufficiently larger than the resistance values of the resistors 52, 53, 59, and 60 connected to the inverting input and the non-inverting input, so that the resistors 52, 53, 59 And 60, there is no real difficulty in sufficiently reducing the output impedance of each element that provides a signal through 60.
[0040]
Here, for convenience of explanation, the resistance values of the resistors 52 and 59 are equally R3, and the resistance values of the resistors 53 and 60 are equally R4. When the output from the DC output reference signal generating means 10 is Vcc / (2 · K) as in the first embodiment, the DC potential Vp of the non-inverting input of the operational amplifier 57 is
Vp = (Vc1 · R4 + Vcc · R3 / (2 · K)) / (R3 + R4) (2)
It becomes.
[0041]
Further, if the DC potential of the inverting input of the operational amplifier 57 is Vn, since the impedance of the capacitor 55 is infinite with respect to the DC component, its influence can be ignored.
Vn = (Vt0 · R4 + Vfb · R3) / (R3 + R4) (3)
It becomes. Vt0 is a DC potential output from the operational amplifier 56.
[0042]
If the unmodulated DC potential of the PWM signal input here is Vsig / 2, and the value of Vt0 at this time is Vt00,
Vt00 = Vc0 · (R1 + R2) / R1−Vsig · R2 / (2 · R1)
It becomes. Here, the resistance value of the resistor 50 is R1, and the resistance value of the resistor 51 is R2.
[0043]
As shown in this equation, the value of Vt00 is a fixed value determined by the DC potential of the PWM signal, the fixed potential Vc0 applied to the non-inverting input of the operational amplifier 56, and the resistance values of the resistors 50 and 51. Therefore, if the fixed potential Vc1 is set to be equal to Vt00, the first term on the right side of the equations (2) and (3) when there is no PWM signal modulation becomes equal.
[0044]
As described above, when the correction circuit 13 is operating normally, Vp and Vn expressed by the equations (2) and (3) are substantially equal. In this case, the right side of the equations (2) and (3) The second term is also equal. That is, Vfb = Vcc / (2 · K). This indicates that the feedback operation is performed so that the DC potential of the feedback signal becomes equal to the DC output reference signal when the PWM signal is not modulated.
[0045]
In addition, when the DC component of the power switch circuit 3 is Vsw and Vfb = Vsw / K, a feedback operation is performed so that Vsw becomes 1/2 of the power supply voltage Vcc, that is, a desired operation is performed. It is shown that.
[0046]
As a setting condition, it is possible to set all of R1 to R4 to the same resistance value R and set the fixed potential Vc0 to Vsig / 2. In this way, Vt00 = Vsig / 2 and the fixed potential Vc1 is the same. Since Vsig / 2 can be set, the circuit configuration is simplified.
[0047]
In the circuit configuration described above, the resistance values of the resistors 52 and 59 are equal to each other and the resistance values of the resistors 53 and 60 are equal to each other, but the same effect can be obtained even if they have different configurations.
[0048]
Further, although the configuration is slightly complicated, instead of supplying the output of the DC output reference signal generating means 10 to the non-inverting input of the differential amplifier 57 constituting the second integrator, means for inverting this signal, that is, It is also possible to provide means for reversing the direction of increase / decrease of the DC output reference signal with respect to increase / decrease of the power supply voltage, and to apply the inverted signal to the inverting input of the differential amplifier 57 via a resistor. In this case, since the potential of the non-inverting input of the differential amplifier is fixed, this amplifier can be easily realized.
[0049]
The class D amplifier described above has a single-ended output stage, but the present invention is not limited to this, and has two output stages that output audio signals that are 180 degrees out of phase with each other. The present invention can also be applied to a so-called BTL configuration. That is, the distortion improvement effect can be obtained in the same manner by additionally applying the correction circuit having the above configuration to each output stage having the BTL configuration.
[0050]
【The invention's effect】
According to the present invention, the distortion of the output signal due to the fluctuation of the power supply voltage supplied to the power switch circuit is greatly reduced compared to the conventional case, and the distortion-free maximum even if the power supply voltage changes within a relatively wide range. A high-efficiency class D amplifier is provided that does not significantly reduce the output level.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a class D amplifier according to Embodiment 1 of the present invention.
FIG. 2 is a block diagram illustrating a configuration of a correction circuit of the class D amplifier according to the first embodiment.
FIG. 3 is a diagram showing signal waveforms at various parts of the class D amplifier according to the first embodiment.
4 is a circuit diagram of a correction circuit of the class D amplifier according to Embodiment 1. FIG.
FIG. 5 is a diagram showing an output waveform of the class D amplifier according to the first embodiment.
FIG. 6 is a block diagram showing a configuration of a class D amplifier according to Embodiment 2 of the present invention.
FIG. 7 is a circuit diagram of a correction circuit of the class D amplifier according to the second embodiment.
[Explanation of symbols]
1 pulse modulation means, 2 correction circuit, 3 power switch circuit, 4 feedback circuit, 5 low-pass filter, 6 speaker, 7 first constant voltage circuit, 8 second constant voltage circuit, 9 power supply terminal, 10 DC output reference Signal generating means, 11 computing means, 13 correction circuit, 20 first subtractor, 21 first integrator, 22 gain adjuster, 23 second subtractor, 24 second integrator, 25
Comparator.

Claims (4)

Switch means for switching a DC power supply voltage in accordance with a pulse width modulated input signal, and correcting the pulse width of the input signal supplied to the switch means in accordance with the amplitude of the feedback signal generated from the output of the switch means A class D amplifier including feedback correction means,
Subtracting means for subtracting a reference voltage generated based on a DC component of the power supply voltage from the feedback signal, and adding means for adding a fixed DC voltage to the output of the subtracting means, the output of the adding means being the feedback A class D amplifier comprising arithmetic means for supplying correction means . Switch means for switching a DC power supply voltage in accordance with a pulse width modulated input signal, and correcting the pulse width of the input signal supplied to the switch means in accordance with the amplitude of the feedback signal generated from the output of the switch means A class D amplifier including feedback correction means,
The feedback correction means is a first integration means for integrating the input signal; a second integration means for integrating a difference between the feedback signal and a reference voltage generated based on a DC component of the power supply voltage; Comparing means for comparing the outputs of the first and second integrating means, and the output of the comparing means is supplied to the switching means. The second integrating means applies the feedback signal to an inverting input via a first resistor, and the reference voltage and the fixed voltage are non-inverted via second and third resistors, respectively. 3. A class D amplifier according to claim 2 , comprising a differential amplifier applied to the input. The second integrating means applies the feedback signal and the inverted reference voltage to an inverting input via a first resistor and a second resistor, respectively, and the fixed voltage causes the third resistor to The class D amplifier according to claim 2 , further comprising a differential amplifier that is applied to the non-inverting input via the terminal.

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