JP4736630B2 - D class amplifier - Google Patents

Description

  The present invention belongs to the technical field of class D amplifiers (class D amplifiers) used in audio-visual equipment.

  As a D-class amplifier for pulse width modulation (PWM) used in audio amplifiers, motor drivers, etc. of digital audio equipment, a so-called feedback type D-class that improves the distortion as shown in the circuit diagram of FIG. There is an amplifier 50.

  The D class amplifier 50 is generated by the triangular wave generation circuit 3 from the operational amplifier 1 that amplifies the audio signal Vin input to the + input terminal, the output signal Vo of the operational amplifier 1 and the master clock (PWM generation clock) 2. A pulse width modulation circuit 5 for inputting a triangular wave to the comparator 4 for pulse width modulation, an output stage switching transistor (power amplifier) 9 having a pair of push-pull MOSFETs, and the pulse width modulation circuit 5 A driver circuit 7 for switching the output stage switching transistor 9 by inputting the pulse width modulation output signal VPWM as a switching control signal, and an inductor 34 and a capacitor 36 connected to the output terminal A of the output stage switching transistor 9. An output low-pass filter 41 and the output low-pass filter 41 the output signal Vout of the operational amplifier 1 of the - has a structure comprising a feedback loop 8 for feeding back to the input terminal. A plurality of small square frames in the figure are passive elements set as appropriate.

  As a publicly known document relating to the feedback type D class amplifier, for example, the following [Patent Document 1] describes a feedback type D class amplifier 60 having a circuit configuration as shown in FIG.

  The D-class amplifier 60 was created to solve the problem of radio frequency interference (RFI) caused by short-through current during switching. The audio signal Vin is input to the negative input terminal of the operational amplifier 10, The hysteresis voltage is also input to the hysteresis voltage supply source 42 side including the differential amplifiers 44 and 46 and the multiplier 48. The hysteresis voltage is held constant over the range of the audio signal Vin in the operating frequency of the pulse width modulator. Thus, the circuit is characterized in that it changes so as to compensate for Vin. In FIG. 8, reference numeral 40 is a pulse width modulator comprising a window comparator 22 comprising differential amplifiers 16 and 18 and an SR flip-flop circuit 28 for receiving output signals 24 and 26 thereof. Reference numeral 32 denotes a power amplifier having a pair of push-pull type switching transistors (MOSFETs), and reference numeral 41 denotes an output low-pass filter including an inductor 34 connected in series to a speaker SPK of a load and a capacitor 36 connected in parallel. .

JP 2003-78363 A

  In the feedback class D-class amplifier 50 as shown in the circuit diagram of FIG. 7, the output signal Vout of the output low-pass filter 41 includes a modulated wave (carrier, for example, clock frequency f = 400 kHz) that cannot be completely removed. ) Residual carrier noise (a jagged noise waveform appearing in the output signal Vout), and the residual carrier noise is also fed back via the feedback loop 8.

  Thus, as shown in the waveform diagram of the same time axis of the output signal Vo of the operational amplifier 1, the pulse width modulation output signal VPWM, and the output signal Vout in FIG. As a result, a waveform in which a considerable residual carrier noise is superimposed on the output Vo of the operational amplifier 1 is output.

When the output Vo of the operational amplifier 1 on which the residual carrier noise is superimposed is input to the comparator 4 of the pulse width modulator 5, the following situations (1), (2), and (3) may be reached. Come out.
(1) Since residual carrier noise is superimposed on the feedback signal S1 after passing through the output low-pass filter 41, instantaneous intermodulation distortion occurs in the first-stage operational amplifier 1 and deteriorates the distortion factor of the D-class amplifier 50 (FIG. 9). (See Vout voltage waveform).
(2) The audio signal Vo input by the subsequent pulse width modulator 5 is compared with a triangular wave, but there may be a case where an erroneous comparison is caused by residual carrier noise that has passed through the operational amplifier (operational amplifier) 1 at that time. possible.
(3) Since the residual carrier noise is superimposed at the time of maximum modulation by the pulse width modulator 5, an overmodulation state is likely to occur (refer to the VPWM voltage waveform in FIG. 9, so-called tooth-missing state). The maximum output amplitude may be limited.

  In this regard, the D-class amplifier 60 shown in FIG. 8 described in [Patent Document 1] is mainly intended to solve the problem of radio frequency interference, and residual carrier noise is transmitted via a feedback loop. It does not give an effective suggestion about the countermeasure against the deterioration of the distortion rate by superimposing the input to the comparator of the pulse width modulator 40.

  Generally, in order to remove the residual carrier noise as described above, an effect cannot be obtained unless an output low-pass filter 41 of the same level as that of the master clock 2 is connected. However, on the other hand, a feedback system (phase margin characteristic at the gain intersection) ) And the stability of the D-class amplifier is deteriorated, which makes it difficult to design the circuit of the feedback-type D-class amplifier.

  The present invention has been made in view of the above circumstances, and a residual carrier for reducing adverse effects caused by feedback of residual carrier noise present in an output signal in a feedback class D-class amplifier as shown in FIG. An object is to provide a high-performance D-class amplifier equipped with a reduction circuit.

The present invention
(1) an operational amplifier 1 for amplifying the audio signal Vin;
A pulse width modulation circuit 5 that performs pulse width modulation by comparing the output signal Vo of the operational amplifier 1 with a triangular wave generated from the master clock 2 by a comparator 4 and outputs a pulse width modulation output signal VPWM;
An output stage switching transistor 9;
A driver circuit 7 for switching the output stage switching transistor 9 based on the pulse width modulation output signal VPWM;
An output low-pass filter 41 connected to the output terminal A of the output stage switching transistor 9;
A feedback loop 8 for feeding back the output signal Vout of the output low-pass filter 41 to the input side of the operational amplifier 1;
The output signal Vout of the output low-pass filter 41 is sampled in synchronism with the master clock 2 at the same clock frequency f as that of the master clock 2 of the pulse width modulation circuit 5 and is inserted into the feedback loop 8 and a high frequency component. And a residual carrier reduction circuit 15 for reducing residual carrier noise included in the output signal Vout of the output low-pass filter 41 and outputting the reduced signal to the input stage side of the operational amplifier 1. By providing the D class amplifier 20, the above-mentioned problems are solved.
(2) an operational amplifier 1 for amplifying the audio signal Vin;
A residual carrier reduction circuit 15 for reducing residual carrier noise included in the output signal Vo of the operational amplifier 1;
A pulse width modulation circuit 5 that outputs a pulse width modulation output signal VPWM by performing pulse width modulation by comparing the output signal Vo ′ of the residual carrier reduction circuit 15 with a triangular wave generated from the master clock 2 by a comparator 4. When,
An output stage switching transistor 9;
A driver circuit 7 for switching the output stage switching transistor 9 based on the pulse width modulation output signal VPWM;
An output low-pass filter 41 connected to the output terminal A of the output stage switching transistor 9;
A feedback loop 8 that feeds back the output signal Vout of the output low-pass filter 41 to the input side of the operational amplifier 1;
The residual carrier reduction circuit 15 samples the output signal Vo of the operational amplifier 1 in synchronization with the master clock 2 at the same clock frequency f as that of the master clock 2 of the pulse width modulation circuit 5 and generates a high frequency component. By removing the residual carrier noise contained in the output signal Vo of the operational amplifier 1 by removing the D-class amplifier 30, the above-mentioned problem is solved.

The D class amplifier according to the present invention is configured as described above.
(1) Since the residual carrier noise contained in the output signal fed back by the feedback D-class amplifier can be reduced with a simple configuration before the pulse width modulation, the overmodulation of the pulse width modulation is prevented, and the amplifier performance (distortion) Rate).
(2) Since the influence of residual carrier noise included in the output signal to be fed back is reduced at the stage of pulse width modulation, it becomes easier to obtain the maximum output power and the power supply utilization rate is improved.

  An embodiment of a D class amplifier according to the present invention will be described with reference to the drawings.

  FIG. 1 is a block circuit diagram showing a D-class amplifier according to the first embodiment of the present invention. FIG. 2 is a block circuit diagram showing a D-class amplifier according to the second embodiment of the present invention. FIG. 3 is a block circuit diagram of a residual carrier reduction circuit according to the present invention. FIG. 4 is a circuit diagram of a specific example of the residual carrier reduction circuit. FIG. 5 shows the voltage waveform of the output voltage Vo ′ of the residual carrier reduction circuit and the voltage waveform of the output VPWM of the PWM modulation circuit input to the comparator of the PWM modulation circuit in the D class amplifier according to the second embodiment of the present invention. It is a voltage waveform diagram which contrasts the voltage waveform of (400 kHz) and the output voltage Vout on the same time axis. FIG. 6 shows the voltage waveform (enlarged) of the sampling signal (1shot signal) and output voltage Vo ′ of the residual carrier reduction circuit of the D-class amplifier according to the second embodiment of the present invention when there is no conventional residual carrier reduction circuit. FIG. 6 is an enlarged waveform diagram of a voltage axis and a time axis to be compared with the signal Vo.

  First, the D class amplifier 20 of the first embodiment shown in FIG. 1 includes an operational amplifier 1 that amplifies an audio signal Vin, an output signal Vo of the operational amplifier 1 and a master clock 2 (clock frequency f = about 400 kHz). A pulse width modulation circuit 5 that inputs a triangular wave generated from the signal to the comparator 4 and performs pulse width modulation (PWM), an output stage switching transistor 9 (power amplifier) including a pair of push-pull CMOSFETs, and the pulse width A driver circuit 7 for switching the output stage switching transistor 9 by inputting the pulse width modulation output signal VPWM of the modulation circuit 5 as a switching control signal, an inductor 34 and a capacitor connected to the output terminal A of the output stage switching transistor 9 An output low-pass filter 41 comprising 36 and the output A D-class amplifier comprising a feedback loop 8 that feeds back the output signal Vout of the pass filter 41 to the input side of the operational amplifier 1, and in particular, the pulse width modulation circuit 5 as shown in the block circuit diagram of FIG. A sampling circuit 11 composed of an analog switch 13 and a one-shot circuit 12 for sampling the output signal Vout of the output low-pass filter 41 in synchronization with the same clock frequency f as the master clock 2 and a high level of the output signal Vs of the sampling circuit 11. A residual carrier reduction circuit 15 (indicated by a hatched small frame in FIG. 1) having a simple circuit configuration surrounded by a dotted line frame and a low-pass filter 14 that does not affect the feedback system for removing the band component, The structure inserted in the loop 8 is characterized.

  A specific example of the residual carrier reducing circuit 15 is shown in FIG. The low-pass filter 14 is composed of a 1 kΩ resistor R7 and a 47 pF capacitor, the analog switch 13 of the sampling circuit 11 is an electronic switch circuit of a transistor or a diode, and the one-shot circuit 12 is a CMOS logic IC (HC-type D flip-flop of HC74D). Circuit and inverter circuit of HC04D).

  By adjusting the sampling timing and sampling time of the sampling circuit 11, only the audio signal component can be sampled, and if only the high frequency noise component at the time of remaining sampling is removed by the low pass filter 14, the residual carrier can be reduced. become. Since the low-pass filter 14 has the purpose of removing only high-frequency noise components at the time of sampling, the circuit design is simple because it does not affect the feedback system.

  Thus, in the D-class amplifier 20 having the above circuit configuration, residual carrier noise (residual component of the carrier switched at the master clock frequency f) superimposed on the output signal Vout fed back is the residual carrier reduction circuit. After being greatly reduced by 15, the signal is inputted to the negative input terminal of the first stage operational amplifier (OP amplifier) 1, so that the output signal Vo of the operational amplifier 1 becomes a good voltage waveform with less noise and a pulse width modulation circuit 5 is input to the comparator 4 of FIG. 5, so that erroneous comparison is prevented and an overmodulation state is prevented.

  As can be seen from the above, the gist of the present invention is that the residual carrier noise superimposed on the output signal Vout of the D class amplifier fed back to the input side of the operational amplifier 1 in the first stage is converted into the comparator 4 of the pulse width modulation circuit 5. By reducing the audio signal input to, an over-modulation state is prevented by preventing erroneous comparison during pulse width modulation. Therefore, the residual carrier reduction circuit 15 is not limited to the configuration of the D class amplifier 20 inserted in the feedback loop 8, but the pulse width as in the D class amplifier 30 of the second embodiment shown in FIG. A sampling circuit 11 that samples the output signal Vo of the operational amplifier 1 at the same clock frequency f as the master clock 2 of the modulation circuit 5, and a low-pass filter 14 that removes a high-frequency component of the output signal Vs of the sampling circuit 11. Even if the residual carrier reducing circuit 15 is inserted between the output side of the operational amplifier 1 and the input side of the pulse width modulation circuit 5, substantially the same operation and effect can be obtained.

  5 shows the voltage waveform of the output voltage Vo ′ of the residual carrier reduction circuit 15 input to the comparator 4 of the PWM modulation circuit 5 in the D class amplifier 30 and the voltage waveform of the output signal VPWM of the PWM modulation circuit 5 (because it is a 400 kHz pulse). In the figure, the lines are densely overlapped and displayed in black solid form.) Is a voltage waveform diagram in which the voltage waveform of the output voltage Vout of the D class amplifier is compared on the same time axis, but it is clear when compared with FIG. In addition, the superposition of residual carrier noise is greatly reduced in Vo ′ (see also Vo ′ in FIG. 6 and the enlarged waveform diagram of the voltage axis and the time axis of the one-shot signal), and VPWM is in an overmodulated state (missing tooth). It can be seen that this is not the case. It can also be seen that the distortion rate of the output signal Vout does not deteriorate and the maximum output amplitude is not limited.

1 is a block circuit diagram showing a D-class amplifier according to a first embodiment of the present invention. It is a block circuit diagram which shows D class amplifier of 2nd Embodiment which concerns on this invention. It is a block circuit diagram of a residual carrier reduction circuit according to the present invention. It is a circuit diagram of the specific example of a residual carrier reduction circuit. The voltage waveform of the output voltage Vo ′ of the residual carrier reduction circuit and the voltage waveform of the output VPWM of the PWM modulation circuit (400 kHz) input to the comparator of the PWM modulation circuit in the D-class amplifier according to the second embodiment of the present invention FIG. 6 is a voltage waveform diagram comparing the voltage waveform of the output voltage Vout on the same time axis. The sampling signal (1shot signal) of the residual carrier reduction circuit of the D-class amplifier according to the second embodiment of the present invention and the voltage waveform (enlarged) of the output voltage Vo ′ are output signals when there is no conventional residual carrier reduction circuit. It is an enlarged waveform figure of the voltage axis and time axis compared with Vo. FIG. 6 is a block circuit diagram of a conventional feedback class D-class amplifier. FIG. 6 is a circuit diagram of a feedback-type D-class amplifier described in [Patent Document 1]. A voltage waveform diagram in which the voltage waveform of the output signal Vo of the first stage operational amplifier of the conventional D-class amplifier of the feedback system, the voltage waveform (400 kHz) of the output VPWM of the PWM modulation circuit, and the voltage waveform of the output voltage Vout are compared on the same time axis. It is.

Explanation of symbols

1 operational amplifier
2 Master clock
3 Triangular wave generation circuit
4 comparator
5 Pulse width modulation circuit
7 Driver circuit
8 Feedback loop
9 Output stage switching transistor
11 Sampling circuit
12 1-shot circuit
13 Analog switch
14 Low-pass filter
15 Residual carrier reduction circuit 20, 30, 50, 60 D class amplifier
34 Inductor
36 capacitors
41 Output low-pass filter SPK Load speaker Vin Audio signal
Vo Output signal of operational amplifier 1 VPWM Pulse width modulation output signal Vout Output low-pass filter output signal
Output signal of Vs sampling circuit
f Clock frequency

Claims (2)

An operational amplifier for amplifying the audio signal;
A pulse width modulation circuit that outputs a pulse width modulation output signal by performing pulse width modulation by comparing an output signal of the operational amplifier and a triangular wave generated from a master clock by a comparator;
An output stage switching transistor;
A driver circuit for switching the output stage switching transistor based on the pulse width modulation output signal;
An output low-pass filter connected to an output terminal of the output stage switching transistor;
A feedback loop for feeding back the output signal of the output low-pass filter to the input side of the operational amplifier;
By inserting the feedback loop, sampling the output signal of the output low-pass filter in synchronization with the master clock at the same clock frequency as the master clock of the pulse width modulation circuit, and removing the high frequency component, A D-class amplifier, comprising: a residual carrier reduction circuit that reduces residual carrier noise contained in an output signal of an output low-pass filter and outputs the residual carrier noise to an input stage side of the operational amplifier. An operational amplifier for amplifying the audio signal;
A residual carrier reduction circuit for reducing residual carrier noise included in an output signal of the operational amplifier;
A pulse width modulation circuit that performs pulse width modulation by comparing the output signal of the residual carrier reduction circuit with a triangular wave generated from a master clock by a comparator, and outputs a pulse width modulation output signal;
An output stage switching transistor;
A driver circuit for switching the output stage switching transistor based on the pulse width modulation output signal;
An output low-pass filter connected to an output terminal of the output stage switching transistor;
A feedback loop that feeds back the output signal of the output low-pass filter to the input side of the operational amplifier;
The residual carrier reduction circuit samples the output signal of the operational amplifier in synchronization with the master clock at the same clock frequency as the master clock of the pulse width modulation circuit and removes the high frequency component, thereby A D class amplifier characterized by reducing residual carrier noise contained in an output signal of the amplifier.

Images