JPH0330373A - Semiconductor non-volatile memory - Google Patents

Abstract

PURPOSE:To avoid the soft write making rapid reading-out feasible by a method wherein an electron injection/extraction region is isolated from a reading-out region through the intermediary of a field region. CONSTITUTION:A memory transistor is divided into an electron injection/ extraction region A and a reading-out region B through the intermediary of a field region 22 then the former region A is formed into a capacitor structure while the latter region B is formed into a semiconductor volatile memory comprising a transistor. Next, the first gate electrodes 25 of a capacitor and the transistor are connected to each other through the intermediary of the field region 22. Through these procedures, the electron injection/extraction region A and the reading-out region B are divided into two independent regions later to avoid the soft write such as floating gate injection, etc., of hot electrons generated during the reading-out process. Furthermore, the memory transistor is divided into the said two regions to reduce the additional capacity to lines for accelerating the reading-out speed.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to the structure of a semiconductor non-volatile memory device, and in particular to an electrically rewritable semiconductor non-volatile memory device (Electrical 13'). IErasable
ePI? It is used for OM (abbreviated as E2 FROM).

E. Prior Art] One conventional E2 PROM cell consists of two transistors C and D, as shown in FIG. The operation of this cell will be explained.

The transistor C is an element for holding data, and has an electrically insulating polysilicon layer called a floating gate above the channel portion with a first gate insulating film interposed therebetween. Depending on the potential of this floating gate, the data 11'' and rOJ can be stored depending on whether the transistor C is turned on or off. Further above the floating gate is a polysilicon layer called a control gate with an insulating film interposed therebetween. The control gate plays an important role in writing data to the floating gate.

Transistor D is a selection transistor. When cells are arranged in a matrix, transistor D is turned on only when selected, outputs the data stored in transistor C to drain d2, and is turned off at other times. It works to make the output terminal high impedance.

The operation of writing data to the above cell will be explained.

There is a thin part of the silicon oxide film (tunnel part) in the floating gate and drain d1 parts, and if electrons are moved through this part, for example, if electrons are extracted from the floating gate, the same effect occurs. A hole remains in the gate, and the potential increases. This potential forms an inversion layer in the channel portion, and the transistor C is turned on. On the other hand, when electrons are injected into the floating gate, the potential of the gate decreases and the channel becomes in an accumulation state.
Transistor C is turned off.

Ejection of electrons from the floating gate or injection of electrons into the floating gate is performed as follows.

The (electron emission) control gate CG is set to GND, and the (grounded) drain is set to a high potential Vpp (for example, 20 V). Floating game! • has an intermediate potential due to the potential difference between the control gate and the drain d. Therefore, a high electric field is locally applied to the tunnel portion (because the oxide film in the tunnel portion is thin), and electrons flow from the floating gate toward the drain dl via this field.

(Electron injection) Contrary to electron emission, the control gate CG is set to a high potential vpp and the drain is set to GND.

Although a high electric field is still applied to the tunnel part, it is in the opposite direction to the electron emission, so there is a floating field from the drain.
Electron movement occurs towards the gate.

In both cases of electron emission and injection, the selection transistor D
must be left on.

In this way, after writing data, the control
Gate CG is set to GND level.

This E2 PROM cell basically has an inherent danger of soft writing (erroneous writing).

First, I will explain the mechanism of the software and lights.

In read or mode, the drain d2 of the cell is biased to a certain potential level. When the stored data of the selected cell is "0", the floating gate is in an electron injection state and the data holding transistor C is off, so the bias potential of the drain remains unchanged.

On the other hand, when the stored data is "1", the data holding transistor C is turned on, and the potential of the drain d1 is transferred to the source S via the selection transistor D.

(GND). At this time, the control gate is set to the GND level as described above.

Let us now show that a soft write may occur when reading a "0" cell.

When the select transistor D is turned on, the bias potential of the do1 twin is transmitted to the diffusion layer below the tunnel portion. Since the memory transistor C is in the off state, this potential remains held. At this time, the floating gate is in a state where electrons are injected, so the potential is low,
If the drain bias potential is high enough, electrons will be emitted from the floating gate through the tunnel.

If reading is continued for a long time, the floating gate will run out of 73 children, and eventually the memory transistor C will be turned on.

This is exactly equivalent to writing "1".

As described above, there is a problem in that the stored data changes while being read (soft write).

Conventionally, in order to prevent this soft write, the drain bias value is suppressed to 1.0 V or less.

(Problem to be solved by the invention) As described above, in order to prevent writes during software, bit
When the potential of the line BL is set to a maximum of 11 V, the logic rlJ
, rOJ are respectively maximum 1.0V and minimum Ov, and the potential difference between the two logics is 1.0V at maximum. OV L, Kanai. In this case, for example, the power supply Vdd
When the voltage is -5V, the drain potential of the "0" cell is 1. O
A level medium shifter is required to convert from v to 5v. In reality, high-speed amplification circuits called sense amplifiers are used, but these circuits are by no means simple, and their design is always fraught with great difficulties.

In particular, even if the power supply voltage Vdd is varied from, for example, 2V to 6V, it is almost impossible to design the device to perform correct operation.

A 2-bus method is used to prevent the above-mentioned soft write and further increase the drain potential. As shown in FIG. 7, the source terminal S1 of the memory transistor in the cell shown in FIG. F is set to GND), and when reading, cell data is read from bus F (at this time, bus G is set to GND).

In this way, the soft write is improved for the following reason. When the data stored in the cell is rOJ, the memory transistor C is off, so the bus F has a predetermined bias value.

At this time, the bias value is not applied to the tunnel portion since the memory transistor C is off. This can prevent soft writes before improvement.

On the other hand, when the stored data is rlJ, the memory transistor C is turned on and the bus F is pulled to the GND side. This state is almost the same as the cell before improvement.

However, since software dispute writing can be prevented,
When the bias value of bus F is increased, selection transistor D
Immediately after turning on, a large current flows from bus F to bus C. At this time, hot electrons are generated in the channel portion of the memory transistor, pass through the tunnel portion, and jump into the floating gate. Since there are many holes in the floating gate,
They annihilate with the incoming electrons, and the number of holes decreases. As a result, the potential of the floating gate decreases and the transistor characteristics deteriorate. This phenomenon occurs only immediately after the selection transistor D starts to turn on (after that,
(Since the potential of the bus F decreases, no hot electrons are produced.) The number of holes that disappear in - times of switching is small. However, if you switch repeatedly,
The total number of holes erased becomes very large, and it becomes as if "0" has been written. In other words, a different soft write occurred than in the cell before the improvement. Conversely, this is a problem that occurs in the case of "1" storage.

Furthermore, the disadvantage of this 2-bus method is that the bus F
The added capacity is large.

When a large number of cells are connected to bus F, and when "1" is written in all of those cells, when one cell is selected, the channel part of the memory transistor of the other cell and Since all the capacitance of the source portion is added to the bus F (see FIG. 8), the speed is significantly reduced. In the conventional cell, the select gate D was connected to the bit φ line BL side, so there was no such capacitance. In FIG. 8, 11 is a row decoder, 12 is a cell, 13 is a column pull-up section, 14 is a current limiter, 15 is a sense amplifier, and 16 is a latch circuit.

An object of the present invention, in the field of electrically rewritable nonvolatile memory devices (R2FROM), is to provide an R2FROM that can prevent soft writes and that can be read at high speed.

[Structure of the Invention] (Means and Effects for Solving Problems) The present invention provides: (1) In an electrically rewritable semiconductor nonvolatile memory device, a first insulating film formed on a semiconductor substrate; an electron injection or extraction region having a first gate electrode in an electrically floating state and a second gate electrode on a second insulating film on this electrode; via this region and a field region; Source and drain regions that are element-separated and formed on the surface region of the semiconductor substrate, a channel region formed between these regions, and a first insulating film laminated on the channel region, electrically floating. a readout region having a first gate electrode on a first gate electrode and a second gate electrode on a second insulating film above the readout region; the first gate electrodes of the electron injection or extraction region The semiconductor nonvolatile memory device is characterized in that the second gate electrodes and the second gate electrodes are integrally connected to each other. Further, the present invention provides the semiconductor nonvolatile memory device according to item (1), wherein (2) the first insulating film of the electron injection or extraction region has a partially thin tunnel region. Further, the present invention provides a configuration in which (3) the electron injection or extraction is performed using at least a diffusion layer formed in the semiconductor substrate under the tunnel region and having a conductivity type opposite to that of the substrate, and a second gate electrode. The semiconductor nonvolatile memory device according to item (2) above is characterized in that: Further, the present invention provides the following features: (4) The readout area is an LDD (Ligl+tl
Any one of (1) to (3) above, characterized in that it constitutes a transistor with a y DopedDrain structure.
The semiconductor non-volatile memory device described in 1.

That is, the present invention provides a value E2FRO consisting of a two-layer gate structure.
In M, the memory transistor is separated into an electron injection/extraction region and a readout region via a field region, the electron injection/extraction region has a capacitor structure, and the readout region is a semiconductor volatile memory device consisting of a transistor. The capacitor and the first gate electrode of the transistor are connected through the field region.

As described above, the soft write, which is a drawback of the conventional one-bus system, is solved because the electron injection/extraction region, which serves as the electron tunnel section, is separated from the readout region. Furthermore, the soft write problem caused by injection of hot electrons into the floating gate, which is a drawback of the conventional two-bus system, can be solved by using an LDD structure for the transistor in the readout region. In addition, the problem of reduced operating speed due to the load capacitance of the source section is resolved because the read area is independent from the write system, so the load capacitance is reduced and higher speeds can be achieved.

(Example) An example of the present invention will be described below with reference to the drawings. 1st
The figure shows the same embodiment, and here shows a memory cell portion of an R2FROM having a two-layer polysilicon structure. Same figure (0)
is a pattern plan view, and figure (a) is a-a' of figure (o).
Figure 2 is a cross-sectional view along line bb', Figure 2 is a cross-sectional view taken along line c-c', Figure 2 is the equivalent circuit of Figure 1. It is. In these figures, A is an electron injection/extraction region, and B is a readout region. Also 21
is a P-type silicon substrate, 22 is a field region (insulating film)
, 23 is a first insulating film, 24 is a tunnel insulating film, 25 is a first polysilicon electrode (floating ln gate FG), 26 is a second polysilicon electrode (control gate CG), 27 is a second insulating film, 28 is a metal (Ag) wiring, 291 is a diffusion layer under the tunnel film (N type), 292 is a low concentration diffusion layer (N- type)
, 30 is a high concentration diffusion layer (N0 type), 31 is a cross-hatched area, 32 is a tunnel window, 33 is a contact, WD is a write drain, R8 is a read source, and RD is a read drain. It is.

The main features of this configuration are as follows.

(1) Electron injection/extraction 6A area A and readout area B
are separated from each other by a field region 22.

(2) The electron injection/extraction region A, which also includes the tunnel window, is not a transistor but a complete capacitor (4-structured), and the readout region B is a transistor.

Next, regarding the semiconductor memory device with this configuration, electron injection,
It shows a series of electron extraction and readout operations.

(a) Electron injection (in E2 FROM, this is an erasing action)
: Write drain WD is set to OV, control gate (C
G)1. :High voltage V\)pc approx. 20V)i, :When biased, electrons are transferred from the WD to the diffusion layer 29. below the tunnel oxide film 24. It travels up to the point where it passes through the tunnel oxide film and is injected into the floating gate FC. At this time, there are two N-type layers under the tunnel oxide film, so it is easier to inject electrons into the FG than if it were a P-type layer (see Figure 3). By setting the second control gate CG to OV and biasing the write drain WD to vpp c (approximately 20V), the floating gate FG follows a path completely opposite to that of electron injection.
The write drain WD is connected to the write drain WD.

(c) Readout: As mentioned above, unlike the conventional method, a dedicated readout path is used for readout.

In other words, set the read drain RD to Vcc (approximately 5y)
In this case, the read source R8 is set to OV, and the control gate CG is set to OV.
Perform this with OV.

In readout after electron injection, floating gate) FG l:
l: Since electrons are accumulated, the threshold value is shifted in the positive direction, and no current flows during the above readout.

On the other hand, after electron extraction, there is a shortage of electrons in the floating gate, so the threshold shifts in the negative direction, and current flows in the above reading method. The amount of current increases as the number of electrons in the floating gate becomes insufficient (as the -threshold value shifts in the negative direction). Furthermore, the same effect can be obtained by increasing the VDS during reading.

Next, the features of the present invention described above will be compared and considered with the problems of the prior art. Problems with the prior art include (1) Drain readout (1-bus method), which has difficulty in circuit design to prevent soft I/write, and requires the drain voltage to be lower than 1V.

On the other hand, regarding the 2-bus type cell, it was shown that (1) hot electrons are injected into the floating gate, and (2) there is a decrease in speed due to the load capacitance of the source section. On the other hand, in the semiconductor device according to the present invention, the above-mentioned problem (2) can be solved by separating the readout region of the tunnel portion, which was the cause of soft write, from the electron injection/extraction region. Regarding (2), since the read transistor has an LDD eM structure different from the structure of conventional memory transistors, the electric field between the source and drain is relaxed, and the generation of channel hot electrons is significantly suppressed. As for (2), as mentioned earlier, the read system is separate from the write system, so the additional capacity is small.
It can maintain the same speed as normal high-speed ROM.

When the embodiment of the semiconductor memory device of FIG. 1 of the present invention is arranged as an actual matrix of memory cells, an embodiment in which a selection gate D is provided between the drain and the control gate is shown in FIG. The role of this selection gate D is to ensure address selection during writing/erasing/reading. This has the effect of preventing so-called half-selection (also called erroneous reading, in which data of an element is read through an adjacent depressed element).

FIG. 5 shows an example of operation bias during writing/erasing/reading. In this way, regarding electron injection (in the case of erasing), Vpp (approximately 20V) is applied to the selection gate SG and control gate CG.
), and the remaining terminals are set to 0・■. Electronic withdrawal (
In the case of writing), Vpp (k 20 V) is applied to the selection gate SG and write drain WD, and the remaining terminals are set to OV.

For reading, Vec' (5V) is applied to the read drain RD and the selection gate SG, and the remaining terminals are set to OV.

Note that the present invention is not limited to the above embodiments, and can be applied in various ways. For example, the electrode made of the polysilicon film mentioned above may of course be made of polycide or silicide. Further, the insulating film 23 existing between the substrate and the floating gate in the readout region B may have the same thickness as the partially thin first insulating film existing in the electron injection/extraction region A in the figure. Further, in the embodiment, an LDD structure is used to prevent hot electrons that cause malfunctions, but other structures may be used as long as the same preventive effect can be obtained.

[Effects of the Invention] As explained above, according to the present invention, a semiconductor memory device according to the present invention is provided in which an electron injection/extraction region and a readout region are separated and each of them is made independent in an E2 FROM having a gate multilayer structure. By using this method, we were able to solve the reliability problem caused by soft write, such as floating gate injection of hot electrons during readout, from a structural perspective.

Furthermore, by separating the above two regions, the additional line capacitance is reduced, and the operation speed is also improved.

[Brief explanation of drawings]

Fig. 1 (0) is a pattern plan view of an embodiment of the present invention, Fig. 1 (a) to c) is a cross-sectional view of the same, Fig. 2 is an equivalent circuit diagram, and Fig. 3 is a detailed view of the same part. , FIG. 4 is a pattern plan view of a cell embodiment for forming the same cell matrix, FIG. 5 is a chart showing an example of the same bias, and FIGS. 6 to 8 are circuit diagrams of a conventional device. 21... P-type substrate, 22... Field region, 23
゜24.27... Insulating film, 291... N-type diffusion layer under tunnel film, 292... N- layer, 30... N ten layer,
A...electron injection/extraction region, B...readout region.

Claims (4)

[Claims] (1) In an electrically rewritable semiconductor nonvolatile memory device, a first gate electrode is electrically floating on a first insulating film formed on a semiconductor substrate, and a second gate electrode on this electrode is an electron injection or extraction region having a second gate electrode on an insulating film; source and drain regions separated from this region via a field region and formed in the surface region of the semiconductor substrate; A channel region formed between the regions, a first gate electrode electrically floating on a first insulating film laminated on this channel region, and a second insulating film on this electrode. a readout region having a second gate electrode; a first gate electrode of the electron injection or extraction region;
A semiconductor nonvolatile memory device characterized in that gate electrodes of the two are integrally connected to each other. (2) The semiconductor nonvolatile memory device according to claim 1, wherein the first insulating film in the electron injection or extraction region has a partially thin tunnel region. (3) The electron injection or extraction is performed using at least a diffusion layer formed in the semiconductor substrate under the tunnel region and having a conductivity type opposite to that of the substrate, and a second gate electrode. 3. The semiconductor nonvolatile memory device according to claim 2. (4) The readout area is an LDD (Lightly Do
4. The semiconductor nonvolatile memory device according to claim 1, wherein the semiconductor nonvolatile memory device comprises a transistor having a ped drain structure.