JPH06204487A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a semiconductor storage device of a single layer conductive film structure which allows the reduction of cell area. CONSTITUTION:The title storage device consists of a p-type silicon substrate 10; an n-type diffusion layer 11-1 formed in the substrate 10; n-type diffusion layer 12 formed in the substrate 10, isolated from the n-type diffusion layer 11-1; a channel region 13 placed between the n-type diffusion layer 11-1 and n-type diffusion layer 12; and floating gate 15 which is formed on the channel region 13, n-type diffusion layer 11-1, and n-type diffusion layer 12 with an insulating layer 14 in-between. The n-type diffusion layer 11-1 is electrically connected with the floating gate 15 by capacitive coupling. With the structure mentioned above, a region to be connected with a floating gate 15 by capacitive coupling, is in contact with a channel region 13, and thus it is unnecessary to form a field oxide film to isolate a region to be connected with the floating gate 15 by capacitive coupling, that is, control gate, from the channel region 13. This results in the reduced area of cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which data can be electrically written or written.

[0002]

2. Description of the Related Art FIG. 4 shows "A novel integration technol".
ogy of EEPROM embeded CMOS LOGICVLSI suitable for
ASIC applications "M. Takebuchi et al. IEEE CICC '9
2 EEPROM disclosed in Proceedings May, 1992
It is the pattern top view and sectional drawing of a cell. Figure 4 (a)
Is a plan view of the pattern, and FIG. 4 (b) is A1 in FIG. 4 (a).
It is a sectional view taken along the line A2.

The cell shown in FIGS. 4 (a) and 4 (b) is called a single-layer conductive film structure, and is characterized by a diffusion layer A formed in a substrate and a floating gate (FLOATING GATE). The diffusion layer A is connected by capacitive coupling to control the control gate.
E) is to function. The operation of the cell shown in FIGS. 4A and 4B will be described. Floating gate
The charge injection to (FLOATING GATE) is performed as follows.

High voltage on diffusion layer A, 0 on diffusion layers B and C
Apply V. The floating gate is set by such potential setting.
The potential of (FLOATING GATE) rises due to capacitive coupling with the diffusion layer A, and a high electric field is applied to the thin oxide film D formed in the tunnel window (TUNNEL WINDOW). A tunnel current flows from the floating gate (FLOATING GATE) to the diffusion layer C. This makes the floating gate
Electrons are injected into the FLOATING GATE. Floating Gate (F
Extraction of electric charge from the LOATING GATE) is performed as follows.

0 V is applied to the diffusion layer A, a high voltage is applied to the diffusion layer C, and the diffusion layer B is opened. With such a potential setting, a high electric field is applied to the thin oxide film D, and a tunnel current flows from the diffusion layer C to the floating gate (FLOATING GATE) through the thin oxide film D. This allows the floating gate (FLO
ATING GATE) The electrons inside are pulled out. Reading of data is performed as follows.

0V for diffusion layers A and C, 5V for diffusion layer B
Is applied. With such a potential setting, the floating gate is
When electrons are accumulated in the (FLOATING GATE), no current flows in the channel E, and the floating gate (FLOATING GA
When the electrons in TE) are deficient, a current flows from the diffusion layer B to the diffusion layer C via the channel E. In this way, the data of 1 and 0 is stored depending on whether or not the current flows from the diffusion layer B to the diffusion layer C.

[0007]

However, as shown in FIG.
The cell having the single-layer conductive film structure as shown in (a) and (b) has the following drawbacks.

Diffusion layer A, that is, control gate
Is separated from the active region by the field oxide film F and separated from the channel E. The area of the field oxide film F and the control gate (CONTR
When combined with the area of the OL GATE), the field oxide film F and the control gate (CONTROL GATE) occupy almost half of the area of the memory transistor (MEMORY TRANSISTOR) as shown in FIG.

That is, in the case of a cell having a single-layer conductive film structure, compared to a cell having a double-layer conductive film structure in which a control gate is superposed on a floating gate, almost a control gate is formed in the substrate. The cell area increases by the amount corresponding to the above.

The width of the field oxide film F cannot be easily narrowed due to the inversion of the conductivity type of the substrate under the field oxide film F and the balance with the breakdown voltage. In addition, the control gate
The area of the control gate is also floating gate (FLOATING GATE)
It cannot be easily reduced in order to satisfy sufficient capacitive coupling with. Furthermore, it is necessary to consider the pattern layout. As described above, the cell having the single-layer conductive film structure has an unavoidable problem of increasing the cell area.

In order to solve this problem, it is necessary to drastically modify the cell structure such as radically changing it. Therefore, an object of the present invention is to provide a semiconductor memory device having a single-layer conductive film structure having a structure capable of reducing the cell area.

[0012]

A semiconductor memory device according to the present invention includes a first conductivity type semiconductor substrate, a second conductivity type first semiconductor region formed in the substrate, and a first conductivity type semiconductor substrate.
Second semiconductor region separated from the semiconductor region, a channel region set between the first semiconductor region and the second semiconductor region, the channel region, the first semiconductor region, and the second semiconductor region. And a charge storage layer in an electrically floating state formed via an insulating layer over each of the semiconductor regions, and the first semiconductor region is electrically connected to the charge storage layer by capacitive coupling. There is.

[0013]

According to the above semiconductor memory device, the first semiconductor region is electrically connected to the charge storage layer by capacitive coupling, and the region to be capacitively coupled to the charge storage layer is in contact with the channel region. Therefore, it is not necessary to form a region to be capacitively coupled with the charge storage layer, that is, an isolation region for separating the control gate and the channel region, such as a field oxide film, unlike the conventional memory device. , The cell area can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. In this description, the same parts are denoted by the same reference symbols throughout the drawings, and redundant description will be avoided. FIG. 1 is a view showing a semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a pattern plan view,
(B) figure is sectional drawing which follows the bb line in (a) figure.

As shown in FIGS. 1A and 1B, P
In the type silicon substrate 10, an N type diffusion layer 11-1 and an N type diffusion layer 12 separated from the N type diffusion layer 11-1 are formed. The N-type diffusion layer 11-1 is the source of the memory transistor.
It functions as a gate / control gate, and the N-type diffusion layer 12 functions as the drain of the memory transistor. N-type diffusion layer 11
A channel region 13 of the storage transistor is set between -1 and the N-type diffusion layer 12. A floating gate 15 in an electrically floating state is formed over the channel region 13, the N-type diffusion layer 11-1 and the N-type diffusion layer 12 via the silicon oxide film 14. The film thickness of the silicon oxide film 14 is about 10 nm. The N-type diffusion layer 11-1 is a floating gate.
It is electrically connected to the port 15 by capacitive coupling. Floating game
The overlap amount between the gate 15 and the N-type diffusion layer 11-1 is set larger than the overlap amount between the floating gate 15 and the N-type diffusion layer 12. As a result, in this embodiment, the capacitance of the capacitor generated between the floating gate 15 and the N type diffusion layer 11-1 is larger than the capacitance of the capacitor generated between the floating gate 15 and the N type diffusion layer 12. Be made bigger. Therefore, the potential of the N-type diffusion layer 11-1 is floating during the electron injection.
Can be easily transmitted to the chamber 15 and the injection efficiency can be improved. In addition, the capacity coupling ratio between the N-type diffusion layer 12 and the floating gate 15 can be increased during electron withdrawal. Further, in the substrate 10, an N-type diffusion layer 16 separated from the N-type diffusion layer 12 is formed. The N-type diffusion layer 16 functions as the drain of the selection transistor. N-type diffusion layer 12
A channel region 17 of the select transistor is set between the N-type diffusion layer 16 and the N-type diffusion layer 16. A selective gate 19 is formed on the channel region 17 via a silicon oxide film 18. The film thickness of the silicon oxide film 18 is about 40 nm. The selection transistor is used when the storage transistor is turned on when electrons in the floating gate 15 are deficient and an inversion layer is formed in the channel region 13 and the voltage of the N-type diffusion layer 11-1 is 0V. For example, when the memory transistor is a depletion type, it is provided to prevent half-selection or erroneous reading. The entire surface of the substrate 10 is covered with a melt film 20 made of PSG, BPSG or the like. The melt film 20 functions as an interlayer insulating film. A contact hole 21 communicating with the N-type diffusion layer 16 is formed in the melt film 20. N is formed on the melt film 20 through a contact hole 21.
A metal wiring 22 electrically connected to the mold diffusion layer 16 is formed.

Only one cell is shown in FIGS. 1 (a) and 1 (b). In an actual semiconductor memory device, the cells are arranged in a matrix in the substrate 10, and the active element regions of the cells are separated by the field oxide film 23-1. Reference numeral 11-2 is the source of cells adjacent in the column direction.
It is an N-type diffusion layer that functions as a gate / control gate. The N-type diffusion layer 11-1 and the N-type diffusion layer 11-2 are separated from each other by the field oxide film 23-2. Further, the N type diffusion layers 11-1 and 11-2 are connected by 8 bits in the row direction, and are connected to the decoder through contact holes (not shown) at their ends. Next, the operation of the cell shown in FIGS. 1A and 1B will be described. The injection of electrons (erasing operation) into the floating gate 15 is performed as follows.

A high voltage of VPP level (about 16 V) is applied to each of the N type diffusion layer 11-1 and the selection gate 19 to turn on the selection transistor, and 1 V of the N type diffusion layer 16 is changed to N.
This is transmitted to the type diffusion layer 12, and the N type diffusion layer 12 is set to about 1V. The reason why the N-type diffusion layer 12 is set to about 1V is to prevent the inversion layer from being formed in the channel region 13. The floating gate 15 raises its potential due to capacitive coupling with the diffusion layer 11-1, and the N-type diffusion layer 12 and the floating gate 15
A high electric field is applied to the silicon oxide film 24 between the and. As a result, a floating gate is formed through the silicon oxide film 24.
A tunnel current flows from the gate 15 to the N-type diffusion layer 12. As a result, electrons are injected into the floating gate 15. The extraction (writing operation) of electrons from the floating gate 15 is
Do the following:

A voltage of 1 V and a selective gate are applied to the N-type diffusion layer 11-1.
A high voltage of VPP level (about 16 V) is applied to the gate 19, the selection transistor is turned on, the VPP level of the N-type diffusion layer 16 is transmitted to the N-type diffusion layer 12, and the N-type diffusion layer 12 is set to about VPP level (about 16V). As a result, the potential difference between the N-type diffusion layer 12 and the N-type diffusion layer 11-1 becomes about 15 V (note that the substrate bias effect of the selective gate 19 is not taken into consideration). The reason why the N-type diffusion layer 11-1 is set to 1V is to prevent the inversion layer from being formed in the channel region 13. With such a potential setting, a high electric field is applied to the silicon oxide film 24, and a tunnel current flows from the N-type diffusion layer 12 to the floating gate 15 via the silicon oxide film 14. As a result, the electrons in the floating gate 15 are extracted. At this time, the N-type diffusion layer 11-1 is not opened, but the potential of the floating gate 15 is lowered to a low potential by the N-type diffusion layer 11-1.

By the way, it is desired that the memory transistor is of a depletion type. This is because it is intended to increase the read current. Here, when the memory transistor is a depletion type, the following concerns occur.

It is assumed that the memory transistor is a depletion type, and the N-type diffusion layer 11-1 is set to the same potential as that at the time of reading data (for example, 0 V) to extract electrons. At this time, in a cell in which electrons are deficient and an inversion layer is generated in the channel region 13, if the N-type diffusion layer 11-1 is set to the same potential as that at the time of data reading, the N-type diffusion layer 1
A current flows from 2 to the N-type diffusion layer 11-1 through the inversion layer,
The potential of the N-type diffusion layer 12 drops from the VPP level (in the worst case, the potential of the N-type diffusion layer 12 becomes the same as that of the N-type diffusion layer 11-1. For example, 0V). This phenomenon is called VPP down. When VPP down occurs, the electron extraction efficiency deteriorates significantly, and the potential of the metal wiring 22 connected to this cell also drops. There are a plurality of cells on the substrate, and among these cells, there are cells with good extraction efficiency and cells with poor extraction efficiency due to factors such as processing variations. In a cell with a high extraction efficiency, the VPP down occurs earlier and the potential of the metal wiring 22 also drops, so that electrons are not sufficiently extracted in other cells connected to the metal wiring 22. That is, the state of the cell cannot be set to the depletion state in which the inversion layer is formed in the channel region 13, and there occurs a cell in which the extraction is completed in the enhanced state in which the inversion layer is not formed. In this case, when the data is read from the cell, the current does not flow in the channel region 13, so that the wrong data is taken out.

In order to prevent this problem, the potential of the N-type diffusion layer 11-1 is such that the inversion layer is not formed in the channel region 13 when the storage transistor is the depletion type when the electrons are extracted. It is desirable to set the potential. In the above embodiment, the N-type diffusion layer 11 at the time of extraction is used.
The potential of -1 is set to 1 V, and the potential of the N-type diffusion layer 11-1 at the time of reading is set to 0 V, which will be described later, to prevent the inversion layer from being formed in the channel region 13. . If the potential of the N type diffusion layer 11-1 is set to 1V,
The potential difference between the N-type diffusion layer 12 and the N-type diffusion layer 11-1 is 15V.
Since the voltage drops below the VPP level (about 16V), the extraction efficiency deteriorates a little, but it is useful in that the reliability of the memory device can be made higher than the writing of incorrect data. is there. Also, the threshold voltage of the storage transistor can be set to about -1V because the voltage of the N-type diffusion layer 11-1 brings about the substrate bias effect, and the potential of the N-type diffusion layer 11-1 is set to 1V. As a result, it is possible to obtain a depletion type memory transistor. Further, the potential setting of 1V can be variously changed depending on the type of device, and in the case of the N-channel type, it may be at least a positive potential with respect to 0V. The data read operation is performed as follows.

0V, selection gate 19 is applied to the N-type diffusion layer 11-1.
Then, the Vcc level (about 5V) is applied to turn on the selection transistor. Thereby, 1V of the N-type diffusion layer 16 is transmitted to the N-type diffusion layer 12, and the N-type diffusion layer 12 is set to about 1V.
With such a potential setting, when electrons are accumulated in the floating gate 15, the inversion layer is not formed in the channel region 13 and the electrons in the floating gate 15 are deficient. In this case, an inversion layer is formed in the channel region 13, and a current flows from the N-type diffusion layer 12 to the N-type diffusion layer 11-1 via this inversion layer. In this way, the data of 1,0 is determined depending on whether or not the current flows from the N-type diffusion layer 12 to the N-type diffusion layer 11-1. 2A and 2B are views showing a semiconductor device according to a second embodiment of the present invention. FIG. 2A is a plan plan view, and FIG. 2B is along the line bb in FIG. 2A. FIG.

The semiconductor device according to the second embodiment has an N-type diffusion layer 11 functioning as a control gate and a source.
The field oxide film 23-2 for separating cells adjacent to each other in the column direction is omitted.

As shown in FIGS. 2A and 2B, the N-type diffusion layer 11-11 functioning as the control gate and source of the memory transistor is connected via the current path of the second select transistor. Connected to the N-type diffusion layer 11-12.
The second select transistor includes a channel region 24 between the N-type diffusion layer 11-11 and the N-type diffusion layer 11-12, and a gate insulating layer formed on the channel region 24 and made of, for example, a silicon oxide film. It is composed of a film 25 and a gate 26 formed on the gate insulating film. When the second selection transistor is turned on, the voltage of the N-type diffusion layer 11-12 is changed to the N-type diffusion layer 11-11.
And the voltage is not transmitted when it is off.

By providing the second selection transistor as described above, the N-type diffusion layer 11 functioning as a control gate and a source is separated in the column direction.
The field oxide film can be omitted, and the effect of reducing the cell area is further promoted. Next, the operation of the cell shown in FIGS. 2A and 2B will be described. The injection of electrons (erasing operation) into the floating gate 15 is performed as follows.

N-type diffusion layer 11-12 and selective gate 19
A high voltage of VPP level (about 16V) is applied to. As a result, the first selection transistor is turned on, and the N-type diffusion layer 1
1V of 6 is transmitted to the N-type diffusion layer 12 and the N-type diffusion layer 12
Is set to about 1V. Further, the high voltage of VPP level (about 16V) applied to the N-type diffusion layer 11-12 turns on the second transistor. As a result, the second select transistor is turned on, the VPP level of the N-type diffusion layer 11-12 is transmitted to the N-type diffusion layer 11-11, and the N-type diffusion layer 11-11 is set to about VPP level. The voltage level of the N-type diffusion layer 11-11 is slightly lower than that of the N-type diffusion layer 11-12, but the potential of the floating gate 15 rises due to capacitive coupling with the diffusion layer 11-11. A high electric field is applied to the silicon oxide film 24 between the N type diffusion layer 12 and the floating gate 15. As a result, a tunnel current flows from the floating gate 15 to the N type diffusion layer 12 through the silicon oxide film 24. As a result, electrons are injected into the floating gate 15. The electron extraction (writing operation) from the floating gate 15 is performed as follows.

The VPP level (about 16
V), a voltage of Vcc level (about 5 V) is applied to the selection gate 26 to turn on the first and second selection transistors. A voltage of 1V is applied to the N type diffusion layer 11-12. When the first selection transistor is turned on, the VPP level of the N-type diffusion layer 16 is transmitted to the N-type diffusion layer 12, and the N-type diffusion layer 12 is set to about VPP level (about 16V). Further, when the second selection transistor is turned on, 1V of the N-type diffusion layer 11-12 changes to 1V.
1-11, the N-type diffusion layer 11-11 is set to about 1V. The reason why the N-type diffusion layers 11-11 and 11-12 are not set to 0V is the same as in the first embodiment. With such a potential setting, a high electric field is applied to the silicon oxide film 24, a tunnel current flows from the N-type diffusion layer 12 to the floating gate 15 through the silicon oxide film 14, and the floating gate 15 has a tunnel current. The electron is pulled out. The data read operation is performed as follows.

0V, selective gate 1 to N type diffusion layer 11-12
A Vcc level (about 5 V) is applied to each of 9 and 26 to turn on the first and second selection transistors. As a result, the N-type diffusion layer 12 is about 1 V, and the N-type diffusion layer 1 is
1-11 is set to about 0V. At this time, the N-type diffusion layer 12
Depending on whether or not a current flows from the N-type diffusion layer 11-11.
Judge the data of 1,0. FIG. 3 is a diagram showing a semiconductor device according to a modification of the present invention, and FIG. 3 (a) is a pattern.
FIG. 2B is a sectional view taken along the line bb in FIG.

The semiconductor device according to the modification is one in which the insulating film 14 provided between the substrate 10 and the floating gate 15 has two kinds of film thickness. The insulating film 14 shown in FIG. 3B includes the N-type diffusion layer 11-1 and the N-type diffusion layer 12
The upper portion has a small film thickness, and the channel region 13 has a large film thickness. The thin film thickness is about 10 nm, and the thick film thickness is about 40 nm, which is almost the same as the gate insulating film 18 of the select transistor.

According to the above modification, the film thickness on the N-type diffusion layer 11-1 and the N-type diffusion layer 12 is made smaller than that on the channel region 13, so that the floating gate 15 It is possible to avoid the concern that the insulating film 14 is deteriorated due to electron tunneling between the valence band and the conduction band, which occurs near the edge of the N-type diffusion layer 12 when the electrons are extracted.

Further, the film thickness of the insulating film 14 on the N-type diffusion layer 11-1 may be further reduced to set three kinds of film thickness in total. By doing so, it is possible to improve the capacitive coupling ratio. Such modified examples can be commonly applied to the semiconductor devices according to the first and second embodiments. The present invention is not limited to the above embodiment, and various modifications such as potential setting during erase / write / read operations can be made without departing from the spirit of the invention.

[0032]

As described above, according to the present invention, it is possible to provide a semiconductor memory device having a single-layer conductive film structure having a structure capable of reducing the cell area.

[Brief description of drawings]

FIG. 1 is a diagram showing a semiconductor device according to a first embodiment of the present invention, FIG. 1 (a) is a pattern plan view,
(B) figure is sectional drawing which follows the bb line in (a) figure.

FIG. 2 is a diagram showing a semiconductor device according to a second embodiment of the present invention, FIG. 2 (a) is a pattern plan view,
(B) figure is sectional drawing which follows the bb line in (a) figure.

3A and 3B are views showing a semiconductor device according to a modification of the present invention, wherein FIG. 3A is a plan plan view, and FIG. 3B is along line bb in FIG. 3A. Sectional view.

FIG. 4 is a diagram showing a conventional semiconductor device,
(A) is a pattern plan view, (b) is a pattern in (a).
-A sectional view taken along the line A2.

[Explanation of symbols]

10 ... P-type silicon substrate, 11-1, 11-2, 11-11,
11-12 ... N-type diffusion layer (region functioning as control gate and source), 12 ... N-type diffusion layer, 13 ... Channel region, 14 ... Silicon oxide film, 15 ... Floating gate, 16 ...
N-type diffusion layer, 17 ... Channel region, 19 ... Selection gate,
23, 23-1, 23-2 ... Field oxide film, 26 ... Selective gate.

Claims (5)

[Claims] 1. A first-conductivity-type semiconductor substrate, a second-conductivity-type first semiconductor region formed in the substrate, and a first-conductivity-type semiconductor region spaced apart from the first semiconductor region in the substrate. A second semiconductor region, a channel region set between the first semiconductor region and the second semiconductor region, on the channel region, on the first semiconductor region, and on the second semiconductor region A charge storage layer in an electrically floating state formed via an insulating layer over each of the upper portions, and the first semiconductor region is electrically connected to the charge storage layer by capacitive coupling. Semiconductor memory device. 2. The semiconductor according to claim 1, wherein the thickness of at least the insulating layer on the first semiconductor region and the second semiconductor region is smaller than the thickness on the substrate. Storage device. 3. The injection and extraction of charges to and from the charge storage layer are performed via the insulating layer between the charge storage layer and the second semiconductor region.
Alternatively, the semiconductor memory device according to claim 2. 4. The injection of charges into the charge storage layer is performed by applying a first potential to the first semiconductor region to raise the potential of the charge storage layer by capacitive coupling, and to the second semiconductor region. By applying a second potential lower than the first potential, a current is caused to flow from the charge storage layer to the second semiconductor region through the insulating layer. From the second semiconductor region by applying a third potential to the first semiconductor region and applying a fourth potential higher than the third potential to the second semiconductor region. 4. The semiconductor memory device according to claim 1, wherein a current is supplied to the charge storage layer through the insulating layer. 5. The capacitance of the capacitor generated between the charge storage layer and the first semiconductor region is equal to that of the charge storage layer and the second semiconductor region.
5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a capacitance larger than that of a capacitor formed between the semiconductor memory device and the semiconductor region.