JP4748002B2 - Nonvolatile semiconductor memory device - Google Patents

Description

  The present invention relates to a nonvolatile semiconductor memory device.

  In recent years, in a nonvolatile semiconductor memory device, a hot hole method for erasing data by injecting hot holes accompanying an avalanche breakdown into a floating gate electrode has attracted attention because data can be erased at a low voltage. Yes.

  For example, in Patent Document 1, in a nonvolatile semiconductor memory device having a stacked gate structure, when erasing data, the drain is opened (floating potential), the substrate is grounded, and a positive voltage (for example, 2 V) is applied to the control gate. In addition, a voltage higher than the source-substrate avalanche breakdown voltage (for example, 9 V) is applied to the source to generate an avalanche breakdown between the source and substrate, and hot carriers associated therewith are injected into the floating gate. A method for erasing data is shown. According to this, the threshold voltage after erasing self-converges to a desired constant value without depending on the initial threshold voltage of the transistor (that is, regardless of whether it is in a written state or an unwritten state), thereby preventing excessive erasure. It is supposed to be possible.

In order to solve the problem of over-erasing, for example, Patent Document 2 discloses a split in which a part of a control gate electrode is opposed to a channel region with an insulating film interposed therebetween and is configured as a selection gate of a selection transistor. A non-volatile semiconductor memory device having a gate structure is shown.
Patent No. 2848223 JP 2001-7227 A

  By the way, when the present inventor confirmed the data erasing method shown in Patent Document 1, even if erasing is performed under the same conditions due to variations in manufacturing process and temperature, the threshold voltage after erasing is between a plurality of bits (for each cell). ). One possible cause is that the avalanche breakdown voltage varies and the amount of hot holes to be injected varies because the impurity concentration distribution of the source in which avalanche breakdown occurs and the P-type region surrounding the source varies from bit to bit.

  In the conventional split gate structure nonvolatile semiconductor memory device represented by Patent Document 2, the floating gate electrode for accumulating charges is disposed only on one of the drain and the source in the semiconductor substrate. ing. In this configuration, if not only writing by hot electrons but also erasing by hot holes are performed for low voltage driving, writing / erasing must be performed only by one of the drain and the source where the floating gate electrode is arranged. I must. Therefore, the drain (or source) in which writing / erasing is performed and the insulating film disposed between the vicinity thereof and the floating gate electrode are damaged, and malfunction is likely to occur during writing / reading (it is weak against disturbance). There's a problem.

  SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a nonvolatile semiconductor memory device that can reduce variations in threshold voltage after erasing and reduce malfunctions when performing writing / erasing with hot carriers.

In order to achieve the above object, the invention according to claim 1 is a non-volatile semiconductor in which hot holes are injected into a floating gate electrode to neutralize electrons accumulated in the floating gate electrode and erase data. A storage device, which is formed in a region where a first conductivity type semiconductor substrate and a surface layer portion of a main surface of the semiconductor substrate are spaced apart from each other and diffused with a second conductivity type impurity opposite to the first conductivity type. A control gate electrode and a control gate electrode having a portion disposed on the channel region with an insulating film therebetween so as to face a certain drain and source and a channel region between the drain and source of the semiconductor substrate; An electrically insulated floating gate electrode is provided, and at least a part of a portion of the control gate electrode facing the channel region is configured as a selection gate of the selection transistor . The floating portion of the gate electrode, and the drain or the source of the semiconductor substrate, formed spaced apart from the drain and source in the surface layer portion, a second conductivity type impurity is disposed and on the diffusion region which is diffused In addition, an avalanche breakdown is generated between the diffusion region formed apart from the drain and the source and the semiconductor substrate, and hot holes associated therewith are injected into the floating gate electrode .

  As described above, the nonvolatile semiconductor memory device of the present invention also has a split gate structure in which a part of the control gate electrode is configured as a selection gate of the selection transistor. The variation of the can be reduced. That is, excessive erasure can be reduced or prevented.

  The floating gate electrode is disposed on the drain or source in the semiconductor substrate and on a diffusion region different from the drain and source. Therefore, writing by hot electrons can be performed near the drain (near the source), and erasing by hot holes can be performed near the diffusion region. That is, since writing and erasing can be performed at different locations, damage to the insulating film can be reduced. As a result, malfunctions (write disturb and read disturb) that occur during writing and reading can be reduced or prevented.

  The diffusion region is configured to be electrically independent from the drain and the source (separate terminal). Therefore, in consideration of withstand voltage and the like, the concentration distribution can be different from that of the drain and the source, and a voltage different from that of the drain and the source can be applied.

Hereinafter, reference embodiments and embodiments of the present invention will be described with reference to the drawings. In each of the following reference embodiments and embodiments , channel hot electrons out of two impurity diffusion regions (conductivity types opposite to those of the semiconductor substrate) formed on the surface layer portion of the main surface of the semiconductor substrate are separated from each other. At the time of writing by the method, a side to which a high voltage is applied is a drain, and the other is a source.
( First reference form )
1A and 1B are diagrams showing a schematic configuration of a main part of a nonvolatile semiconductor memory device according to a first reference embodiment . FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along line AA in FIG. (B) is sectional drawing which follows the BB line of (a).

As shown in FIGS. 1A to 1C, the non-volatile semiconductor memory device 100 has an N concentration of about 1 × 10 ²⁰ cm ^{−3 on} the main surface of a P-conductivity type (P) semiconductor substrate 110, for example. A drain 120 and a source 130 which are conductivity type (N +) impurity diffusion regions are formed apart from each other. Therefore, the region 125 sandwiched between the drain 120 and the source 130 in the surface layer portion of the semiconductor substrate 110 functions as the channel region 125 of the nonvolatile semiconductor memory device 100.

Further, in the present embodiment , the drain 120 and the source 130 do not have a symmetric structure, and the source 130 extends from the base 130a and the base 130a constituting the channel region 125 between the drain 120, On a part or in the vicinity thereof, a part of a floating gate electrode 160 to be described later is constituted by an extending part 130b disposed to face each other through an insulating film. The extending portion 130b can be configured to be bent in the vertical direction with respect to the base portion 130a along the longitudinal direction of the channel region 125, for example. That is, in the planar direction of the semiconductor substrate 110, the source 130 can be configured to include a base portion 130a and an extending portion 130b by being T-shaped, L-shaped, or cross-shaped. In this reference embodiment , as shown in FIG. 1A, it is formed in a T shape close to an L shape. Note that a P conductivity type (P) well region (not shown) having a higher concentration than the semiconductor substrate 110 is formed on the main surface of the semiconductor substrate 110, and the drain 120 and the source 130 are formed in the well region. It is good also as a structure.

Around the drain 120 and the source 130 (at least on the opposite sides of the drain 120 and the source 130), the P conductivity type having a higher concentration than the channel region 125 of the semiconductor substrate 110 (for example, the concentration is about 1 × 10 ¹⁸ cm ⁻³ ). (P +) diffusion regions 140 are respectively formed. As described above, when the diffusion region 140 is provided, an avalanche breakdown is likely to occur between the drain 120 and the semiconductor substrate 110, which will be described later. The electrode 160 can be injected. That is, the low-voltage drive nonvolatile semiconductor memory device 100 can be obtained.

  On the main surface of the semiconductor substrate 110, two gate electrodes 160 and 180, for example, a floating gate electrode 160 obtained by introducing impurities into a polycrystalline silicon film and a control gate electrode 180 are disposed.

The floating gate electrode 160 includes a drain facing portion 160a that is biased toward the drain 120 and faces the channel region 125, an extension portion 130b of the source 130 and / or a source facing portion 160b that faces the vicinity thereof, and a drain facing portion 160a. And a connecting part 160c for connecting the source facing part 160b. The drain facing portion 160a is disposed (opposed) on the channel region 125 so as to be biased toward the drain 120 via the first gate insulating film 150a having a thickness of about 10 nm so as to affect the potential of the channel region 125. ing. Accordingly, the potential of the channel region 125 can be changed in accordance with the charge accumulation state of the floating gate electrode 160, for example, to form a channel. In addition, since the drain facing portion 160a is disposed (opposed) on the drain 120 and / or its vicinity, it floats electrons (hot electrons) in a high energy state in the vicinity of the drain 120 during writing, which will be described later. It can be injected into the gate electrode 160. The source facing portion 160b is a portion that extends beyond the control gate electrode 180 to the source 130 side, and is disposed on the extending portion 130b of the source 130 and / or its vicinity through the first gate insulating film 150a. (Opposed). Therefore, at the time of erasing described later, holes (hot holes) in a high energy state generated in the vicinity of the extended portion 130 b of the source 130 can be injected into the floating gate electrode 160. The connecting portion 160c connects the drain facing portion 160a and the source facing portion 160b. Note that the floating gate electrode 160 according to the present embodiment is L-shaped so as to straddle the control gate electrode 180 (selection gate portion 180a described later) in the planar direction of the semiconductor substrate 110, as shown in FIG. A source facing portion 160b is formed at one end of the L shape, and a drain facing portion 160a is formed near the other end.

  A part of the control gate electrode 180 is stacked on the floating gate electrode 160 via the intermediate film 170. The intermediate film 170 electrically insulates the floating gate electrode 160 and the control gate electrode 180. For example, an insulating film (so-called ONO film) having a three-layer structure of oxide film-nitride film-oxide film is employed. Can do. The portion disposed on (and in the vicinity of) the floating gate electrode 160 corresponds to the gate electrode of the memory cell transistor. Further, the control gate electrode 180 has a selection gate portion 180 a that faces the channel region 125. The selection gate portion 180a is disposed (opposed) on the channel region 125 where the drain facing portion 160a of the floating gate electrode 160 is not disposed via the second gate insulating film 150b thicker than the first gate insulating film 150a. Yes. In other words, the selection gate portion 180a is arranged in a biased manner toward the source 130 in the channel region 125. Therefore, in the vicinity of the source 130 of the channel region 125, the control gate electrode 180 can independently perform a current control function with respect to the channel region 125.

  Reference numerals 190a and 190b shown in FIG. 1A are contacts of the drain 120 and the source 130, respectively. Reference numeral 200 shown in FIG. 1C denotes a LOCOS oxide film (field insulating film) that partitions the cell region.

As described above, the nonvolatile semiconductor memory device 100 according to this embodiment has a split gate structure in which one control gate electrode 180 also functions as a gate electrode of a selection transistor. Therefore, by appropriately setting the positional relationship between the floating gate electrode 160 and the control gate electrode 180 with respect to the channel region 125, it is possible to stably exhibit the effect of reducing threshold variation described later.

  The nonvolatile semiconductor memory device 100 having such a configuration can be formed by using a known split gate structure manufacturing method. As an example, the surface of a P-conductivity type (P) semiconductor substrate 110 is thermally oxidized to form a silicon oxide film to be the first gate insulating film 150a, and the floating gate electrode 160 is formed on the silicon oxide film by a CVD method. A polycrystalline silicon layer (first poly) is formed. Then, after an ONO film to be the intermediate film 170 is formed on the polycrystalline silicon layer, selective etching is performed to form the first gate insulating film 150a, the floating gate electrode 160, and the intermediate film 170. Next, the surface of the semiconductor substrate 110 is thermally oxidized to form a silicon oxide film to be the second gate insulating film 150b, and a polycrystalline silicon layer (second poly-silicon layer) to be the control gate electrode 160 is formed on the silicon oxide film by a CVD method. ). Then, the second gate insulating film 150b and the control gate electrode 180 are formed by selective etching. Thereafter, a P-conductivity type impurity such as boron and an N-conductivity type impurity such as phosphorus are implanted into the semiconductor substrate 110 in a self-aligning manner using the floating gate electrode 160 and the control gate electrode 180 as a mask. 130 and a diffusion region 140 are formed. For example, the nonvolatile semiconductor memory device 100 can be formed in this way.

Next, the write and erase operation of the nonvolatile semiconductor memory device 100 according to this preferred embodiment will be described with reference to FIG. 2A and 2B are diagrams for explaining a write / erase operation of the nonvolatile semiconductor memory device 100. FIG. 2A shows writing and FIG. 2B shows erasing.

Data is written by a channel hot electron (CHE) method which is a well-known method. Specifically, one of the drain 120 and the source 130 (source 130 in this embodiment ) is set to the same potential as the substrate potential, and the other of the drain 120 and the source 130 (drain 120 in this embodiment ) is set to the substrate potential. In the state where a positive voltage (preferably 9 V or less) is applied, a positive voltage (preferably 12 V or less) is applied to the control gate electrode 180. In this reference embodiment , as shown in FIG. 2A, the source 130 and the semiconductor substrate 110 are grounded, and 5 V is applied to the drain 120 and 8 V is applied to the control gate electrode 180.

  Under the above conditions, as shown in FIG. 2A, electrons supplied from the base portion 130a of the source 130 move at a high speed in the channel region 125 toward the drain 120 facing the base portion 130a (that is, the channel current is reduced). Flow) Electrons (hot electrons) in a high energy state in the vicinity of the drain 120 jump over the first gate insulating film 150a and are injected into the drain facing portion 160a of the floating gate electrode 160. That is, data is written.

Note that, in the channel region 125, the floating gate electrode 160 (drain facing portion 160a) is arranged to be biased toward the drain 120 (a configuration in which charges can be accumulated near the drain 120). Therefore, the electrons injected into the floating gate electrode 160 can be only hot electrons that are sufficiently accelerated in the vicinity of the drain 120. As a result, erroneous writing can be reduced or prevented.

Data is erased by a hot hole (HH) method which is a well-known method. Specifically, a voltage that is the same as the substrate potential or a negative voltage with respect to the substrate potential is applied to the control gate electrode 180, and the drain 120 and the source 130 to which the high voltage is applied at the time of writing (in this embodiment ) Is a positive voltage that causes an avalanche breakdown with respect to the substrate potential relative to the substrate potential on the side to which the high voltage is not applied at the time of writing (source 130 in the present embodiment ). For example, about 5 to 12 V) is applied. In the present embodiment , as shown in FIG. 2B, the semiconductor substrate 110 is grounded, the drain 120 is applied with a floating potential, the source 130 is applied with 8V, and the control gate electrode 180 is applied with −2V.

  Under the above conditions, as shown in FIG. 2B, an avalanche breakdown occurs between the extended portion 130b of the source 130 and the semiconductor substrate 110, so that an avalanche current flows. A hole in a high energy state (hot hole) generated near the portion 130 b is injected into the source facing portion 160 b of the floating gate electrode 160. Thereby, in the data writing, the electrons injected into the floating gate electrode 160 are neutralized and the data is erased.

  As described above, the selection gate portion 180a of the control gate electrode 180 can exert a current control function on the channel region 125 independently of the floating gate electrode 160 (drain facing portion 160a). For example, even if the amount of hot holes injected into the floating gate electrode 160 varies among the cells, the threshold voltage of the nonvolatile semiconductor memory device 100 does not fall below the threshold voltage of the selection transistor formed by the selection gate unit 180a. That is, the on / off state of the nonvolatile semiconductor memory device 100 can be controlled by the selection transistor formed by the selection gate portion 180a, and variations in threshold voltage can be reduced.

As described above, since the nonvolatile semiconductor memory device 100 according to this embodiment has a split gate structure, the variation of the threshold voltage after erasure is caused by the effect of the selection transistor by the selection gate portion 180a of the control gate electrode 180. Can be small. That is, excessive erasure can be reduced or prevented.

  In addition, the source 130 includes an extended portion 130b extending from the base portion 130a facing the drain 120 (that is, forming the channel region 125), and the floating gate electrode 160 is biased toward the drain 120 side. It has a drain facing portion 160a facing the region 125, and a source facing portion 160b facing the extended portion 130b of the source 130 and / or its vicinity. Therefore, writing by hot electrons can be performed in the vicinity of the drain 120, and erasing by hot holes can be performed in the vicinity of the extending portion 130 b of the source 130. That is, writing and erasing can be performed separately for the drain 120 and the source 130 (at different locations). Accordingly, damage to the first gate insulating film 150a and the second gate insulating film 150b can be reduced, and malfunctions (write disturb and read disturb) occurring at the time of writing / reading can be reduced or prevented.

In the present embodiment , an example in which the diffusion region 140 is formed around the drain 120 and the source 130 is shown. However, a configuration without the diffusion region 140 may be used. Further, in order to easily generate an avalanche breakdown between the semiconductor substrate 110 and the diffusion region 140 only around the side of the drain 120 and the source 130 where the avalanche breakdown occurs (the source 130 in this embodiment ). It is good also as a structure in which is formed.

( Second reference form )
Next, the 2nd reference form of the present invention is explained based on Drawing 3 (a)-(c). Figure 3 is a diagram showing a schematic configuration of a main portion of a nonvolatile semiconductor memory device 100 according to this preferred embodiment, (a) is a plan view, (b) is a sectional view taken along the line C-C in (a) (C) is sectional drawing which follows the DD line | wire of (a).

Since the non-volatile semiconductor memory device 100 according to the second reference embodiment is in common with the non-volatile semiconductor memory device 100 shown in the first reference embodiment , detailed description of the common parts will be omitted below, and different parts will be emphasized. I will explain it.

In the first reference embodiment , the floating gate electrode 160 is formed in an L shape in the planar direction of the semiconductor substrate 110, the source facing portion 160b is configured at one end of the L shape, and the drain facing portion 160a is disposed near the other end. An example configured is shown. On the other hand, in the present embodiment , as shown in FIGS. 3A to 3C, the floating gate electrode 160 is formed in an annular shape in the planar direction of the semiconductor substrate 110, and a part of the control gate electrode 180 is formed. The floating gate electrode 160 is disposed in the inner peripheral hole portion 161 and is opposed to the channel region 125.

Specifically, in the planar direction of the semiconductor substrate 110, the drain 120 and the source 130 have a line-symmetric structure with respect to the center line of the channel region 125 (a line perpendicular to the longitudinal direction of the channel region 125). The floating gate electrode 160 is formed in an annular shape having an inner periphery and an outer periphery that are the same rectangle, and is arranged symmetrically with respect to the center line. Further, a drain facing portion 160a that is biased toward the drain 120 and faces the channel region 125 is formed in a part of the annular portion, and the channel region 125 is biased toward the source 130 with the inner peripheral hole portion 161 (center line) interposed therebetween. Opposing source facing portions 160d are configured. The source facing portion 160d plays the same role as the source facing portion 160b described in the first reference embodiment . In addition, the control gate electrode 180 is also arranged symmetrically with respect to the center line. A portion stacked on the floating gate electrode 160 via the intermediate film 170 corresponds to the gate electrode of the memory cell transistor. In addition, a portion that is disposed in the inner peripheral hole portion 161 of the floating gate electrode 160 and faces the channel region 125 through the second gate insulating film 150b serves as a selection gate portion 180a of the selection transistor.

Such a nonvolatile semiconductor memory device 100 can also be formed by using a well-known split gate structure manufacturing method as shown in the first reference embodiment , for example. Also, data writing / erasing can be performed by performing the same treatment as in the example shown in the first reference embodiment . In the present embodiment , since the nonvolatile semiconductor memory device 100 is symmetrical with respect to the center line, the current value is equal even when a high voltage is applied to either the drain 120 or the source 130 in data reading. can do.

As described above, since the nonvolatile semiconductor memory device 100 according to the present embodiment also has a split gate structure, the variation of the threshold voltage after erasure is caused by the effect of the selection transistor by the selection gate portion 180a of the control gate electrode 180. Can be small. That is, excessive erasure can be reduced or prevented.

Further, by making the floating gate electrode 160 annular, the floating gate electrode 160 is disposed on the drain 120 and / or its vicinity and the source 130 and / or its vicinity, and in the inner peripheral hole portion 161 of the floating gate electrode 160. A part of the control gate electrode 180 is arranged to form the selection gate portion 180a. Therefore, writing by hot electrons can be performed near the drain 120 and erasing by hot holes can be performed near the source 130. In other words, writing and erasing can be performed separately for the drain 120 and the source 130 (separate portions can be performed. Thus, damage to the first gate insulating film 150a and the second gate insulating film 150b can be reduced, and writing / erasing can be performed. Malfunctions (write disturb and read disturb) that occur at the time of reading can be reduced or prevented, and the structure of the drain 120 and the source 130 that performs erasing by hot holes (the source 130 in the present embodiment ) is This can be simplified compared to the configuration shown in the first reference embodiment , that is, the area per cell can be reduced.

Further, since the selection gate portion 180a of the control gate electrode 180 is not disposed on the drain 120 and / or its vicinity or the source 130 and / or its vicinity in the channel region 125, a high voltage is applied to the control gate electrode 180. Is applied, the high electric field is not applied to the second gate insulating film 150b between the channel region 125 and the channel region 125. Therefore, the second gate insulating film 150b can be designed thinner than the configuration shown in the first reference embodiment .

In the present embodiment , an example in which the nonvolatile semiconductor memory device 100 is configured symmetrically with respect to the center line is shown. However, at least the floating gate electrode 160 is formed in an annular shape, and a part of the control gate electrode 180 (selection gate portion 180a) is disposed in the inner peripheral hole portion 161 of the floating gate electrode 160 and is disposed to face the channel region 125. Any configuration is acceptable. Preferably, the floating gate electrode 160 is arranged on the drain 120 and the source 130 which are arranged symmetrically. More preferably, the nonvolatile semiconductor memory device 100 is symmetric with respect to the center line.

( 3rd reference form )
Next, the 3rd reference form of the present invention is explained based on Drawing 4 (a) and (b). Figure 4 is a diagram showing a schematic configuration of a main portion of a nonvolatile semiconductor memory device 100 according to this preferred embodiment, (a) is a plan view, (b) is a sectional view taken along the line E-E of (a) It is.

Since the nonvolatile semiconductor memory device 100 according to the third reference embodiment is common in common with the nonvolatile semiconductor memory device 100 shown in the first and second reference embodiments , detailed description of the common parts will be omitted below and different. The part will be explained with emphasis.

In the first and second reference embodiments , the configuration in which the control gate electrode 180 is stacked on the floating gate electrode 160 via the intermediate film 170 in the memory cell transistor region is shown. On the other hand, in the present embodiment , as shown in FIGS. 4A and 4B, the floating gate electrode 160 is stacked on the control gate electrode 180 via the intermediate film 170 in the memory cell transistor region. It is characterized by an arrangement point (so-called inverted structure of the first poly and the second poly).

Specifically, in the planar direction of the semiconductor substrate 110, the drain 120 and the source 130 have a line-symmetric structure with respect to the center line of the channel region 125 (a line perpendicular to the longitudinal direction of the channel region 125). The control gate electrode 180 has a planar rectangular shape and is disposed (opposed) on the semiconductor substrate 110 via the second gate insulating film 150b so as to be symmetrical with respect to the center line. In addition, the floating gate electrode 160 has a rectangular shape and is arranged symmetrically with respect to the center line. The floating gate electrode 160 is disposed on the control gate electrode 180 via the intermediate film 170 and the first gate insulation. A portion disposed (opposed) on the semiconductor substrate 110 via the film 150a is provided. Then, as a portion disposed (opposed) on the semiconductor substrate 110, it is biased toward the source 130 with the drain facing portion 160 a biased toward the drain 120 and facing the channel region 125, and the control gate electrode 180 (center line) interposed therebetween. And a source facing portion 160e facing the channel region 125. That is, the floating gate electrode 160 is disposed across the control gate electrode 180 at least in the channel region 125. Note that the source facing portion 160e plays the same role as the source facing portion 160b described in the first reference embodiment ( the source facing portion 160d described in the second reference embodiment ).

Note that such a non-volatile semiconductor memory device 100 also has a well-known split gate structure manufacturing method (for example, in the example shown in the first reference embodiment , the floating gate electrode 160 and the control gate electrode 180 are replaced, and the first gate insulating film 150a and the silicon oxide film to be the second gate insulating film 150b are interchanged). Also, data writing / erasing can be performed by performing the same treatment as in the example shown in the first reference embodiment . In the present embodiment , since the nonvolatile semiconductor memory device 100 is symmetrical with respect to the center line, the current value is equal even when a high voltage is applied to either the drain 120 or the source 130 in data reading. can do.

As described above, since the nonvolatile semiconductor memory device 100 according to the present embodiment also has a split gate structure, variation in threshold voltage after erasure can be reduced by the effect of the selection transistor by the control gate electrode 180. That is, excessive erasure can be reduced or prevented.

  In addition, by providing the control gate electrode 180 as a lower layer of the floating gate electrode 160, the control gate electrode 180 has a function as a selection gate, and the floating gate electrode 160 has a structure across the control gate electrode 180. Alternatively, it is arranged on the vicinity thereof and on the source 130 and / or the vicinity thereof. Therefore, writing by hot electrons can be performed near the drain 120 and erasing by hot holes can be performed near the source 130. That is, writing and erasing can be performed separately for the drain 120 and the source 130 (at different locations). Thus, damage to the first gate insulating film 150a and the second gate insulating film 150b can be reduced, and malfunctions (write disturb and read disturb) occurring at the time of writing / reading can be reduced or prevented.

In addition, the configuration of the drain 120 and the source 130 on the side to be erased by hot holes (the source 130 in the present embodiment ) can be simplified as compared with the configuration shown in the first embodiment . Furthermore, the structure of the floating gate electrode 160 can be simplified as compared with the configuration shown in the second reference embodiment . That is, the area per cell can be further reduced.

In addition, since the control gate electrode 180 is not disposed on the drain 120 and / or the vicinity thereof or the source 130 and / or the vicinity thereof in the channel region 125, even if a high voltage is applied to the control gate electrode 180. A high electric field is not applied to the second gate insulating film 150b between the channel region 125 and the channel region 125. Therefore, the second gate insulating film 150b can be designed thinner than the configuration shown in the first reference embodiment .

In the present embodiment , an example in which the nonvolatile semiconductor memory device 100 is configured symmetrically with respect to the center line is shown. However, it is sufficient that at least the floating gate electrode 160 is stacked on the control gate electrode 180 via the intermediate film 170 in the memory cell transistor region. Preferably, the floating gate electrode 160 is arranged on the drain 120 and the source 130 which are arranged symmetrically. More preferably, the nonvolatile semiconductor memory device 100 is symmetric with respect to the center line.

( 4th reference form )
Next, the 4th reference form of the present invention is explained based on Drawing 5 (a)-(d). Figure 5 is a diagram showing a schematic configuration of a main portion of a nonvolatile semiconductor memory device 100 according to this preferred embodiment, (a) is a plan view, (b) is a sectional view taken along the line F-F of (a) (C) is sectional drawing which follows the GG line of (a), (d) is sectional drawing which follows the HH line of (a).

Since the non-volatile semiconductor memory device 100 according to the fourth reference embodiment is in common with the non-volatile semiconductor memory device 100 shown in the first reference embodiment , a detailed description of the common parts will be omitted below, and different parts will be emphasized. I will explain it.

In the first reference embodiment , the source 130 is configured by a base portion 130a facing the drain 120 and constituting the channel region 125 and an extending portion 130b extending from the base portion 130a, and the extending portion 130b and / or the extension portion 130b. An example is shown in which the source facing portion 160b of the floating gate electrode 160 formed in an L shape is disposed to face the vicinity. On the other hand, in the present embodiment , as shown in FIGS. 5A to 5D, the source facing portion 160b of the floating gate electrode 160 is formed in the surface layer portion of the semiconductor substrate 110 and electrically connected to the source 130. It is characterized in that it is arranged on the source connection region 210 connected to and / or its vicinity. The other configuration is basically the same as that of the first reference embodiment .

Specifically, a source connection region 210, which is an N conductivity type (N +) impurity diffusion region, is formed in the surface layer portion of the main surface of the semiconductor substrate 110, similarly to the drain 120 and the source 130. The source connection region 210 is formed by an embedded diffusion region 220 that is an N conductivity type (N +) impurity diffusion region formed so as to include at least a part of the source 130 and at least a part of the source connection region 210. , And electrically connected to the source 130. Such a nonvolatile semiconductor memory device 100 can also be formed by using a known split gate structure manufacturing method. Also, data writing / erasing can be performed by performing the same treatment as in the example shown in the first reference embodiment .

As described above, since the nonvolatile semiconductor memory device 100 according to the present embodiment also has a split gate structure, the variation of the threshold voltage after erasure is caused by the effect of the selection transistor by the selection gate portion 180a of the control gate electrode 180. Can be small. That is, excessive erasure can be reduced or prevented.

  Further, the source connection region 210 electrically connected to the source 130 is provided, and the source facing portion 160b of the floating gate electrode 160 is disposed to face the source connection region 210 and / or its vicinity. Therefore, writing by hot electrons can be performed near the drain 120 and erasing by hot holes can be performed near the source connection region 210. That is, it can be performed at different locations. Thus, damage to the first gate insulating film 150a and the second gate insulating film 150b can be reduced, and malfunctions (write disturb and read disturb) occurring at the time of writing / reading can be reduced or prevented.

In the present embodiment , as shown in FIGS. 5B to 5C, an example in which the diffusion region 140 is formed only around the drain 120 is shown. However, the diffusion region 140 can be formed around the source 130 and the source connection region 210 as long as the source 130 and the source connection region 210 are electrically connected via the buried diffusion region 220. For example, since the avalanche breakdown is easily generated between the diffusion region 140 and the semiconductor substrate 110, the region where the source facing portion 160b of the floating gate electrode 160 is disposed in the source connection region 210 and / or Alternatively, it is preferable that the diffusion region 140 is formed at least on the side part in the vicinity and is electrically connected to the buried diffusion region 220 at a part where it is not partially formed.

( First embodiment )
Next, 1st Embodiment of this invention is described based on Fig.6 (a)-(c) and Fig.7 (a), (b). 6A and 6B are diagrams showing a schematic configuration of a main part of the nonvolatile semiconductor memory device 100 according to the present embodiment. FIG. 6A is a plan view, and FIG. 6B is a cross-sectional view taken along the line II of FIG. (C) is sectional drawing which follows the JJ line of (a). 7A and 7B are diagrams for explaining write / erase operations of the nonvolatile semiconductor memory device 100, where FIG. 7A shows writing and FIG. 7B shows erasing.

Since the nonvolatile semiconductor memory device 100 according to the first embodiment is common in common with the nonvolatile semiconductor memory device 100 shown in the first reference embodiment , detailed descriptions of common parts are omitted below, and different parts are emphasized. I will explain it.

In order to perform writing by hot electrons in the vicinity of the drain 120 and erase by hot holes in the vicinity of the source 130, for example, in the first embodiment , the source 130 forms a base portion 130a that forms a channel region 125 with the drain 120. And an extended portion 130b extending from the base portion 130a, and a source facing portion 160b of the floating gate electrode 160 formed in an L shape is disposed oppositely on the extended portion 130b and / or its vicinity. An example is shown. On the other hand, in the present embodiment, as shown in FIGS. 6A to 6C, a region corresponding to the source facing portion 160b of the floating gate electrode 160 (the erasing facing portion 160f) is opposed to the region. The drain diffusion region 230 is an impurity diffusion region having the same N conductivity type (N +) as the drain 120 and the source 130. The other configuration is basically the same as that of the first reference embodiment .

Specifically, in addition to the drain 120 and the source 130, an erasing diffusion region 230, which is an N conductivity type (N +) impurity diffusion region, is formed on the surface layer portion of the main surface of the semiconductor substrate 110, similar to the drain 120 and the source 130. Is formed. A contact 190c is formed in the erasing diffusion region 230, and the potential can be made independent of the drain 120 and the source 130. Similarly to the first reference embodiment , an L-shaped floating gate electrode 160 is formed, and one end of the floating gate electrode 160 is disposed on the erasing diffusion region 230 and / or its vicinity via the first gate insulating film 150a. ing. That is, in the present embodiment, the source facing portion 160b of the floating gate electrode 160 is replaced with the erasing facing portion 160f. Such a nonvolatile semiconductor memory device 100 can also be formed using a known split gate structure manufacturing method.

  Next, write / erase operations of the nonvolatile semiconductor memory device 100 according to the present embodiment will be described with reference to FIGS. In writing data by the CHE method, one of the drain 120 and the source 130 (the source 130 in this embodiment) is set to the same potential as the substrate potential, and the other of the drain 120 and the source 130 (the drain 120 in this embodiment) is connected to the substrate. A positive voltage (preferably 9 V or less) is applied to the potential, and a positive voltage (preferably 12 V or less) is applied to the control gate electrode 180. Further, the erasing diffusion region 230 is set to a floating potential. In this embodiment, as shown in FIG. 7A, the source 130 and the semiconductor substrate 110 are grounded, the erasing diffusion region 230 is applied with a floating potential, 5 V is applied to the drain 120, and 8 V is applied to the control gate electrode 180. I tried to do it.

  Under the above conditions, as shown in FIG. 7A, electrons supplied from the base portion 130a of the source 130 move at high speed in the channel region 125 toward the drain 120 facing the base portion 130a (that is, the channel current is reduced). Flow) Electrons (hot electrons) in a high energy state in the vicinity of the drain 120 jump over the first gate insulating film 150a and are injected into the drain facing portion 160a of the floating gate electrode 160. That is, data is written.

Note that, in the channel region 125, the floating gate electrode 160 (drain facing portion 160a) is arranged to be biased toward the drain 120 (a configuration in which charges can be accumulated near the drain 120). Therefore, the electrons injected into the floating gate electrode 160 can be only hot electrons that are sufficiently accelerated in the vicinity of the drain 120. As a result, erroneous writing can be reduced or prevented.

  In erasing data by the HH method, the control gate electrode 180 is applied with the same potential as the substrate potential or a negative voltage with respect to the substrate potential, the drain 120 and the source 130 are set to the floating potential, and the substrate potential is applied to the erasing diffusion region 230. In contrast, a positive voltage (for example, about 5 to 12 V) that causes avalanche breakdown between the semiconductor substrate 110 is applied. In the present embodiment, as shown in FIG. 7B, the semiconductor substrate 110 is grounded, the drain 120 and the source 130 are at a floating potential, 8V is applied to the erasing diffusion region 230, and −2V is applied to the control gate electrode 180. Applied.

  Under the above conditions, as shown in FIG. 7B, an avalanche breakdown occurs between the erasing diffusion region 230 and the semiconductor substrate 110 and an avalanche current flows. The generated high energy hole (hot hole) is injected into the erasing facing portion 160 f of the floating gate electrode 160. Thereby, in the data writing, the electrons injected into the floating gate electrode 160 are neutralized and the data is erased.

  As described above, the selection gate portion 180a of the control gate electrode 180 can exert a current control function on the channel region 125 independently of the floating gate electrode 160 (drain facing portion 160a). For example, even if the amount of hot holes injected into the floating gate electrode 160 varies among the cells, the threshold voltage of the nonvolatile semiconductor memory device 100 does not fall below the threshold voltage of the selection transistor formed by the selection gate unit 180a. That is, the on / off state of the nonvolatile semiconductor memory device 100 can be controlled by the selection transistor formed by the selection gate portion 180a, and variations in threshold voltage can be reduced.

  As described above, since the nonvolatile semiconductor memory device 100 according to the present embodiment also has a split gate structure, the variation of the threshold voltage after erasure is caused by the effect of the selection transistor by the selection gate portion 180a of the control gate electrode 180. Can be small. That is, excessive erasure can be reduced or prevented.

  In addition, an erasing diffusion region 230 that is electrically independent from the drain 120 and the source 130 is provided, and the erasing facing portion 160f of the floating gate electrode 160 is disposed to face the erasing diffusion region 230 and / or its vicinity. Has been. Therefore, writing by hot electrons can be performed near the drain 120 and erasing by hot holes can be performed near the erasing diffusion region 230. That is, it can be performed at different locations. Thus, damage to the first gate insulating film 150a and the second gate insulating film 150b can be reduced, and malfunctions (write disturb and read disturb) occurring at the time of writing / reading can be reduced or prevented.

  In the present embodiment, as shown in FIG. 6C, the diffusion region 140 is also formed around the erasing diffusion region 230. Therefore, an avalanche breakdown can easily occur between the erasing diffusion region 230 and the semiconductor substrate 110.

  Note that the erasing diffusion region 230 is electrically independent of the drain 120 and the source 130. Therefore, the concentration distribution may be different from that of the drain 120 and the source 130 in consideration of the breakdown voltage. Further, when erasing data, a voltage different from that of the drain 120 and the source 130 may be applied.

In the present embodiment, as in the first reference embodiment , the floating gate electrode 160 is disposed across the control gate electrode 180 and is formed on the opposite side of the drain 120 with the control gate electrode 180 (channel region 125) interposed therebetween. The example of being arranged on the erased diffusion region 230 and / or the vicinity thereof is shown. However, the erasing diffusion region 230 is electrically independent of the drain 120 and the source 130. Therefore, for example, as shown in FIG. 8, an erasing diffusion region 230 is formed on the same side as the drain 120 with respect to the control gate electrode 180 (channel region 125), and the erasing diffusion region 230 and / or the vicinity thereof is formed. In addition, the floating gate electrode 160 may not straddle the control gate electrode 180 so that the erasing facing portion 160f is disposed. FIG. 8 is a plan view showing a modification.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. The present invention can be applied to a nonvolatile semiconductor memory device having a split gate structure. For example, the memory cell transistor region can be applied to a configuration in which the floating gate electrode 160 and the control gate electrode 180 are not stacked and disposed, for example, adjacent to each other with the intermediate film 170 interposed therebetween.

  In the present embodiment, of the two impurity diffusion regions formed on the surface layer portion of the main surface of the semiconductor substrate 110 so as to be separated from each other, the side to which a high voltage is applied at the time of writing by the CHE method is the drain 120 and the other is Illustrated as source 130. However, the reverse configuration (writing on the source 130 side) may be used.

  In the present embodiment, an example of an N channel type is shown as the nonvolatile semiconductor memory device 100. However, the P channel type can also be adopted.

It is a figure which shows schematic structure of the principal part of the non-volatile semiconductor memory device which concerns on 1st reference form , (a) is a top view, (b) is sectional drawing which follows the AA line of (a), (b) These are sectional drawings which follow the BB line of (a). 4A and 4B are diagrams for explaining write / erase operations of the nonvolatile semiconductor memory device, where FIG. 5A shows writing and FIG. 5B shows erasing. It is a figure which shows schematic structure of the principal part of the non-volatile semiconductor memory device which concerns on 2nd reference form , (a) is a top view, (b) is sectional drawing which follows the CC line of (a), (c). These are sectional drawings which follow the DD line of (a). It is a figure which shows schematic structure of the principal part of the non-volatile semiconductor memory device which concerns on 3rd reference form , (a) is a top view, (b) is sectional drawing which follows the EE line of (a). It is a figure which shows schematic structure of the principal part of the non-volatile semiconductor memory device which concerns on 4th reference form , (a) is a top view, (b) is sectional drawing which follows the FF line of (a), (c). (A) is sectional drawing which follows the GG line, (d) is sectional drawing which follows the HH line of (a). It is a figure which shows schematic structure of the principal part of the non-volatile semiconductor memory device which concerns on 1st Embodiment , (a) is a top view, (b) is sectional drawing which follows the II line | wire of (a), (c) These are sectional drawings which follow the JJ line of (a). 4A and 4B are diagrams for explaining write / erase operations of the nonvolatile semiconductor memory device, where FIG. 5A shows writing and FIG. 5B shows erasing. It is a top view which shows a modification.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 ... Nonvolatile semiconductor memory device 110 ... Semiconductor substrate 120 ... Drain 130 ... Source 130a ... Base part 130b ... Extension part 160 ... Floating gate electrode 160a ... Drain opposite Part 160b ... source facing part 180 ... control gate electrode

Claims (1)

A non-volatile semiconductor memory device in which data is erased by neutralizing electrons accumulated in the floating gate electrode by injecting hot holes into the floating gate electrode,
A first conductivity type semiconductor substrate;
A drain and a source, which are formed in a surface layer portion of the main surface of the semiconductor substrate so as to be spaced apart from each other and in which a second conductivity type impurity opposite to the first conductivity type is diffused;
A control gate electrode and a control gate electrode having a portion disposed on the channel region with an insulating film interposed therebetween so as to face a channel region between the drain and the source of the semiconductor substrate manner and a said floating gate electrode insulated,
Of the control gate electrode, at least a part of the portion facing the channel region with the insulating film interposed therebetween is configured as a selection gate of a selection transistor ,
A diffusion region in which a part of the floating gate electrode is formed on the drain or the source in the semiconductor substrate and on the surface layer portion so as to be separated from the drain and the source, and the second conductivity type impurity is diffused. It is arranged in the upper,
An avalanche breakdown is caused between the semiconductor substrate and a diffusion region formed apart from the drain and the source, and a hot hole associated therewith is injected into the floating gate electrode Semiconductor memory device.

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