JP2003304125A - Time-division multi-channel amplifying device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the using efficiency of an amplifier by switching one amplifier by time-division to use it by each channel. <P>SOLUTION: A level detecting circuit 4 quickly detects the level of the input signal of a channel when switching circuits 5 and 7 are turned off, and an arithmetic control circuit 10 calculates a time T (i) to connect each channel by the switching circuits 5 and 7 according to the detected level of each channel and the level balance. At that time, the time T(i) is calculated so as to be made longer according as the level of each channel is made higher. An amplifier 6 belongs to linear until the input level is turned to be VIc, and performs amplification with the maximum amplification factor when the input level exceeds the VIc. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time-division multi-channel amplification device for amplifying a multi-channel input signal in a time division manner by using one amplifier.

[0002]

2. Description of the Related Art Audio equipment for home theaters, etc.
In an amplifier that handles signals on multiple channels,
As shown in FIG. 1, amplifiers corresponding to the number of channels are provided.

In such a device, there is no idea that each amplifier handles signals of each channel independently and allocates the function of each amplifier to a plurality of channels.

[0004]

However, in an audio device such as an audio device used in a home theater, which handles multi-channels, it is rare that an input signal with a large input level is simultaneously applied to each amplifier, and at a certain moment, it is almost impossible. There are many non-signal channels. For this reason, there is a problem in that the efficiency of use of the amplifier is poor and it is difficult to reduce the cost and the size because the amplifier is essential for each channel.

An object of the present invention is to provide a time division multi-channel amplifier which can improve the efficiency of use of the amplifier by switching one amplifier in time division and using it for each channel.

[0006]

According to the present invention, an input signal Vin (i) of each channel (i is channel 1 to n).
A sample and hold circuit for sampling and holding, a level detection circuit for detecting the level of each sampled and held input signal Vin (i), an input signal Vin (i) up to a predetermined value VIc is linearly amplified, and exceeds VIc. An amplifier that amplifies the input signal Vin (i) of the level with the maximum amplification factor, and the sample-and-hold signals Vin (i)
The input signal switching circuit for switching the input signal to the amplifier by switching at the switching time T (i) and the output of the amplifier by T (i).
In accordance with the level of each channel, the output signal switching circuit for switching to the output signal of the i-channel and T (i) becomes longer as the level of each channel detected by the level detection circuit becomes higher. and a control circuit for calculating and setting i).

According to the present invention, when the input signals of the channels CH1 to CHn are sample-held and passed through one amplifier in a time division manner, the time T (i) of each time division channel is set according to the level of each channel. Therefore, it is possible to use the amplifier with high efficiency,
The speaker output can be increased as the input level of the channel increases. In addition, according to the level of each channel mentioned above, it means that it corresponds to the level itself of each channel and that it corresponds to the level balance of each channel.

[0008]

FIG. 2 is a block diagram of a time division multi-channel amplifier which is an embodiment of the present invention.

The sample and hold circuit 1 includes CH1 to CH
The input signal Vin (i) (i is channel 1 to n) of each of n channels is sampled and held by a sampling clock formed by the sampling clock circuit 2 of about several 100 kHz. Each sample and hold circuit 1
The level of the input signal Vin (i) sampled and held by (1) is sequentially detected by the level detection circuit 4 via the switching circuit 3 which is switched by a clock of about several MHz.
In addition, the sampled and held input signal Vin
(I) is input to the amplifier 6 via the input signal switching circuit 5, and the input signal of each channel is amplified in time division.

The amplifier 6 is a linear amplifier, which linearly amplifies an input signal up to a predetermined value VIc with a constant gain, and amplifies an input signal having a level exceeding VIc with a maximum amplification rate.

The output signal of the amplifier 6 is output as an output signal of channels 1 to n through the output signal switching circuit 7. The output signals of channels 1 to n are integrated by an integrating circuit 8 including L and C, converted into an analog signal, and output to a speaker 9.

The level of each input signal detected by the level detection circuit 4 is input to the arithmetic control circuit 10, where:
A switching timing signal for the switching circuits 5 and 7 is formed. This switching timing signal is input to the switching control circuit 11,
The switching circuits 5 and 7 are switched in synchronization with each other. The operation control circuit 10 performs the level detection of each input signal in the level detection circuit 4 and the formation of the switching timing signal in accordance with the period, with the period for the switching circuits 5 and 7 switching from CH1 to CHn as one period. To do.

The arithmetic control circuit 10 calculates a period T (i) in which each channel is connected to the amplifier 6 in accordance with the level and level balance of each channel to form a switching timing signal. That is, the arithmetic control circuit 10 lengthens the period T (i) as the level of each channel detected by the level detection circuit 4 is higher. For this reason, the higher the level of the input signal, the longer the time T (i) for passing through the amplifier 6, and the larger the power distributed to the channel.

As described above, by sequentially switching the channels by the switching circuits 5 and 7, one amplifier 6 can be driven in a time-divisional manner for each channel, and the higher the level of each channel is, the loudspeaker 9 of the channel concerned is increased. Drive power increases. As a result, the amplifier 6 can be used with high efficiency. The integrating circuit 8 is
This is for smoothing the signals which are driven in a time division manner.

Next, the calculation method of the period T (i) and the control procedure of the calculation control circuit 10 will be described in detail with reference to FIG.

FIG. 3 is a flowchart showing the control procedure of the arithmetic control circuit 10.

In the configuration shown in FIG. 2, the input is a predetermined value V
The gain of the amplifier 6 is constant up to Ic, and the input is VI
When c, the output has the maximum value VOmax. But VI
When there is an input with a level exceeding c, the output is VOma
It is fixed at x. The number of channels is N, and the highest frequency of the desired frequency band of the output signal is F. In order to realize linear amplification up to the same maximum frequency F, the switching frequency of each channel of the input signal switching circuit 5 and the output signal switching circuit 7 is m times F (m is an integer of 2 or more and 4 to
It is desirable to select from an integer of about 10). The sampling clock circuit 2 constantly supplies a sampling clock of about several 100 kHz to the sample and hold circuit 1, and the sample and hold circuit 1 of each channel constantly samples and holds the input signal Vin (i).

In FIG. 3, first, the arithmetic control circuit 10
Controls the input signal switching circuit 5 and the output signal switching circuit 7 to turn off all channels and bring them into the unconnected state (S
T1). Next, the level detection circuit 4 samples and holds the input signal Vin (i) of each channel.
Detect the level of. At this time, the switching circuit 3 switches with a signal of about several MHz which is sufficiently higher than the sampling frequency. The input level of channel i read by the level detection circuit 4 is VI (i).

Next, the on-time T (i) of each channel of the input signal switching circuit 5 and the output signal switching circuit 7 is calculated based on VI (i) (ST3).

A method of calculating T (i) will be illustrated with reference to FIGS.

The time of one cycle of the switching circuits 5 and 7 is 1 / F
m. Therefore, when F = 20 kHz and m = 5, the time required for the switching circuits 5 and 7 to return from CH1 to CH1 is 10 μsec. A time Tc that is always assigned is set for each channel. Then, the total value of the channels of Tc is set to 1/2 of 1 / Fm (5 μse
c), the remaining 1 / (2 × Fm) time (5 μsec) is distributed according to the level or level balance of each channel. The time distributed to each channel is represented by TL (i). As will be described later, as a result of the above distribution calculation, the total value of TL (i) may exceed 1 / (2 × Fm). In this case, 1 / (2 × Fm) should be set to the level balance of each channel. , And otherwise, according to the level of each channel. Further, in this distribution, TL (i) = 0 is set when the input level is equal to or lower than a certain level VIc, and TL (i)> 0 is set when the input level exceeds VIc so that the input level is V
The distribution is made only for the channels exceeding Ic. FIG. 5A shows an input level example for each input channel. Further, FIG. 5B shows a state before distribution, and FIG. 6 shows a state after distribution. If the amplifier 6
However, if the input signal exceeding the predetermined value VIc can be linearly amplified, the output of the amplifier 6 should be as shown in FIG. 5B, but the maximum output of the amplifier 6 is VOmax.
Therefore, the input channels 2, 3, ..., N whose input level VI is equal to or higher than the predetermined value VIc are controlled so that the output is extended on the time axis as shown in FIG. That is, the hatched area in FIG. 5B is controlled so that the output is extended on the time axis.

Therefore, in the example shown in FIGS. 5 and 6,
Since the input level of CH (1) is less than VIc, TL
(1) = 0. CH (2), CH (2), CH
For (n), since the respective levels exceed VIc, TL (2), T
L (3), TL (n)> 0 and T (i)> Tc. When the input signal level exceeds VIc, the output level of the amplifier 6 is fixed at VOmax, so that T (i) in the above example is as shown in FIG. The level of the input signal exceeds VIc (VI
The relationship between −VIc) and TL is a linear relationship as shown in FIG. 7. The characteristic of this linearity can be appropriately determined in advance by measurement, simulation, or the like. However, when the level of the input signal is very high, the total value of TL (i) is 1 /
It may exceed (2 × Fm). Therefore, in such a case, 1 / (2 × Fm), which is the distributable time, is proportionally divided according to the level balance of each channel. Figure 6
Is calculated by apportioning 1 / (2 × Fm)
An example is shown in which the total value of (i) is 1 / Fm. Conversely, if the input signal level is very low,
The total value of T (i) becomes 1 / Fm or less.

The concrete arithmetic expression of T (i) is as follows.

T (i) = Tc + {TL (i) / ΣTL
(I)} × {1 / (2 × Fm)} where F is the highest frequency of the desired frequency band of the output signal,
m is an arbitrary integer value (> 1), Tc is the time that is always allocated to each channel, 1 / (2 × Fm × N), TL
(I) is a value (time) corresponding to the input level VI (i) when the input level exceeds VIc, and N is the total number of channels.

{TL (i) / ΣTL on the right side of the above equation
In (i)} × {1 / (2 × Fm)}, a value obtained by apportioning 1 / (2 × Fm) according to the level balance of each channel is obtained, and this value is added to the constant value Tc to obtain T
(I) is required.

As described above, the calculation control circuit 10 calculates T (i) (ST3), and the switching control circuit 1
In 1, the switching circuits 5 and 7 are connected to the channel during the calculated T (i) period (ST4).

Now, assuming that F = 20 kHz and m = 5,
1 / Fm = 10 μsec. Also, the number of channels N
If T is 5, Tc = 1/2 × 10 μsec × 1/5 =
It becomes 1 μsec. 1 / (2 distributed to each channel
× Fm) is 5 μsec.

In ST4 of FIG. 3, the T calculated above is calculated.
According to (i), the switching control circuit 11 causes the input signal switching circuit 5
And the output signal switching circuit 7 are sequentially switched to control CH (i).
When the switching of is completed, the process returns to ST1 and the above operation is repeated. The integrator circuit 8 demodulates the analog signal by smoothing the output signal shown in FIG. That is, when the input signal VI exceeds VIc, the amplifier 6 operates as a class D amplifier.

In the above configuration, for example, when the total number of channels N is 5 and the amplifier 6 is 100 W, the linearity of the output power is guaranteed up to 10 W for each channel, and the MAX signal comes in simultaneously on 5 channels. Then, the output of each channel becomes 20 W × 5 channels. Also, when only one channel is maximum, 60W
It becomes + 10W × 4 channels, and when 2 channels are maximum, it becomes 35W × 2 channels + 10W × 3 channels. In this way, the speaker can be driven with the highest efficiency according to the level balance of each channel.

Although the level detection circuit 4 is used in a time division manner, it is also possible to prepare a level detection circuit for each input channel and input each detected value to the arithmetic control circuit 10.

(Other Embodiments) In the above embodiment, the amplifier 6 linearly amplifies the input signal up to the predetermined value VIc, and when it exceeds VIc, it is fixed at the maximum value VOmax and T (i) is fixed. A fluctuating PWM amplification operation is performed. Instead of this, the amplifier 6 is 100% PW
It can also be configured to perform M amplification operation. With this configuration, in the arithmetic control circuit 10, T (i) is linearly changed when the input level reaches the predetermined value VIc, and T (i) = Tc (i) is obtained. Tc (i) is a value determined according to the level of the input signal VI (i), and is obtained from the linear relationship shown in FIG. Tc (i) corresponding to the input level is always assigned to each channel i.

For the input signal VI (i) having a level exceeding the predetermined value VIc, T (i) of the channel is input.
Is calculated by T (i) = Tcmax + TL (i). Here, Tcmax is the maximum value of TC when the input level is VIc, and is calculated from the relationship of FIG. TL (i) is the time distributed by proportional division according to the level or level balance of each channel as in the above embodiment. The total distribution time was 1 / (2 × Fm) in the above embodiment, but in the present embodiment, (1 / F
m-ΣTc (i)). However, ΣTc (i) is
It is a value obtained by totaling the time Tc (i) assigned to the channel i (different for each channel) for all channels.

Therefore, in this embodiment, T (i)
Is T (i) = Tc (i) + {TL (i) / ΣTL (i)}
× {1 / Fm-ΣTc (i)} where F is the highest frequency of the desired frequency band of the output signal,
m is an arbitrary integer value (> 1) Tc (i) is a time assigned to each channel (i) according to the input level, and a value according to the input level (= <Tcmax) Tcmax is 1 / ( 2 × Fm × N), the Tc value TL (i) when the input level exceeds VIc is the value (time) N corresponding to the excess when the input level VI (i) exceeds VIc. , Total number of channels.

FIG. 8 shows an input level example for each input channel. Further, FIG. 9 shows a state after distribution. In the input channel (1), since the input level is VIc or less, TC (1) is TCmax or less. Input channels CH (2), CH (3), CH
In (n), since the input level exceeds VIc, T
C (2), TC (3), TC (n) are Tmax to T
It is a value obtained by adding L (2), TL (3), and TL (n).

In this embodiment as well, the speaker can be driven with the highest efficiency in accordance with the level balance of each channel.

In any of the above embodiments,
Since noise is generated at the switching timing of the switching circuits 5 and 7, in order to prevent it, a known noise mute means composed of a capacitor or the like is provided, and the time Tα for noise mute by this is added to the above T (i). Is desirable.

[0037]

According to the present invention, since only one amplifier is required, it is advantageous in improving space efficiency and reducing component costs, and the operating time of the amplifier is optimally distributed according to the level balance of input signals. Therefore, one amplifier can drive a plurality of speakers with high efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram of a conventional multi-channel amplifier.

FIG. 2 is a configuration diagram of a time division multi-channel amplifier according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a schematic operation of the arithmetic control circuit 10.

FIG. 4 is a diagram illustrating a calculation method.

FIG. 5 is a diagram illustrating a calculation method.

FIG. 6 is a diagram illustrating a calculation method.

FIG. 7 is a diagram showing linearity that determines TL according to the level balance of each channel.

FIG. 8 is a diagram illustrating a calculation method according to another embodiment of the present invention.

FIG. 9 is another diagram for explaining a calculation method according to another embodiment of the present invention.

FIG. 10 shows TC depending on the input level VI of each channel.
Showing linearity that determines

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Claims (2)

[Claims] 1. An input signal Vin (i) (i) of each channel
Is a sample and hold circuit that samples and holds channels 1 to n), a level detection circuit that detects the level of each sampled and held input signal Vin (i), and a linear input signal Vin (i) up to a predetermined value VIc. An amplifier that amplifies an input signal Vin (i) having a level exceeding VIc at a maximum amplification rate, and switches each sampled and held signal Vin (i) at a switching time T (i) to input to the amplifier. Input signal switching circuit, an output signal switching circuit that switches the output of the amplifier by T (i) to output an i-channel output signal, and the higher the level of each channel detected by the level detection circuit, the higher the T (i ) Becomes longer, a control circuit for calculating and setting T (i) according to the level of each channel, and Tunnel amplifier. 2. The control circuit performs T as follows.
The time division multi-channel amplifier according to claim 1, which calculates (i). T (i) = Tc + {TL (i) / ΣTL (i)} × {1
/ (2 × Fm)} where F is the highest frequency of the desired frequency band of the output signal,
m is an arbitrary integer value (> 1), Tc is the time that is always allocated to each channel, 1 / (2 × Fm × N), TL
(I) is a value (time) corresponding to the amount when the input level VI (i) exceeds a predetermined value VIc, and N is
Total number of channels.