JP4063801B2 - Light emitting diode - Google Patents

Description

  The present invention provides a compound semiconductor device having an n-type or p-type ohmic electrode on an n-type or p-type boron phosphide-based semiconductor layer, and comprising an ohmic electrode having a low contact resistance. It relates to technology.

Conventionally, for example, a group III nitride semiconductor represented by the general formula Al _x Ga _y In _z N (0 ≦ x, y, z ≦ 1, x + y + z = 1) has been used for short-wavelength visible light in the blue or green band. Is used as a material for forming a light emitting element that emits light and a field effect transistor (abbreviation: FET) (see, for example, Non-Patent Document 1). On the other hand, a boron phosphide-based semiconductor containing boron (element symbol: B) and phosphorus (element symbol: P) as constituent elements is, for example, a contact layer for constituting a laser diode (abbreviation: LD). (See, for example, Patent Document 1). The contact layer is a conductive layer provided to form an ohmic electrode with low contact resistance. Conventionally, an example in which the contact layer is formed of a p-type boron phosphide layer to which magnesium (Mg) is added is known (see, for example, Patent Document 1).

  Monomeric boron phosphide (BP) is said to provide a p-type conductive layer which is undoped and has a low resistance without doping with impurities (see, for example, Patent Document 2). . For this reason, boron phosphide is used as a material suitable for constituting the contact layer. For example, on a contact layer made of p-type boron phosphide, a compound semiconductor element is formed by providing a p-type ohmic electrode from aluminum (Al) alone. For example, a technique for forming an LD by providing a p-type ohmic electrode made of gold (Au) / zinc (Zn) on a contact layer made of p-type boron phosphide has been disclosed (for example, see Patent Document 1). .)

JP-A-2-288388 US Pat. No. 6,069,021 Akazaki Isamu, "III-V compound semiconductor", first edition, Baifukan Co., Ltd., May 20, 1994, Chapter 13

  However, in the conventional configuration in which the p-type or n-type ohmic electrode is provided in direct contact with the surface of the p-type or n-type boron phosphide-based semiconductor layer, the ohmic electrode exhibiting good ohmic contact is sufficiently stable. It was not obtained. Therefore, the advantage of the boron phosphide-based semiconductor layer in which a conductive layer having a low resistance can be obtained in an undoped state in which impurities are not intentionally added and without requiring a post-treatment such as a heat treatment after film formation. There has been a demand for technical means for obtaining an ohmic electrode that can be utilized.

  In the present invention, unlike the prior art, the p-type or n-type ohmic electrode is not provided in direct contact with the surface of the boron phosphide-based semiconductor layer. In order to solve the above-described problems of the prior art, in the present invention, an ohmic electrode is provided in contact with the conductive silicon (Si) semiconductor layer provided on the boron phosphide-based semiconductor layer. The present invention also provides a compound semiconductor light emitting device using an electrode having excellent ohmic contact obtained by this configuration.

In order to solve the above problems, the present invention has the following configuration.
(1) A crystal substrate, a boron phosphide-based semiconductor layer containing boron (element symbol: B) and phosphorus (element symbol: P) provided on one surface of the crystal substrate as constituent elements, and the phosphation A boron phosphide-based semiconductor layer provided in contact with the surface of the boron phosphide-based semiconductor layer in a compound semiconductor device including an ohmic electrode provided on the boron-based semiconductor layer A compound semiconductor element, wherein an ohmic electrode is provided in contact with a silicon (element symbol: Si) semiconductor layer having the same conductivity type.

  (2) The boron phosphide-based semiconductor layer is p-type, and the silicon semiconductor layer provided in contact with the surface of the p-type boron phosphide-based semiconductor layer is a p-type conductive layer containing boron (B), The compound semiconductor device according to (1) above, wherein a p-type ohmic electrode is provided in contact with the surface of the p-type silicon semiconductor layer.

  (3) The boron phosphide-based semiconductor layer is n-type, and the silicon semiconductor layer provided in contact with the surface of the n-type boron phosphide-based semiconductor layer is an n-type conductive layer containing phosphorus (P), The compound semiconductor device according to (1) above, wherein an n-type ohmic electrode is provided in contact with the surface of the n-type silicon semiconductor layer.

  (4) In the above (1), (2), or (3), the ohmic electrode is provided in contact with the surface of the silicon semiconductor layer that is left only in the region where the ohmic electrode is provided. The compound semiconductor element as described.

  (5) A boron phosphide-based semiconductor layer containing boron (B) and phosphorus (P) as constituent elements is formed on one surface of a crystal substrate by a vapor phase growth method, and then the boron phosphide-based semiconductor In a method for forming a compound semiconductor element, a silicon (Si) semiconductor layer having the same conductivity type is formed on a layer, and an ohmic electrode is provided on the silicon semiconductor layer to form a compound semiconductor element. Boron phosphide-based semiconductor is added while the boron phosphide-based semiconductor layer used for vapor-phase growth of the boron phosphide-based semiconductor layer is added after vapor-phase growth of the boron phosphide-based semiconductor layer using the raw material and the phosphorous material. A method for forming a compound semiconductor device, comprising: forming a conductive silicon semiconductor layer having the same conductivity type as a boron phosphide-based semiconductor layer on a surface of the layer by vapor phase growth.

  (6) After the vapor growth of the p-type boron phosphide-based semiconductor layer using the boron raw material and the phosphorus raw material, the boron raw material used for the vapor-phase growth of the p-type boron phosphide-based semiconductor layer is added. However, the method for forming a compound semiconductor device according to (5) above, wherein a p-type silicon semiconductor layer is formed by vapor phase growth on the surface of the p-type boron phosphide-based semiconductor layer.

  (7) While vapor-growing an n-type boron phosphide-based semiconductor layer using a boron raw material and a phosphorus raw material, adding the phosphorus raw material used for vapor-phase growing the n-type boron phosphide-based semiconductor layer The method for forming a compound semiconductor device according to (5) above, wherein an n-type silicon semiconductor layer is formed by vapor phase growth on the surface of the n-type boron phosphide-based semiconductor layer.

  (8) A silicon semiconductor layer having the same conductivity type as the boron phosphide-based semiconductor layer is formed on the surface of the boron phosphide-based semiconductor layer, and the silicon semiconductor layer is left only in a region where an ohmic electrode is to be formed. The method of forming a compound semiconductor device according to (5), (6), or (7) above, wherein the ohmic electrode is formed by contacting with the surface of the remaining silicon semiconductor layer.

  (9) On the first conductivity type silicon single crystal substrate, a lower clad layer made of a boron phosphide-based semiconductor of the first conductivity type, a light emitting layer made of a gallium nitride-based semiconductor, and a boron phosphide-based semiconductor of the second conductivity type And a second conductivity type silicon semiconductor layer is laminated on and in contact with the upper clad layer, and a second conductivity type ohmic electrode and a second conductivity type silicon semiconductor layer are formed on the surface of the second conductivity type silicon semiconductor layer. A light emitting diode in which an ohmic electrode of a first conductivity type is formed on the back surface of a single conductivity type silicon single crystal substrate.

  (10) On the sapphire substrate, a lower cladding layer made of a gallium nitride semiconductor of a first conductivity type, a light emitting layer made of a gallium nitride semiconductor, and an upper cladding layer made of a boron phosphide semiconductor of a second conductivity type are sequentially stacked. A second conductivity type silicon semiconductor layer is laminated on and in contact with the upper clad layer, and a second conductivity type ohmic electrode and a first conductivity type lower clad layer are formed on the surface of the second conductivity type silicon semiconductor layer. A light emitting diode in which an ohmic electrode of a first conductivity type is formed.

  According to the present invention, a compound semiconductor is provided by utilizing an ohmic electrode provided in contact with a boron phosphide-based semiconductor layer and in contact with a silicon semiconductor layer having the same conductivity type as the boron phosphide-based semiconductor layer. Since the element is configured, for example, a compound semiconductor LED having a low forward voltage (Vf) can be provided.

  In the present invention, in particular, an ohmic electrode is formed on a phosphorus source or an n-type or p-type silicon semiconductor layer containing phosphorus or boron formed by vapor phase growth of a boron phosphide-based semiconductor layer. Therefore, for example, a compound semiconductor LED having a low forward voltage can be provided.

  In the present invention, a compound semiconductor element is configured using an n-type or p-type ohmic electrode provided in contact with an n-type or p-type silicon semiconductor layer left only in a region where an ohmic electrode is provided. Therefore, for example, unnecessary light emission absorption due to the silicon semiconductor layer can be avoided, and a compound semiconductor LED with a low forward voltage and high brightness can be provided.

The boron phosphide-based semiconductor according to the present invention includes boron (B) and phosphorus (P) as constituent elements, for example, B _α Al _β Ga _γ In _1-α-β-γ P _1-δ As _δ (0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ <1, 0 <α + β + γ ≦ 1, 0 ≦ δ <1). Also, for example, B _α Al _β Ga _γ In _1-α-β-γ P _1-δ N _δ (0 <α ≦ 1, 0 ≦ β <1, 0 ≦ γ <1, 0 <α + β + γ ≦ 1, 0 ≦ δ <1). For example, monomeric boron phosphide (BP), boron phosphide / gallium / indium (compositional formula B _α Ga _γ In _1-α-γ P: 0 <α ≦ 1, 0 ≦ γ <1), Boron phosphide (compositional formula BP _1-δ N _δ : 0 ≦ δ <1) or boron arsenide phosphide (compositional formula B _α P _1-δ As _δ : 0 ≦ δ <1) containing a group V element It is a crystal. In mixed crystals in which the boron (B) composition ratio (= α) and the phosphorus composition ratio (= 1−δ: 0 ≦ δ <1) both exceed 0.5 (= 50%), the low resistance p-type and n The shaped conductive layer can be easily formed in an undoped state and an as-grown state. For this reason, it is convenient to obtain an electrode excellent in ohmic contact.

The boron phosphide-based semiconductor layer can be formed by vapor phase growth means such as a halogen method, a hydride method, or a MOCVD (metal organic chemical vapor deposition) method. Vapor phase growth can also be performed by molecular beam epitaxy (see J. Solid State Chem., 133 (1997), pages 269 to 272). For example, the boron phosphide (BP) layer can be formed by MOCVD using triethylboron (molecular formula: (C ₂ H ₅ ) ₃ B) as a boron source and phosphine (molecular formula: PH ₃ ) as a phosphorus source. For example, a temperature of 1000 ° C. to 1200 ° C. is suitable for forming a p-type BP layer. On the other hand, a lower temperature of 800 ° C. to 1000 ° C. is suitable for forming the n-type BP layer than when the p-type BP layer is vapor-phase grown.

The silicon semiconductor layer can be deposited on the boron phosphide-based semiconductor layer using the vapor phase growth means described above. For example, it can be formed by a halogen vapor phase growth method using silicon tetrachloride (molecular formula: SiCl ₄ ) as a silicon (Si) source. The conductivity type of the silicon semiconductor layer is matched with the conductivity type of the boron phosphide-based semiconductor layer. For example, the silicon semiconductor layer provided on the p-type boron phosphide layer is a p-type conductive layer. The silicon semiconductor layer is preferably a conductive layer having a high carrier concentration and a low resistance in order to conveniently form an electrode having excellent ohmic contact thereon. In particular, the carrier concentration at room temperature is particularly preferably 1 × 10 ¹⁹ cm ⁻³ or more and the resistivity is 5 × 10 ⁻² Ω · cm or less. The silicon semiconductor layer can be simply formed using the same growth equipment after the vapor growth of the boron phosphide-based semiconductor layer. At that time, if a boron source used for vapor phase growth of the boron phosphide-based semiconductor layer is used as a boron doping material, a p-type boron-doped silicon semiconductor layer can be formed. Furthermore, by adjusting the amount of boron added, a p-type boron-doped silicon semiconductor layer with a controlled carrier concentration can be obtained. Further, an n-type phosphorus-doped silicon semiconductor layer having a desired carrier concentration can be formed by adjusting the amount of phosphorus source added.

  The thickness of the silicon semiconductor layer is desirably 5 nanometers (nm) or more and 500 nm or less. If the silicon semiconductor layer is excessively thin, it is difficult to obtain a continuous film that can sufficiently cover the surface of the boron phosphide-based semiconductor layer, and a region where the ohmic electrode directly contacts the surface of the boron phosphide-based semiconductor layer is generated. . Accordingly, a silicon semiconductor layer of less than 5 nm cannot be used preferably. On the other hand, the surface of the thick silicon semiconductor layer exceeding 500 nm is not flat and is messy, and thus cannot be preferably used in the present invention. In a short-wavelength visible or ultraviolet light-emitting diode (abbreviation: LED), the thickness of the silicon semiconductor layer provided in the direction in which light emission is extracted to the outside is 2 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less. is there. The forbidden band width at room temperature of silicon (Si) semiconductor is as low as about 1.2 electron volts (unit: eV), and visible light and ultraviolet light are absorbed. For this reason, when the silicon semiconductor layer is thickened, the efficiency of taking out emitted light to the outside is lowered, which causes inconvenience in obtaining high-luminance visible and ultraviolet LEDs.

  A p-type ohmic electrode is provided on the surface of the p-type silicon semiconductor layer on the p-type boron phosphide-based semiconductor layer. The p-type ohmic electrode can be composed of a known electrode material for the silicon semiconductor layer. The p-type ohmic electrode includes, for example, aluminum (Al), gold (Au), gold-boron (Au-B) alloy, aluminum-lead (Al-Pb) alloy, indium (In), indium-lead (Pb) alloy, etc. (Refer to AG Milles, D. L. Feucht, “Semiconductor Heterojunction”, September 1, 1974, published by Morikita Publishing Co., Ltd., first edition, first edition, pages 297-300. .) The n-type ohmic electrode provided on the n-type silicon semiconductor layer includes a gold-antimony (Au-Sb) alloy, a gold-tin (Au-Sn) alloy, an aluminum-gold-phosphorus (Al-Au-P) alloy, gold -An antimony-silicon (Au-Sb-Si) alloy etc. can be comprised (refer said "semiconductor heterojunction" above).

By providing an electrode in contact with the p-type or n-type silicon semiconductor layer, an ohmic electrode having a low contact resistance can be obtained. For example, contact of an electrode made of a gold-germanium (Au 99 mass% -Ge 1 mass%) alloy provided in direct contact with the surface of an n-type boron phosphide layer having a carrier concentration of about 5 × 10 ¹⁹ cm ⁻³ The resistance is about 6 × 10 ⁻³ Ω · cm ² . On the other hand, the contact resistance of the Au—Ge electrode provided in contact with the surface of the phosphorus (P) -doped n-type silicon semiconductor layer having substantially the same carrier concentration grown by vapor deposition according to the present invention is about 9 × 10 ^{−. 2} Ω · cm ² , decreasing to about 1/7.

  For example, the silicon semiconductor layer may be provided on the entire surface of the electron supply layer made of a boron phosphide-based semiconductor layer left in a region where the source and drain electrodes of the high electron mobility FET are provided. . On the other hand, it is not always necessary to form the entire surface of the boron phosphide-based semiconductor layer, and the boron phosphide-based semiconductor layer may be provided only in a region where an ohmic electrode is to be provided. For example, in a LED in which light emission is extracted from the side on which the boron phosphide-based semiconductor layer is formed, the silicon semiconductor layer can be limited to a region for forming an ohmic electrode. When the silicon semiconductor layer is arranged in this manner, the degree of light emission absorbed by the silicon semiconductor layer can be reduced as compared with the case where the silicon semiconductor layer is formed on the entire surface of the boron phosphide-based semiconductor layer. Therefore, when the silicon semiconductor layer is arranged in this manner, it is possible to efficiently emit light to the outside and to configure an LED including an ohmic electrode with low contact resistance.

As a means of leaving the silicon semiconductor layer only in the region where the ohmic electrode is to be formed, the silicon semiconductor layer is once vapor-phase grown on substantially the entire surface of the boron phosphide-based semiconductor layer, and then selectively etched. There is a means to apply. If a selective patterning technique using known photolithography and an etching technique are used, the silicon semiconductor layer can be left only in the region where the ohmic electrode is formed. The silicon semiconductor layer can be etched with a mixed acid of hydrofluoric acid (molecular formula: HF) and nitric acid (molecular formula: HNO ₃ ). The silicon semiconductor layer can be removed by plasma etching means using a halogen-based gas. As another technical means, there is a means for vapor-depositing a silicon semiconductor layer only in a region where an ohmic electrode is provided on a boron phosphide-based semiconductor layer using a selective growth technique. When the silicon semiconductor layer is selectively grown on the boron phosphide-based semiconductor layer, a dielectric film such as a silicon oxide film such as silicon dioxide (SiO ₂ ) or a silicon nitride film such as trisilicon tetranitride (Si ₃ N ₄ ) Can be used.

  A conductive silicon semiconductor layer having the same conductivity type as the boron phosphide-based semiconductor layer provided on the boron phosphide-based semiconductor layer has an effect of providing an ohmic electrode having a low contact resistance.

  The silicon semiconductor layer left on the boron phosphide-based semiconductor layer limited to the region where the ohmic electrode is provided is, for example, an LED that emits light to the silicon semiconductor layer side, and an ohmic electrode with a low contact resistance is used. In addition, it has the effect of increasing the efficiency of taking out emitted light to the outside.

  The present invention is embodied by taking an example in which an n-type silicon semiconductor layer is provided on the surface of an n-type boron phosphide semiconductor layer and a compound semiconductor LED is configured using an n-type ohmic electrode formed on the silicon semiconductor layer. I will explain it.

FIG. 1 schematically shows a cross-sectional structure of an LED 100 having a double hetero (DH) junction structure described in this example. For the substrate 101, boron (B) doped p-type (111) -silicon (Si) single crystal was used. Vapor phase growth of an undoped p-type (111) -boron phosphide (BP) layer (carrier concentration = 3 × 10 ¹⁹ cm ⁻³ , layer thickness = 1.1 μm) as a lower cladding layer 102 on the substrate 101 I let you. On the lower cladding layer 102, a multi-quantum in which a unit laminated structure composed of an n-type gallium nitride / indium (Ga _0.90 In _0.10 N) well layer 103a and an n-type gallium nitride (GaN) barrier layer 103b is laminated in three periods. A light emitting layer 103 having a well (MQW) structure was deposited. On the n-type (0001) -GaN barrier layer constituting the outermost layer of the MQW structure constituting the light emitting layer 103, an undoped n-type (111) -boron phosphide layer (carrier concentration = 8 × 10 ¹⁸ cm ^{−). 3} and layer thickness = 1.0 μm) was deposited and formed.

The undoped p-type and n-type boron phosphide layers 102 and 104 constituting the lower and upper cladding layers 102 and 104 are made of triethyl boron (molecular formula: (C ₂ H ₅ ) ₃ B) as a boron (B) source and phosphine ( It was formed by using an atmospheric pressure (substantially atmospheric pressure) organometallic vapor phase epitaxy (MOVPE) means using a molecular formula: PH ₃ ) as a phosphorus source. The p-type boron phosphide layer 102 was formed at 1025 ° C., and the n-type boron phosphide layer 104 was formed at 850 ° C. The light emitting layer 103 was formed at 800 ° C. by trimethylgallium (molecular formula: (CH ₃ ) ₃ Ga) / NH ₃ / H ₂ reaction system atmospheric pressure MOCVD means. The gallium nitride / indium layer constituting the well layer 103a is composed of a multiphase structure composed of a plurality of domains having different indium compositions. The average indium composition of the domain (crystal mass) was 0.10 (= 10%). The layer thicknesses of the well layer 103a and the barrier layer 103b were 5 nm and 10 nm, respectively.

  The forbidden band width of the undoped n-type boron phosphide forming the upper clad layer 104 is 3.2 eV at room temperature, so that it also serves as a window layer for transmitting light emitted from the light emitting layer 103 to the outside. Used as an n-type cladding layer.

An n-type silicon semiconductor layer 105 containing phosphorus (P) is deposited on the surface of the upper cladding layer 104 using phosphine (PH ₃ ) used as a phosphorus source during vapor phase growth of the n-type boron phosphide layer. did. The silicon semiconductor layer 105 was grown at 1050 ° C. using disilane (molecular formula: Si ₂ H ₆ ) as a silicon source. The silicon semiconductor layer 105 was constructed simply by completing the vapor phase growth of the n-type boron phosphide layer according to the MOVPE method described above, and subsequently performing it in the same MOCVD growth apparatus. The amount of phosphine added was adjusted so that the carrier concentration of the silicon semiconductor layer 105 was 8 × 10 ¹⁹ cm ⁻³ . The silicon semiconductor layer 105 had a thickness of 10 nm and was provided on the entire surface of the n-type boron phosphide layer forming the upper cladding layer 104.

  A circular n-type ohmic electrode 106 having a diameter of 130 μm was disposed at the center of the surface of the silicon semiconductor layer 105 by a normal vacuum vapor deposition method and an electron beam vapor deposition method. The n-type ohmic electrode 106 is a Au / Ge alloy film (thickness = 700 nm) / nickel (Ni) film in which the side in contact with the surface of the silicon semiconductor layer 105 is a gold / germanium alloy (Au 97 mass% + Ge 3 mass%) film. A three-layer structure of (thickness = 80 nm) / gold (Au) (thickness = 1400 nm) was adopted. On the other hand, a p-type ohmic electrode 107 was formed on the entire back surface of the p-type silicon single crystal substrate 101 by depositing a gold / antimony (Au / Sb) film by a general vacuum deposition method. Next, a square LED chip (chip) 100 having a side of 350 μm was cleaved parallel to the <110> crystal direction of the Si single crystal substrate 101.

  A light emission characteristic of the LED chip 100 was investigated by passing a device drive current of 20 mA in the forward direction between the n-type and p-type ohmic electrodes 106 and 107. The LED 100 emitted blue band light having a center wavelength of 430 nm. The half width of the emission spectrum was 120 millielectron volts (meV). In this example, although the silicon semiconductor layer 105 was provided on the entire surface of the n-type boron phosphide layer on the surface side for extracting emitted light to the outside, the thickness of the silicon semiconductor layer 105 was reduced to 10 nm. For this reason, the absorption of light emission was suppressed, and the luminance in the chip state measured using a general integrating sphere was 8 millicandelas (mcd). Since the n-type ohmic electrode 106 is provided in contact with the surface of the n-type silicon semiconductor layer 105 containing phosphorus, the forward voltage (Vf) when the forward current is 20 mA is as low as 3.1 V. Value. On the other hand, the reverse voltage when the reverse current was 10 μA was 9.5 V, and the LED was excellent in reverse breakdown voltage.

  The present invention will be specifically described by taking as an example the case of forming a compound semiconductor LED by forming a p-type silicon semiconductor layer only in a region where a p-type ohmic electrode is provided.

  FIG. 2 schematically shows a planar structure of the LED 200 described in the present embodiment. FIG. 3 schematically shows a cross-sectional structure of the LED 200 along the broken line A-A ′ shown in FIG. 2.

As the substrate 101, (0001) -sapphire (α-Al ₂ O ₃ single crystal) was used. A lower clad layer 102 made of n-type gallium nitride (GaN) (carrier concentration = 7 × 10 ¹⁸ cm ⁻³ , layer thickness = 3.1 μm) on a substrate 101, n-type gallium nitride phosphide doped with silicon Light-emitting layer 103 made of mixed crystal (GaN _0.97 P _0.03 ) (carrier concentration = 7 × 10 ¹⁷ cm ⁻³ , layer thickness = 0.1 μm), undoped p-type B _0.98 Ga _0.02 P (carrier concentration = 1 × 10) ^The upper cladding layer 104 having a thickness of ¹⁹ cm ⁻³ and a layer thickness of 1.1 μm was sequentially grown by the MOVPE method. The vapor phase growth temperature was 1100 ° C. for the n-type GaN layer, and 1000 ° C. for the GaN _0.97 P _0.03 layer and the B _0.98 Ga _0.02 P layer.

A silicon semiconductor layer 105 having a thickness of 490 nm was once deposited on the upper cladding layer 104. The silicon semiconductor layer 105 was grown while adding triethylboron (molecular formula: (C ₂ H ₅ ) ₃ B) used as a boron source during the growth of the B _0.98 Ga _0.02 P layer. The carrier concentration of the p-type silicon semiconductor layer 105 containing boron (B) was 8 × 10 ¹⁹ cm ⁻³ .

First, the silicon semiconductor layer 105, the upper clad layer 104, and the light emitting layer 103 in a region where the n-type ohmic electrode 106 is to be formed are removed using a known photolithography technique and plasma etching technique (see FIG. 3). ). Thus, the surface of the lower cladding layer 102 was exposed only in the region where the n-type ohmic electrode 106 was to be formed. Next, after patterning the boron-containing p-type silicon semiconductor layer 105 of the B _0.98 Ga _0.02 P layer, the unnecessary p-type silicon semiconductor layer 105 was removed by plasma dry etching. Thus, the p-type silicon semiconductor layer 105 was left only in the rectangular region where the p-type ohmic electrode 107 on the B _0.98 Ga _0.02 P layer was to be formed (see FIGS. 2 and 3). An n-type ohmic electrode 106 was formed on the lower cladding layer 102 exposed as described above. The n-type ohmic electrode 106 has a multilayer structure in which the side in contact with the n-type GaN layer is titanium (Ti: film thickness = 0.5 μm) and the upper layer is gold (Au: film thickness = 2.1 μm). In addition, on the silicon semiconductor layer 105 left as described above, a rectangular p-type ohmic electrode 107 similar to the planar shape of the left silicon semiconductor layer 105 was formed. The p-type ohmic electrode 107 was made of gold (Au: film thickness = 2.2 μm).

The emission center wavelength when a forward current of 20 mA was passed between the n-type and p-type ohmic electrodes 106 and 107 of the LED chip 200 was 430 nm. In this example, the p-type silicon semiconductor layer was left only in the region where the p-type ohmic electrode 107 on the B _0.98 Ga _0.02 P layer in the direction of taking out the emitted light was left. For this reason, unnecessary absorption of light emission due to the silicon semiconductor layer 105 was avoided, and the light emission luminance was 12 mcd. In addition, since the p-type ohmic electrode 107 is provided in contact with the surface of the p-type silicon semiconductor layer 105 containing boron (B), an ohmic electrode with low input resistance can be formed. For this reason, the forward voltage when a forward current of 20 mA was passed was a low value of 3.2V. When the reverse current was 10 μA, the reverse voltage was 8.7 V, resulting in an LED with excellent reverse withstand voltage.

2 is a schematic diagram showing a cross-sectional structure of an LED described in Example 1. FIG. 6 is a schematic diagram showing a planar structure of an LED described in Example 2. FIG. FIG. 3 is a schematic diagram showing a cross-sectional structure along a broken line A-A ′ of the LED shown in FIG. 2.

Explanation of symbols

100, 200 LED
DESCRIPTION OF SYMBOLS 101 Substrate 102 Lower clad layer 103 Light emitting layer 104 Upper clad layer 105 Silicon semiconductor layer 106 n-type ohmic electrode 107 p-type ohmic electrode

Claims (2)

On the sapphire substrate, a lower cladding layer made of a gallium nitride semiconductor of a first conductivity type, a light emitting layer made of a gallium nitride semiconductor, and an upper cladding layer made of a boron phosphide semiconductor of a second conductivity type are sequentially stacked, A second conductivity type silicon semiconductor layer is stacked on and in contact with the upper clad layer, and the second conductivity type ohmic electrode is formed on the surface of the second conductivity type silicon semiconductor layer, and the first conductivity type lower clad layer is provided with the first conductivity type. Light emitting diodes each having an ohmic electrode of a shape. The upper clad layer is p-type, and the silicon semiconductor layer laminated in contact with the p-type upper clad layer is a p-type conductive layer containing boron (B), and is in contact with the surface of the p-type silicon semiconductor layer. The light emitting diode according to claim 1, further comprising a p-type ohmic electrode.

Images