JP4032922B2 - Display device and display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device in which each pixel includes a light-emitting element whose emission luminance is changed by a current such as an organic EL (Electro Luminescence), and a display panel used therefor.
[0002]
[Prior art]
In recent years, display devices using organic EL as a light-emitting element have been actively developed for portable information terminals and television receivers. A self-luminous display device provided with a light emitting element such as an organic EL in each pixel has good visibility and excellent moving image display characteristics.
In particular, in an active display device using a thin film transistor (TFT) formed on a glass substrate as a pixel switching element, a current is supplied to the light emitting element until the next rewriting based on the rewritten signal. Since it can continue to flow, there is an advantage that high luminance can be obtained with a driving current to a light emitting element smaller than that of a passive type that does not use a switching element in a pixel.
[0003]
The conventional display device includes a scanning line driving circuit that sequentially selects the scanning lines scanA and scanB, and a current source CS that generates a signal current Iw having a current level corresponding to luminance information and sequentially supplies the signal current Iw to the data line data. A data line driving circuit and a plurality of pixels including current-driven light-emitting elements OLED that are arranged at intersections of the scanning lines scanA and scanB and the data lines data and emit light upon receiving a driving current. I have. As a feature, the pixel includes a receiving unit that takes in the signal current Iw from the data line data when the scanning line scanA is selected, and a conversion that temporarily converts the current level of the taken signal current Iw into a voltage level and holds it. And a drive unit that causes a drive current having a current level corresponding to the held voltage level to flow through the light emitting element OLED (see, for example, Patent Document 1).
[0004]
[Patent Document 1]
JP 2001-147659 A (page 7-9, FIG. 1 and FIG. 5)
[0005]
[Problems to be solved by the invention]
Among the thin film transistors, low temperature polycrystalline silicon TFTs (low temperature p-Si TFTs) that can be manufactured by a low temperature process have higher mobility than amorphous silicon TFTs, so this low temperature p-Si TFT drive circuit is placed on a glass substrate on a pixel matrix. It can be formed integrally with a circuit and has been widely used for liquid crystal display devices.
However, a low-temperature p-Si TFT is generally formed by laser annealing, but Vth (threshold voltage) or μ is higher than that of single crystal silicon because it is difficult to control the laser irradiation intensity uniformly within the glass substrate surface. It is known that characteristic variations such as (mobility) are large.
[0006]
In a conventional display device, when a data line driving circuit is configured integrally with a pixel matrix on a glass substrate using TFTs in a display panel, the data line (signal line) driving current varies in each column due to variations in TFT characteristics. As a result, there is a problem that unevenness of vertical streaks or vertical stripes occurs in the light emission luminance.
[0007]
The present invention has been made in order to solve the above-described problems. Even when the variation in TFT characteristics is large, variation in signal line drive current in each column can be suppressed, and unevenness in light emission luminance can be suppressed. An object is to obtain a display device.
[0008]
It is another object of the present invention to provide a display panel that can easily perform non-defective product / defective product inspection by detecting variations in signal line drive current when manufacturing a display panel or a display device.
[0009]
[Means for Solving the Problems]
A display device according to a first configuration of the present invention includes a pixel matrix circuit for supplying a drive current to a light emitting element of each pixel based on a signal current supplied in accordance with an image signal to be displayed, and the pixel matrix circuit. A power source connected to the pixel matrix circuit, a signal line for supplying the signal current to the pixel matrix circuit, Scanning means for sequentially scanning the pixel matrix circuit; Signal line driving means for outputting the image signal to be displayed to the signal line as the signal current flowing between the power supply and the signal line, and the signal supplied to the signal line in each column of the pixel matrix circuit A signal current is detected when the signal line driving means outputs the signal current, and is sequentially output as a detection result, and the display should be performed based on the detection result detected by the signal current detection means. Correction means for correcting the image signal In the display device, the signal current detection means includes a switch circuit having one end connected to each of the signal lines in each column and provided for each column, and a current in which the other end of the switch circuit is connected in common. A switch control means for controlling the detection circuit and the switch circuit to be sequentially turned on, and the pixel matrix circuit is scanned by the scanning means during the writing operation to the pixel matrix circuit; When the signal current to be output flows between the power source and the signal line through the power supply connection portion and the signal current is detected by the signal current detection means, the scanning means is stopped and the pixel matrix is stopped. The signal current does not flow in the circuit, and the signal line and the current detection line are sequentially conducted by the switch circuit, and output from the signal line driving means. The signal current of each column is detected appeared in the current detection line It is characterized by that.
[0011]
In the display device according to the third configuration of the present invention, 1 In the above configuration, the signal current detection means includes current-voltage conversion means for amplifying the signal current of each column appearing on the current detection line by a predetermined current ratio and converting the amplified signal current to a voltage.
[0012]
In addition, the first of the present invention 3 In the display device having the configuration described above, in the first configuration, the detection result when the image signals to be displayed at the first and second levels are respectively input and the reference corresponding to the first and second levels. Error detection means for outputting a difference from the detection result as an error detection result, wherein the correction means is configured to display the image to be displayed based on the error detection result of each column corresponding to the first and second levels. The signal is corrected.
[0013]
In addition, the first of the present invention 4 In the display device having the configuration, in the first configuration, the detection result and the N types of levels when the image signals to be displayed of N types of levels (3 ≦ N ≦ number of display gradations) are respectively input. Error correction means for outputting a difference from the reference detection result corresponding to the error detection result as the error detection result, wherein the correction means is configured such that the level of the image signal to be displayed is two adjacent levels of the N types of levels. The image signal to be displayed is corrected based on the error detection result of each column corresponding to the two adjacent levels.
[0014]
In addition, the first of the present invention 5 In the display device having the configuration described above, in the first configuration, the correction unit is configured to display the display based on the error detection result of each column when all possible levels of the image signal to be displayed are input. This corrects the image signal to be corrected.
[0016]
Furthermore, the present invention 6 In the display device having the configuration of 3 ~ 5 In any of the configurations, memory means for holding the error detection result is provided.
[0017]
According to another aspect of the invention, a display panel is connected to a pixel matrix circuit that supplies a drive current to a light emitting element of each pixel based on a signal current supplied in accordance with an image signal to be displayed, and the pixel matrix circuit. A signal line for supplying the signal current to the pixel matrix circuit, and a signal line drive for outputting the image signal to be displayed to the signal line as the signal current flowing between the power source and the signal line. And signal current detection means for detecting the signal current supplied to the signal line in each column of the pixel matrix circuit when the signal line driving means outputs the signal current and sequentially outputting the detection result With In the display panel, the signal current detecting means includes a switch circuit having one end connected to each of the signal lines of each column and provided for each column, and a current having the other end of the switch circuit connected in common. A switch control means for controlling the detection circuit and the switch circuit to be sequentially turned on, and the pixel matrix circuit is scanned by the scanning means during the writing operation to the pixel matrix circuit; When the signal current to be output flows between the power source and the signal line through the power supply connection portion and the signal current is detected by the signal current detection means, the scanning means is stopped and the pixel matrix is stopped. The signal current does not flow through the circuit, and the switch circuit sequentially connects the signal line and the current detection line to output from the signal line driving means. The signal current of each column being is detected appeared in the current detection line Is.
[0018]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a display device according to Embodiment 1 of the present invention. In the figure, 1 is a shift register circuit, 2R, 2G, and 2B are R, G, and B input signal lines to which analog image signals of RGB colors are supplied, 3 is a data line drive circuit, and 4 is a data line (Signal line) 5 is a pixel matrix in which RGB color pixels are arranged in a matrix, 6R, 6B, and 6G are R, G, and B pixel circuits, 7 is a pixel, 8 is a vertical scanning circuit, and 9 is data. Line drive current detection circuit, 10 switch circuit, 11 current detection line, 12 select circuit, 13 shift register circuit, 14 current-voltage conversion circuit, 15 organic EL display panel, 16 D / A conversion circuit , 17 is a data correction circuit, 18 is a memory circuit, 19 is a memory control circuit, 20 is an error detection circuit, and 21 is an A / D conversion circuit.
[0019]
Here, for example, a case where 260,000 colors are displayed using 6-bit image data of each color of R (Red), G (Green), and B (Blue) will be described. Further, the figure shows a configuration for two RGB columns, and the subscript m indicates that it corresponds to, for example, the m-th RGB column (a set of RGB columns) from the left.
The shift register circuit 1, the data line driving circuit 3, the pixel circuits 6R, 6G, and 6B, the vertical scanning circuit 8, and the data line driving current detection circuit 9 are built in the organic EL display panel 15. That is, for example, these circuits are formed by low-temperature polycrystalline silicon TFTs formed on a glass substrate, and an organic EL layer is formed on the pixel electrodes (not shown) of the pixel circuits 6R, 6G, and 6B by vapor deposition or the like. ing.
[0020]
Next, the operation will be described. In the first embodiment, a display mode for performing display based on input digital image signals R [5..0], G [5..0], B [5..0], and each data line And a data line driving current detection mode in which a difference from a predetermined reference value REF is stored in the memory circuit 18 as an error signal. First, the operation in the display mode will be described below.
[0021]
Image data R [5..0], G [5..0], B [5..0] to be displayed input from a controller circuit (not shown) are subjected to predetermined correction by the data correction circuit 17. After being performed (the correction method will be described later), it is converted into an analog current by the D / A conversion circuit 16 and supplied to each color input signal line 2R, 2G, 2B.
On the other hand, a start pulse STH and a shift clock CLKH are input to the shift register circuit 1 from a controller circuit (not shown) at a predetermined timing, and the shift pulses SH (0),..., SH (m),. -Generate SH (M-1) sequentially and output it to the data line drive circuit 3.
[0022]
The data line driving circuit 3 of each column receives the input signal lines 2R, SH (M-1) by the shift pulses SH (0),..., SH (m),. The analog currents AR, AG, AB for one line display corresponding to the image to be displayed supplied to 2G, 2B are sequentially sampled, and the current flowing through the driving TFT at that time is held by the capacitor connected to the gate.
Here, for example, as shown in FIG. 2, the data line driving circuit 3 includes two-system A / B current source circuits 32a and 32b, gate circuits 31a and 31b, and a switch circuit 30, and includes input signal lines 2R and 2G. 2B, the current write operation for writing (sampling) the analog current input to 2B and the current output operation for reproducing the written analog current and outputting it to the data line 4 are complementarily repeated for each line period. . In the present embodiment, each data line driving circuit 3 drives the data line 4 so as to draw a current. Here, this current drawing operation is expressed as a current output for convenience.
[0023]
In the figure, 30 is a switch circuit for switching the outputs of the two-system A / B current source circuits 32a and 32b, and includes n-type TFTs 300a and 300b. 31a and 31b are gate circuits that output control signals to the current source circuits 32a and 32b in response to the system A output enable signal EN_A, the system B output enable signal EN_B, and the shift pulse SH (m) from the shift register circuit 1. Here, it is assumed that AND circuits 310a, 310b, 311a, 311b and OR circuits 312a, 312b are included.
[0024]
The system A current source circuit 32a includes n-type TFTs 320a, 322a, and 323a, a capacitor 321a, a p-type TFT 324a, and a dummy load 325a. The TFT 320a is a driving transistor for driving the data line 4, and its drain is connected to the source of the TFT 300a, its gate is connected to one end of the capacitor 321a, and its source is grounded. The other end of the capacitor 321a is grounded.
The drain of the TFT 322a is connected to the drain of the TFT 320a, the gate is connected to the gate of the TFT 323a and the output of the AND circuit 310a, and the source is connected to the gate of the TFT 320a and the capacitor 321a.
[0025]
The drain of the TFT 323a is connected to the input signal lines 2R, 2G, and 2B, and the source is connected to the drain of the TFT 320a. The drain of the TFT 324a is connected to the drain of the TFT 320a, the gate is connected to the output of the AND circuit 311a, and the source is connected to the power supply VDD via the dummy load 325a.
Further, the system B current source circuit 32b is configured similarly to the system A current source circuit 32a.
[0026]
For example, when the system A output enable signal EN_A is inactive (“L” level) and the system B output enable signal EN_B is active (“H” level), the output signal of the AND circuit 310a corresponds to the shift pulse SH (m). To “H” level, and the TFTs 322a and 323a of the system A current source circuit 32a are made conductive. As a result, the drain and gate of the TFT 320a are connected to form a diode connection state. On the other hand, the analog image signal currents AR, AG, AB supplied via the input signal lines 2R, 2G, 2B flow between the drain and source of the TFT 320a via the TFT 323a and are connected to the gate via the TFT 322a. The capacitor 321a is charged.
[0027]
When the sampling pulse SH (m) of the column becomes “L” level, the TFTs 322a and 323a are turned off, and the supply of the analog image signal currents AR, AG, and AB to the TFT 320a is terminated, but the gate voltage of the TFT 320a is It is held by the capacitor 321a.
When the system A output enable signal EN_A becomes active (“H” level), the driving TFT 320a responds to the potential held at the gate by the capacitor 321a when the analog image signal current is supplied through the TFT 300a. The data line 4 is driven by flowing current from the drain.
[0028]
At this time, during the period from the end of the current supply from the input signal lines 2R, 2G, 2B until the system A output enable signal EN_A becomes active ("H" level) and drives the data line 4, the TFT 320a is sucked in. When the current path is interrupted, the drain potential of the TFT 320a decreases, and the charge held in the capacitor 321a leaks through the TFT 320a and the TFT 322a. This means that the gate voltage of the TFT 320a gradually decreases and the sink current (drain-source current) decreases, and the input signal line drive current sucked from the input signal line gradually decreases. It causes uneven display.
[0029]
Therefore, a TFT 324a and a dummy load 325a are provided. The source of the TFT 324a is connected to the dummy load 325a, and the dummy load 325a is further connected to the power supply VDD. Here, the OR circuit 312a takes the logical sum (OR) of the system A output enable signal EN_B and the current detection identification signal DET (active ("H" level) in the current detection mode), and the output signal and the shift pulse SH A logical product (AND) with (m) is output by the AND circuit 311a, thereby controlling the conduction of the TFT 324a.
[0030]
Thus, in the display mode, when the driving TFT 320a does not drive the data line 4 via the TFT 300a, and when no current is supplied by the input signal lines 2R, 2G, and 2B, the drain of the TFT 320a passes through the TFT 324a and the dummy load 325a. By being connected to the power supply VDD, a current flows through the TFT 320a, and the sink current path is not interrupted. Accordingly, it is possible to prevent the gate potential of the TFT 320a from gradually decreasing due to leakage of the charge of the capacitor 321a.
The system B current source circuit 32b operates similarly to the system A current source circuit 32a, and drives the data lines 4 in a complementary manner.
[0031]
Next, the pixel circuits 6R, 6G, and 6B will be described.
FIG. 3 is a diagram illustrating the configuration of the pixel circuits 6R, 6G, and 6B. In the figure, 60 and 61 are p-type TFTs, 62 and 63 are n-type TFTs, 64 is a capacitor, and 65 is an organic EL light emitting element. First, in the write operation via the input signal line, when the scan line B is at the “H” level, the scan line A is at the “H” level, and the input signal line drive current is supplied via the signal line (data line 4). Sucked from the input signal line driving circuit 3. The gate potential corresponding to the input signal line drive current flowing in the TFT 60 at this time is held by the capacitor 64.
[0032]
In the EL light emitting element driving operation, when the scan line B becomes “L” level and the scan line A subsequently becomes “L” level, the gates of the TFTs 60 and 61 are connected, so that the TFTs 60 and 61 are connected. A current mirror circuit is configured, and a current corresponding to the gate potential held in the capacitor flows between the source and drain of the TFT 61, and the drain of the TFT 61 is connected to the anode of the organic EL light-emitting element 65. It becomes a drive current of the light emitting element 65. The organic EL light emitting element 65 emits light with a light emission intensity corresponding to the drive current. Since the gate voltage of the TFT 61 is held by the capacitor 64, the drive current continues to flow through the organic EL light emitting element 65 until the scan lines A and B are scanned in the next frame period. Become. Further, by setting only the scan line B to the “H” level, the charge held in the capacitor 64 leaks through the TFTs 62 and 60 and the gate potential of the TFT 61 is raised, so that the TFT 61 is cut off and the organic EL emission is performed. Light emission can be stopped by stopping the drive current of the element 65.
[0033]
Returning to FIG. 1, the start pulse STV and the shift clock CLKV are input from the controller to the vertical scanning circuit 8 at a predetermined timing, and a shift pulse is generated based on the start pulse STV and the pixel circuits 6R, 6G, and 6B. A scan signal is supplied to scan line A and scan line B.
As described above, in the display mode, the current corresponding to the image for one row display supplied to the input signal lines 2R, 2G, and 2B is sequentially supplied to and supplied to the data line driving circuit 3 within one line period. The data line 4 is driven by reproducing the current in the next line period, and the current is written (supplied) to the pixel circuits 6R, 6G, and 6B. By repeating such processing for each line period, display for one screen is performed.
[0034]
Next, the operation in the data line drive current detection mode will be described.
FIG. 4 is a waveform diagram showing an operation sequence in the data line drive current detection mode. First, in the data line drive current detection mode, the supply of the start pulse STV and the shift clock CLKV from a controller circuit (not shown) is stopped (for example, both control signals are fixed at the “L” level), thereby causing a vertical scanning circuit. 8 is stopped. Thereby, the scanning of each pixel circuit 6R, 6B, 6G is stopped, and control is performed so as not to write current to each pixel circuit 6R, 6B, 6G.
On the other hand, as in the display mode, the start pulse STH and the shift clock CLKH are supplied from the controller circuit to the shift register circuit 1 at a predetermined timing, and the shift pulses SH (0),..., SH (m),. -Generate SH (M-1) sequentially.
[0035]
In addition, a 6-bit digital signal having the first level (magnitude) K1 is transmitted from the controller circuit as digital image signals R [5..0], G [5..0], and B [5..0]. Input to the correction circuit 17. At this time, the data correction circuit 17 performs bit expansion as will be described later on the input image signal, and outputs it to the D / A conversion circuit 16 as a signal of level Si (1). The D / A conversion circuit 16 outputs a digital signal of level Si (1) as an analog current Ii (1) to the input signal lines 2R, 2G, 2B of the organic EL panel 15.
[0036]
At this time, the system A output enable signal EN_A is input from the controller as inactive ("L" level) and the system B output enable signal EN_B is active ("H" level), and is generated by these output enable signals and the shift register. In the same manner as in the display mode, the shift pulse is supplied to the input signal lines 2R, 2G, and 2B sequentially between the drain and source of the driving TFT 320a in the system A current source circuit 32a of the data line driving circuit 3 of each column. The analog current Ii (1) flows. Then, the current writing operation by writing (sampling) the analog current Ii (1) to the system A current source circuits 32a of all the columns is completed.
[0037]
Thereafter, the operation shifts to a current detection operation for detecting the drive current of the data line 4. In the current detection operation, the system A output enable signal EN_A becomes active (“H” level), the system B enable signal EN_B becomes inactive (“L” level), and the system A current source circuit 32a performs the current output operation.
In the drive current detection operation for the data line 4 connected to the R pixel circuit 6R, as shown in FIG. 4, a start pulse STT and a shift clock are sent to the shift register 13 from a controller (not shown) at a predetermined timing. CLKT is input, and shift pulses ST (0),..., ST (m),..., ST (M−1) are sequentially generated and input to the select circuit 12.
[0038]
FIG. 5 shows the configuration of the data line drive current detection circuit. Data lines 4 connected to the R pixel circuit 6R, the G pixel circuit 6G, and the B pixel circuit 6B (hereinafter referred to as R data line 4R, G data line 4G, and B data line 4B, respectively). Are connected to the sources of the TFTs 50R, 50G, and 50B, and each TFT constitutes the switch circuit 10. The drains of the TFTs 50R, 50G, and 50B are connected to a common current detection line 11, and the gates of the TFTs 50R, 50G, and 50B are connected to the outputs of AND gates 51R, 51G, and 51B that constitute the select circuit 12, respectively. ing.
[0039]
The AND gate 51R receives the shift pulse ST (m) corresponding to the column and the R select signal SLR. When both signals are active (“H” level), the output signal of the AND gate 51R is “ Control is performed so that the TFT 50R becomes conductive when it becomes the H "level.
Similarly, shift pulses ST (m) and G and B select signals SLG and SLB are connected to the AND gates 51G and 51B, respectively, and control the conduction of the TFTs 50G and 50B.
Here, as shown in FIG. 4, first, the R select signal SLR is activated ("H" level) from a controller (not shown), and the start pulse STT and the shift clock CLKT of the shift register 13 are input. The TFTs 50R connected to the R data lines 4R are sequentially turned on. That is, the shift register circuit 13 and the select circuit 12 are controlled so that the switch circuit 10 is sequentially turned on.
[0040]
On the other hand, a current mirror circuit 55 is connected to the current detection line 11, and the drive current of each R data line 4R sequentially flows between the source and drain of the p-type TFT 52 constituting the input side thereof. . A corresponding current flows between the source and drain of the p-type TFT 53 constituting the output side of the current mirror circuit 55 and also flows to the current detection resistor element 54 connected to the outside of the organic EL display panel 15. Thus, the detection voltage value DO is converted and output to the A / D conversion circuit 21. That is, the current mirror circuit 55 and the detection resistance element 54 constitute a current-voltage conversion circuit 14 that amplifies the data line drive current at a predetermined current ratio and converts it into a voltage.
[0041]
Here, since the current value for driving the data line is generally a minute current of the order of μA or less, when the current mirror circuit 55 outputs the current as it is, the voltage is used to ensure the detection sensitivity of the A / D conversion circuit 21 at the subsequent stage. If an attempt is made to increase the value, the resistance value of the current detection resistor element 54 will also increase correspondingly, and it will be susceptible to noise. Therefore, for example, it is desirable to set the transistor size ratio of the TFTs 52 and 53 constituting the current mirror circuit 55 so that the input-output current ratio of the current mirror circuit 55 is about several tens of times. As a result, the resistance value of the current detecting resistance element 54 can be lowered, and the influence of noise can be made difficult.
Further, one end is connected to each data line of each column, and the switch circuit provided for each column is controlled to be sequentially conducted so that the signal current of each column appearing on the current detection line is sequentially output as a detection result. Since it comprised, the number of current detection lines can be reduced and the number of terminals for taking out the current detection result from the organic EL display panel 15 can also be reduced.
[0042]
The result (detection voltage value DO) of detecting the drive current of each R data line 4R in this way is sequentially converted into a digital detection signal by the A / D conversion circuit 21 and input to the error detection circuit 20. In the error detection circuit 20, a difference from the reference level Ref (1) corresponding to the first input level K1 is calculated as an error signal, and the error signal is controlled by the memory control circuit 19 so that the memory circuit 18 is controlled. Stored at a predetermined address.
Similarly, as shown in FIG. 4, the digital image signal of the first level K1 is output to the input signal lines 2R, 2G, 2B of the organic EL panel 15 as the analog current Ii (1), and the data line of each column The current write operation to the system A current source circuit 32a of the drive circuit 3 is sequentially performed.
[0043]
Then, the select signal SLG is activated ("H" level), the drive current of the G data line 4G is sequentially detected, and stored in the memory circuit 18 as an error signal.
Further, after sequentially performing the current writing operation to the system A current source circuit 32a of the data line driving circuit 3 of each column, the select signal SLB is made active ("H" level), and the driving current of the B data line 4B is changed. The signals are sequentially detected and stored in the memory circuit 18 as error signals.
[0044]
As described above, the driving current when the data line of each column is driven by the current corresponding to the first input level K1 by the system A current source circuit 320a of the data line driving circuit 3 by the data line driving current detection circuit 9. The detection result is stored in the memory circuit 18 as an error signal.
Next, as shown in FIG. 4, the digital image signal of the second input level K2 is sent from the controller to the input signal lines 2R, 2G, 2B as an analog current in the D / A conversion circuit 16 via the data correction circuit 17. By inputting and repeating the same operation as described above, each data line driving current by the system A current source circuit 320a is detected, and the detection result is stored in the memory circuit 18 as an error signal.
[0045]
Further, the output enable signal EN_A is active ("H" level), the output enable signal EN_B is inactive ("L" level), and the data lines in each column are connected to the system B current with a current corresponding to the first input level K1. After writing to the source circuit 320b, the output enable signal EN_A is inactive ("L" level), EN_B is active ("H" level), and the drive current when each data line is driven by the system B current source circuit 320b Is detected by the data line drive current detection circuit 9 and the result is stored in the memory circuit 18 as an error signal.
[0046]
Then, the current corresponding to the second input level K2 is input to the input signal lines 2R, 2G, and 2B, and the same operation is repeated to drive currents when the data lines are driven by the system B current source circuit 320b. Is detected by the data line drive current detection circuit 9 and the result is stored in the memory circuit 18 as an error signal.
As described above, in the data line drive current detection mode, the data line drive current of each column is detected by the system A and B current source circuits 320a and 320b when the first and second levels are input, The result is stored in the memory circuit 18 as an error signal.
[0047]
Now, during the current detection period in the data line drive current detection mode, except when the data lines 4R, 4G, and 4B in the column are connected to the TFT 52 of the current mirror circuit 55 through the TFTs 50R, 50G, and 50B by the shift pulse ST. In the capacitor 321a and 321b connected to the gates of the driving TFTs 320a and 320b, the drain potential of the TFT 320a decreases, and the data line is not connected to the load and the current suction path is cut off. Thus, the charge held in the capacitor 321a leaks. That is, during the current detection period, the gate voltage of the TFT 320a gradually decreases, and the sink current (drain-source current) decreases. Here, since the current is sequentially detected from the leftmost data line, the current is written to the driving TFTs 320a and 320b as the data line goes to the right side, and then the load is connected to the data line. Since the time until the signal is output (sucked) is long, the output current of the driving TFT, that is, the data line driving current decreases.
[0048]
Therefore, in the first embodiment, during the current detection period in the data line drive detection mode, as shown in FIG. 4, not only the shift register circuit 14 but also the shift register circuit 1 is supplied with the start pulse STH and A shift clock SH (0) equivalent to the shift pulse ST (0),..., ST (m),. , SH (m),..., SH (M−1).
At this time, since the current detection identification signal DET is active ("H" level), the shift pulses SH (0), ..., SH (m), ..., SH (M-1) are AND circuits 311a. 311b is controlled to control the gate potential of the TFTs 324a and 324b.
[0049]
That is, even during the current detection period in the data line drive current detection mode, the output of the drive TFTs 320a and 320b is output from the TFT 324a in a period other than when the data line drive current detection circuit 9 detects the drive current of the data line in the column. 324b and the dummy loads 325a and 325b are connected to the power supply VDD.
Thus, the dummy loads 325a and 325b are connected to the outputs of the driving TFTs 320a and 320b to form a current path until the TFT 52 of the current mirror circuit 55 is connected to the data line as a load and forms a current path. In addition, it is possible to prevent the data line driving current from being lowered due to leakage of charges held in the capacitors 321a and 321b, and it is possible to accurately detect the data line driving current across each column.
[0050]
Next, a method for correcting the digital image signal input based on the error signal E as the detection result of the data line drive current stored in the memory 18 as described above will be described. In the data line drive current detection mode, as described above, the data line drive current output by the system A and system B current sources 32a and 32b of the data line drive circuit corresponding to the first and second image signal levels. The error signal is detected for each color column. Here, based on the error signal of the data line drive current by the current source circuit of either A / B system of a certain column, A case where the corresponding image signal is corrected will be described.
[0051]
FIG. 6 is a characteristic diagram showing the relationship between the image signal level input from the controller and the current detection level detected by the data line driving current detection circuit 10 in the data line driving current detection mode. In the figure, a dotted line is a data line having a current detection level larger than the reference levels Ref (1) and Ref (2), and a one-dot chain line is a data line having a current detection level smaller than the reference levels Ref (1) and Ref (2). An example is shown. In the data line drive current detection mode, the error detection signal E (1) between the data line drive current detection level D (1) and the reference level Ref (1) corresponding to the first input level K1, and the second input The data line driving current detection level D (2) corresponding to the level K2 and the error detection signal E (2) between the reference level Ref (2) are stored in the memory 18 for each data line.
Thus, only the difference between the detection results D (1) and D (2) corresponding to the first and second levels and the reference levels Ref (1) and Ref (2) in the data line drive current detection mode. The error detection signals E (1) and E (2) are stored in the memory circuit 18, and the error detection signals E (1) and E (2) are read from the memory circuit 18 and used to correct the input image signal in the display mode. Therefore, the memory capacity for holding the detection result can be reduced.
[0052]
At this time, the data correction circuit 17 drives the data line when the image signal level (grayscale level) is k based on the error detection signals E (1) and E (2) corresponding to each data line. The current detection error E (k) is obtained by linear prediction (linear interpolation) shown in the following equation. Here, for example, since the image signal has 6 bits, a value of 0 ≦ k ≦ 63 is obtained.
First, in the data correction circuit 17, for example, the input 6-bit image signals R [5..0], G [5..0], and B [5..0] are converted into 10-bit signals r [9..0]. 0], g [9..0], and b [9..0] are converted in advance to perform bit extension. Here, linear conversion of the conversion coefficient α shown in the following equation (1) is performed as the signal level so (k) after conversion.
[0053]
so (k) = α · k (1)
Here, for the sake of simplicity, α = 16 is assumed if conversion is performed by left 4-bit shift.
[0054]
Based on the error detection signals E (1) and E (2), the error signal E (k) at the image signal level k is obtained by interpolation using the following equation (2).
E (k) = ((E (2) −E (1)) / (K2−K1)) · (k−K1) + E (1) (2)
Here, the error signal corresponding to the image signal level on which the error signal is detected need not be obtained by interpolation, and may be used as it is as an error signal.
[0055]
Next, a correction value e (k) for the image signal is obtained by the following equation (3).
e (k) = E (k) / G (3)
G: conversion coefficient of the output level of the A / D conversion circuit 21 with respect to the output level of the data correction circuit 17.
[0056]
Then, the following expression (4) is performed on the converted so (k).
Si (k) = so (k) -e (k) (4)
However, Si (k): the output signal level of the data correction circuit 17 at the input image signal level k.
[0057]
Thus, in the first embodiment, it may be considered that a kind of feedback control system as shown in FIG. 7A is configured for the drive current of each data line (each column). That is, in the data line drive current detection mode, the processing system shown in FIG. 7B is configured, and two levels of input image signals (levels K1, K2) are input to the data correction circuit 17 from the controller circuit. For example, the signal is converted into a 10-bit signal (level so (1), so (2)) according to the equation (3), and D / A is output as the output signal (first level K1, second level K2) of the data correction circuit 17 It is sent to the conversion circuit 16. After being converted into an analog current by the D / A conversion circuit 16 (conversion coefficient is G1), it is input to the organic EL display panel 15, and the data line is driven as the data line drive current Id by the data line drive circuit 3. . Here, since the variation in the characteristics of the data line driving circuit 3 appears as the variation in the data line driving current, the conversion coefficient of the data line driving circuit 3 varies from column to column.
[0058]
At this time, as described above, the vertical scanning circuit 8 has stopped operating, and the data line drive current Id is detected by the data line drive current detection circuit 9 without being supplied to the pixel circuit 7 (conversion coefficient). G3), after A / D conversion by the A / D conversion circuit 21 as a current detection output signal (level D (1), D (2)) (conversion coefficient is G4), to the error detection circuit 20 Entered.
In the error detection circuit 20, the difference between the current detection signals of the two levels D (1) and D (2) and the reference levels Ref (1) and Ref (2) corresponding to the first and second levels, respectively. And stored in the memory circuit 18 as error detection signals E (1) and E (2).
[0059]
As described above, such processing is performed on all the data lines, and the respective error detection signals E (1) and E (2) when the first and second level signals are input to each data line. ) Is stored in the memory circuit 18.
In the display mode, as described above, the current corresponding to the data to be displayed for each RGB column is sequentially written to the data line driving circuit 3. At this time, the processing system shown in FIG. 7C is configured for each data line. From the error detection signals E (1) and E (2) in the data line read from the memory circuit 18, the processing system shown in FIG. According to the equation (2), an error signal E (k) corresponding to the image signal level to be displayed is obtained by linear prediction (linear interpolation). The conversion coefficient β of linear interpolation based on the expression (2) in the present embodiment is 1. Then, an error signal e (k) whose level is converted is obtained in accordance with the above-described equation (3).
[0060]
Here, the conversion coefficient G of the output level of the A / D conversion circuit 21 with respect to the output level of the data correction circuit 17 is:
G = G1, G2, G3, G4
Indicated by
G2: conversion coefficient of the data line driving circuit 3 obtained from the reference levels Ref (1) and Ref (2).
[0061]
On the other hand, the image signal input from the controller is bit-extended according to the above equation (1) according to the level thereof, and D / A as correction data Si (k) in which the error is corrected according to the above equation (4). It is sent to the conversion circuit 16. Then, after being converted into an analog current in the D / A conversion circuit 16, it is input to the organic EL display panel 15 and sequentially supplied to the data line driving circuit 3 in each column as a current corresponding to the data to be displayed with the error corrected. Written.
Then, in the next line period, each data line driving circuit 3 has data line driving currents IR (1), IG (1), IB (1),..., IR (m), IG (m), IB ( m),..., IR (M-1), IG (M-1), and IB (M-1) are output to each data line 4 at a timing common to each column.
[0062]
As described above, in the first embodiment, the difference between the detection result when the first and second level input image signals are input and the reference detection result corresponding to the first and second levels is calculated. Since the image signal to be displayed is corrected based on the error detection result, the error of the signal line drive current when the image signal other than the first and second levels is input is easily obtained by linear interpolation. Therefore, variation in data line driving current due to variation in characteristics of TFTs forming the data line driving circuit can be suppressed, and display unevenness can be improved.
[0063]
Embodiment 2. FIG.
In the first embodiment, the correction is made by the two error detection signals E (1) and E (2) on the assumption that the data line driving current for the input image signal has a linear characteristic.
However, the data line driving current with respect to the input image signal may have a non-linear characteristic relationship, particularly when performing display gamma correction. A mode in which the data line driving current with respect to the input image signal has nonlinear characteristics will be described below as a second embodiment.
[0064]
FIG. 8 is a diagram showing the relationship between the image signal level input from the controller and the current detection level detected by the data line driving current detection circuit 10 in the data line driving current detection mode in the second embodiment.
In the data correction circuit 17, the reference levels Ref (0), Ref () are preliminarily set for possible values of the image signal level k (all integer values of 0 ≦ k ≦ 63 if the image signal is 6 bits). 1), ..., Ref (63) is set in advance.
[0065]
Based on the error detection signals E (1) and E (2), the error signal E (k) at the image signal level k is obtained by interpolation according to the following equation (5).
E (k) = (E (2) −E (1)) × ((Ref (k) −Ref (1)) / (Ref (2) −Ref (1))) + E (1). (5)
Here, the error signal corresponding to the image signal level on which the error signal is detected need not be obtained by interpolation, and may be used as it is as an error signal.
Since other configurations and operations are the same as those described in the first embodiment, detailed description thereof is omitted.
[0066]
As described above, in the second embodiment, the reference detection results are set in advance for the possible values of the image signal level, and the image signals to be displayed at the first and second levels are respectively input. Since the difference between the detection result at the time and the reference detection result of the corresponding image level is used as an error detection result, the image signal to be displayed is corrected based on the difference, so that the image signals other than the first and second levels The error of the signal line drive current when the signal is input can be easily obtained by interpolation, and the input image signal is corrected based on the error. Therefore, the variation in the signal line drive current due to the characteristic variation of the TFT forming the signal line drive means Can be suppressed, and display unevenness can be improved. Further, since only the difference between the detection result corresponding to the first and second levels and the reference detection result is used for the correction of the input image signal, the memory capacity for holding the detection result can be reduced.
[0067]
Embodiment 3 FIG.
In the first embodiment, on the premise that the data line driving current for the input image signal has a linear characteristic, an error signal corresponding to the input image signal is obtained from the two error detection signals E (1) and E (2). It was configured to obtain by interpolation. However, the data line driving current with respect to the input image signal may have nonlinear characteristics, particularly when performing gamma correction for display. In this case, correction may be insufficient by linear interpolation using the two error detection signals in the first embodiment.
Here, a description will be given of a case where correction is performed using a multipoint error detection signal that can further improve the accuracy of correction.
[0068]
In the current detection mode according to the third embodiment, a series of writing to the data line driving circuit 3 described with reference to FIG. 4 in the first embodiment → data line driving current detection → writing error signals into the memory circuit 18. This sequence is sequentially repeated with the input image signal level as K1, K2,..., KN (3 ≦ N ≦ 63).
[0069]
FIG. 9 is a diagram showing the relationship between the image signal level input from the controller and the current detection level detected by the data line driving current detection circuit 10 in the data line driving current detection mode in the third embodiment. The figure shows a case where the image signal level k is in the interval between K1 and K2.
[0070]
In the data correction circuit 17, it is determined which of the two points among the N points where the error signal is detected is in the image signal level k.
For example, when the image signal level k is between Kn and Kn + 1, the error detection signal is obtained in the same manner as the equation (2) shown in the first embodiment or the equation (5) shown in the second embodiment. Based on E (n) and E (n + 1), the error signal E (k) at the image signal level k is obtained by interpolation according to the following equation (6) or (7).
E (k) = ((E (n + 1) -E (n)) / (Kn + 1-Kn)). (K-Kn) + E (n) (6)
E (k) = (E (n + 1) −E (n)) × ((Ref (k) −Ref (n)) / (Ref (n + 1) −Ref (n))) + E (n) ... Formula (7)
The error signal corresponding to the image signal level for which the error signal is detected does not need to be obtained by interpolation, and may be used as it is as an error signal.
Since other configurations and operations are the same as those described in the first embodiment, detailed description thereof is omitted.
[0071]
As described above, in the third embodiment, the detection result when each of the N types of input image signals (3 ≦ N ≦ the number of display gradations) is input and the reference detection result corresponding to the N types of levels. And the difference between the input image signal level and the input image signal level is determined in which section between two adjacent levels of the N types of levels, and corresponding to the two adjacent levels. The image signal to be displayed is corrected based on the error detection result of each column. Thereby, even when the data line driving current with respect to the input image signal has a nonlinear characteristic relationship, an error of the data line driving current when an image signal other than N types of levels is input is easily obtained by linear interpolation. Since the input image signal is corrected based on this, variation in the data line drive current due to variation in characteristics of the TFTs forming the data line drive circuit can be suppressed, and display unevenness can be improved.
[0072]
Embodiment 4 FIG.
In each of the above first to third embodiments, the error signal corresponding to the input image signal is obtained by interpolation from the error detection signals of two points or multiple points. In the fourth embodiment, an error signal corresponding to all possible values of the input image signal level is detected so that the image signal can be corrected with higher accuracy.
[0073]
In the current detection mode according to the fourth embodiment, the series of writing to the data line driving circuit 3 described with reference to FIG. 4 in the first embodiment → data line driving current detection → writing error signals to the memory circuit 18. This sequence is sequentially repeated over all possible values of the input image signal level (similar to Embodiments 1 to 3 above, if the input image signal is 6 bits, all integer values of 0 ≦ k ≦ 63). It will be. Then, each error signal corresponding to the detected image signal is stored in the memory circuit 18.
[0074]
In the display mode, the error signal interpolation process according to each of the first to third embodiments is omitted, but the other configuration and operation are the same as those described in the first embodiment, and thus detailed description thereof is omitted. To do.
Further, with respect to the configuration of the processing system described with reference to FIG. 7 in the first embodiment, the interpolation processing block according to the equation (2) is simply omitted, and the rest is the same as in the second, third, and third embodiments. The configuration is the same as that described above.
[0075]
As described above, in the fourth embodiment, the image signal to be displayed is corrected based on the error detection result of each column when all possible levels of the image signal to be displayed are input. Image signal can be corrected with higher accuracy, and variation in data line drive current due to variation in characteristics of TFTs forming the data line drive circuit can be more effectively suppressed, thereby improving display unevenness. Can do.
[0076]
Embodiment 5. FIG.
As described in the first embodiment, the organic EL display panel 15 used in the display device includes the shift register circuit 1, the data line driving circuit 3, the pixel circuits 6R, 6B, and 6G, the vertical scanning circuit 8, and the data line driving. A current detection circuit 9 is built in, and these circuits are formed by, for example, a low-temperature polycrystalline silicon TFT on a glass substrate. Further, an organic EL layer is formed on the pixel electrodes (not shown) of the pixel circuits 6R, 6G, and 6B by vapor deposition or the like. A substrate having a circuit composed of low-temperature polycrystalline silicon TFTs is generally called an array substrate.
When the organic EL display panel 15 is manufactured, the array substrate is formed in a step before the organic EL layer is formed on the pixel electrode, for example, depending on the degree of variation in the data line driving current output from the data line driving circuit 3. It is possible to inspect non-defective / defective products.
That is, in the non-defective product inspection in the array substrate manufacturing process, an image signal and a control signal necessary for the current detection mode of the first embodiment are input from an external inspection device, and the data line of each column detected by the data line detection circuit 9 is detected. When the deviation of the drive current detection level is within a predetermined range, the array substrate can be determined as a non-defective product, and when it is outside the predetermined range, it can be determined as a defective product.
[0077]
In the second to fourth embodiments, a 6-bit input image signal is converted to a 10-bit signal by performing bit extension instead of linear conversion, for example, gamma correction processing by referring to a lookup table. Is also possible.
[0078]
In the first to fourth embodiments, when the image signal level k = 0, the data line driving current from the data line driving circuit 3 is not supplied to turn off the organic EL element from the viewpoint of increasing the contrast ratio. It is desirable to control as follows. For this reason, when the image signal level k = 0, that is, in the case of all black display, it may not be particularly necessary to correct the variation in the data line driving current. In such a case, when the image signal level k = 0, the image signal correction processing in the data correction circuit 17 may not be performed.
[0079]
In the second to fourth embodiments, the case where the data line driving current for the input image signal has a nonlinear characteristic has been described. However, in consideration of the required correction system, a part of the input image signal is used. It is also possible to correct by the linear interpolation shown in the first embodiment, that is, take a form combined with the first embodiment.
Moreover,
[0080]
The memory circuit 18 is a nonvolatile memory such as an EEPROM (Erasable Programmable Read Only Memory) or an EEPROM (Electrically Erasable Programmable Read Only Memory), or a volatile memory such as an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory). Can be used.
[0081]
In the case of using a non-volatile memory, for example, the current detection mode may be executed at the time of shipment of the device, and the error detection signal of each column may be written into the memory circuit 18. When a volatile memory is used, for example, a current detection mode may be executed when the apparatus is started, and an error detection signal for each column may be written to the memory circuit 18.
[0082]
The D / A conversion circuit 16, the data correction circuit 17, the memory circuit 18, the memory control circuit 19, the error detection circuit 20, and the A / D conversion circuit 21 are configured as an ASIC (Application Specific IC) integrated with the controller. Is possible.
The operations of the data correction circuit 17 and the error detection circuit 20 can also be performed by software processing using a microprocessor or the like.
[0083]
Further, in each of the above first to fifth embodiments, the light emitting element has been described as an organic EL element. However, other current control type elements such as LEDs (Light Emitting Diodes) and FE (Field Emitters) whose light emission luminance is changed by current. It goes without saying that the present invention can also be applied to a display device using the above.
[0084]
【The invention's effect】
The display device according to the first configuration of the present invention detects a signal current supplied to the signal line of each column of the pixel matrix circuit, sequentially outputs the detection result, and an image signal to be displayed based on the detection result Therefore, variations in signal line drive current due to variations in characteristics of TFTs forming the signal line drive means can be suppressed.
First of the present invention 1 The display device with the configuration of ,each Since one end is connected to each of the signal lines in the column and the switch circuit provided for each column is sequentially turned on, the number of current detection lines can be reduced, and the detection result is output from the display panel. In this case, it is possible to reduce the number of extraction terminals.
First of the present invention 1 Display device Is Since the scanning means is stopped when the signal current is detected by the signal current detection means, it is possible to accurately and reliably detect the signal line drive current by avoiding the shunting of the signal line drive current to the pixel circuit. Become.
[0086]
First of the present invention 2 A display device having the above configuration is 1 In the configuration, the signal current detection means is configured to amplify the signal current of each column appearing on the current detection line by a predetermined current ratio, and then convert it to a voltage and output it, so that the output impedance can be lowered, It is possible to detect and output the signal line drive current with high accuracy by reducing the influence of noise.
[0087]
First of the present invention 3 The display device having the above configuration is the same as the first configuration. No The difference between the detection result when the image signals to be displayed at the first and second levels are respectively input and the reference detection result corresponding to the first and second levels is used as an error detection result based on the difference. Since the image signal to be displayed is corrected, an error of the signal line drive current when an image signal other than the first and second levels is input can be easily obtained by linear interpolation. It is possible to suppress variations in the signal line drive current due to variations in the characteristics of the TFTs forming the.
[0088]
First of the present invention 4 The display device according to the configuration corresponds to the detection result and N types of levels when the image signals to be displayed of N types (3 ≦ N ≦ number of display gradations) are input in the first configuration. The difference from the reference detection result is an error detection result, and the image signal level to be displayed is determined in which section between two adjacent levels among the N types of levels, and the adjacent 2 Since the image signal to be displayed is corrected based on the error detection result of each column corresponding to one level, particularly when the signal line driving current with respect to the input image signal has a nonlinear characteristic relationship, N types The signal line drive current error when an image signal other than this level is input can be easily obtained by linear interpolation, and signal line drive due to variations in characteristics of TFTs forming the signal line drive means It is possible to suppress variations in flow.
[0089]
First of the present invention 5 The display device according to the configuration is configured to correct the image signal to be displayed based on the error detection result of each column when all the possible levels of the image signal to be displayed are input in the first configuration. Therefore, it is possible to correct the input image signal with higher accuracy, and it is possible to more effectively suppress variations in the signal line driving current due to variations in characteristics of the TFTs forming the signal line driving means.
[0091]
First of the present invention 6 A display device having the above configuration is 3 ~ 5 In any of the configurations, the memory means for holding the error detection result is provided, so that the operation mode for writing the error detection result of the signal current supplied to the signal line of each column to the memory means and the image signal to be displayed Can be temporally separated from the operation mode in which the image is displayed by the correction means, and the former operation mode can be executed when the apparatus is activated.
[0092]
A display panel according to the present invention includes a pixel matrix circuit that supplies a drive current to a light emitting element of each pixel based on a signal current supplied according to an image signal to be displayed, and a power source connected to the pixel matrix circuit. A signal line for supplying the signal current to the pixel matrix circuit; Scanning means for sequentially scanning the pixel matrix circuit; Signal line driving means for outputting the image signal to be displayed to the signal line as the signal current flowing between the power source and the signal line, and the signal current supplied to the signal line in each column of the pixel matrix circuit Detecting when the signal line driving means outputs the signal current, comprising signal current detection means for sequentially outputting as a detection result, The signal current detection means includes a switch circuit having one end connected to each signal line of each column and provided for each column, a current detection line having the other end of the switch circuit connected in common, and the switch Switch control means for controlling the circuit so as to be sequentially turned on, and at the time of writing to the pixel matrix circuit, the pixel matrix circuit is scanned by the scanning means and the signal current output from the signal line driving means Flows between the power supply and the signal line via the power supply connection portion, and when the signal current is detected by the signal current detection means, the scanning means is stopped and the signal current is supplied to the pixel matrix circuit. The signal line and the current detection line are sequentially conducted by the switch circuit, and the signal of each column output from the signal line driving means is transmitted. Current is detected appears in the current detection line Therefore, the non-defective / defective array substrate can be inspected according to the degree of variation in the signal line drive current.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a display device according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a configuration of a data line driving circuit in the display device according to the first embodiment of the present invention;
FIG. 3 is a circuit diagram showing a configuration of a pixel circuit in the display device according to the first embodiment of the present invention.
FIG. 4 is a waveform diagram showing an operation sequence in a data line drive current detection mode in the display device according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of a data line driving current detection circuit in the display device according to the first embodiment of the present invention;
FIG. 6 is a characteristic diagram showing the relationship between the input image signal level and the current detection level in the data line drive current detection mode in the display device according to the first embodiment of the present invention;
FIG. 7 is a block diagram showing a configuration of a processing system in the display device according to the first embodiment of the present invention.
FIG. 8 is a characteristic diagram showing a relationship between an input image signal level and a current detection level in a data line drive current detection mode in the display device according to the second embodiment of the present invention;
FIG. 9 is a characteristic diagram showing a relationship between an input image signal level and a current detection level in a data line drive current detection mode in a display device according to a third embodiment of the present invention.
[Explanation of symbols]
3 data line drive circuit, 4 data line (signal line), 5 pixel matrix, 8 vertical scanning circuit, 9 data line drive current detection circuit, 10 switch circuit, 11 current detection line, 12 select circuit, 13 shift register circuit, 14 Current-voltage conversion circuit, 15 organic EL display panel, 17 data correction circuit, 18 memory circuit, 20 error detection circuit.

Claims (8)

A pixel matrix circuit that supplies a drive current to the light emitting elements of each pixel based on a signal current supplied in accordance with an image signal to be displayed, a power supply connection unit that connects a power supply to the pixel matrix circuit, and the pixel matrix A signal line for supplying the signal current to the circuit, scanning means for sequentially scanning the pixel matrix circuit, and the image signal to be displayed as the signal current flowing between the power source and the signal line to the signal line. The signal line driving means for outputting and the signal current supplied to the signal lines in each column of the pixel matrix circuit are detected when the signal line driving means outputs the signal current, and sequentially output as detection results. display device comprising: a signal current detection means, based on a detection result detected by the signal current detection means and a correction means for correcting the image signal to be the display There,
The signal current detection means includes a switch circuit having one end connected to each signal line of each column and provided for each column, a current detection line having the other end of the switch circuit connected in common, and the switch Switch control means for controlling the circuit to sequentially conduct,
During the writing operation to the pixel matrix circuit, the pixel matrix circuit is scanned by the scanning unit, and the signal current output from the signal line driving unit is supplied to the power source, the signal line, and the signal line through the power source connection unit. Flows between
When the signal current is detected by the signal current detection means, the scanning means is stopped and the signal current does not flow through the pixel matrix circuit, and the signal line and the current detection line are sequentially conducted by the switch circuit. The signal current in each column output from the signal line driving means appears on the current detection line and is detected . The signal current detection means, after the signal current of each column appearing in the current detection line is amplified by a predetermined current ratio, the current into a voltage - according to claim 1, further comprising a voltage converting means Display device.   Error detection for outputting, as an error detection result, a difference between the detection result when the image signals to be displayed at the first and second levels are respectively input and the reference detection result corresponding to the first and second levels. The correction means corrects the image signal to be displayed based on the error detection result of each column corresponding to the first and second levels. Display device.   An error detection result is a difference between the detection result when the image signals to be displayed at N types of levels (3 ≦ N ≦ number of display gradations) are input and the reference detection result corresponding to the N types of levels. An error detection means for outputting, wherein the correction means determines in which section between the two adjacent levels of the N types of levels the level of the image signal to be displayed is The display device according to claim 1, wherein the image signal to be displayed is corrected based on the error detection result of each column corresponding to the two levels.   The correction means corrects the image signal to be displayed based on the error detection result of each column when all possible levels of the image signal to be displayed are respectively input. The display device according to 1. Display device according to any one of claims 3-5, characterized in that it comprises a memory means for holding the error detection result. A pixel matrix circuit that supplies a drive current to the light emitting elements of each pixel based on a signal current supplied in accordance with an image signal to be displayed, a power supply connection unit that connects a power supply to the pixel matrix circuit, and the pixel matrix a signal line for supplying the signal current to the circuit, a scanning means for sequentially scanning the pixel matrix circuit, into the signal line the image signals to be displayed as the signal current flowing between the power source and the signal line The signal line driving means for outputting and the signal current supplied to the signal lines in each column of the pixel matrix circuit are detected when the signal line driving means outputs the signal current, and sequentially output as detection results. A display panel provided with signal current detection means ,
The signal current detection means includes a switch circuit having one end connected to each signal line of each column and provided for each column, a current detection line having the other end of the switch circuit connected in common, and the scan line. Switch control means for controlling the switch circuit so as to sequentially conduct,
During the writing operation to the pixel matrix circuit, the pixel matrix circuit is scanned by the scanning unit, and the signal current output from the signal line driving unit is supplied to the power source, the signal line, and the signal line through the power source connection unit. Flows between
When the signal current is detected by the signal current detection means, the scanning means is stopped and the signal current does not flow through the pixel matrix circuit, and the signal line and the current detection line are sequentially conducted by the switch circuit. The signal current of each column output from the signal line driving means appears on the current detection line and is detected . The signal current detection means, after the signal current of each column appearing in the current detection line is amplified by a predetermined current ratio, the current into a voltage - according to claim 7, further comprising a voltage converting means Display panel.

Images