JP3892732B2 - Driving method of display device - Google Patents

Driving method of display device Download PDF

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Publication number
JP3892732B2
JP3892732B2 JP2002022835A JP2002022835A JP3892732B2 JP 3892732 B2 JP3892732 B2 JP 3892732B2 JP 2002022835 A JP2002022835 A JP 2002022835A JP 2002022835 A JP2002022835 A JP 2002022835A JP 3892732 B2 JP3892732 B2 JP 3892732B2
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Prior art keywords
voltage
period
pixel
display device
video signal
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JP2003223136A (en
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茂之 西谷
敏浩 佐藤
玄士朗 河内
秋元　　肇
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Hitachi Ltd
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Hitachi Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0243—Details of the generation of driving signals
    • G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/06—Details of flat display driving waveforms
    • G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0261—Improving the quality of display appearance in the context of movement of objects on the screen or movement of the observer relative to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/04—Maintaining the quality of display appearance
    • G09G2320/043—Preventing or counteracting the effects of ageing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0606—Manual adjustment
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/06—Adjustment of display parameters
    • G09G2320/0666—Adjustment of display parameters for control of colour parameters, e.g. colour temperature
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

Description

【０００１】
【発明の属する技術分野】
本発明は、表示装置およびその駆動方法に係り、特に、アクティブマトリクス方式の有機エレクトロルミネッセンスディスプレイの駆動方法に関する。
【０００２】
【従来の技術】
アクティブマトリクス駆動の有機エレクトロルミネッセンスディスプレイ（以下、ＡＭＯＬＥＤと記す）は、従来の液晶ディスプレイの次の世代のフラットパネルディスプレイとして期待されている。
従来、ＡＭＯＬＥＤの駆動回路としては、例えば、特開２０００−１６３０１４号公報に開示されているような、有機エレクトロルミネッセンス素子（以下、単に、ＥＬ素子という。）に電流を供給するための駆動用の薄膜トランジスタ（以下、ＥＬ駆動ＴＦＴという）、ＥＬ駆動ＴＦＴのゲート電極に接続され、映像信号電圧を保持する保持コンデンサと、前記保持コンデンサに映像信号電圧を供給するためのスイッチ用の薄膜トランジスタ（以下、スイッチＴＦＴという）からなる２トランジスタ構成の回路がもっとも基本的な画素回路として知られている。（以下、第１の従来技術という）
【０００３】
【発明が解決しようとする課題】
前記第１の従来技術である２トランジスタ構成の基本画素回路の大きな問題として、ＥＬ駆動ＴＦＴを構成する半導体薄膜（通常は、多結晶シリコン膜が使用される）の結晶性の場所毎のバラツキにより、ＥＬ駆動ＴＦＴのしきい電圧（Ｖｔｈ）や移動度（μ）が画素毎にばらつくために生じる画像の不均一性がある。
しきい電圧や移動度のバラツキは、そのまま、ＥＬ素子の駆動電流値のバラツキとなるため、発光強度がバラツキ、表示上では微細なムラとなって見えることになる。この表示ムラは駆動電流値が小さい中間調表示時に特に問題となる。
このようなＥＬ駆動ＴＦＴの特性のバラツキによる表示不均一を抑制するために、例えば、特開２０００−３３０５２７号公報には、ＥＬ駆動ＴＦＴを、完全にオフか、または完全にオン状態とする２値スイッチとして駆動し、画像の階調表示は発光の時間幅を変えることにより表示する、所謂パルス幅変調による駆動法が開示されている。（以下、第２の従来技術という）
第２の従来技術による画像表示の均一化効果については、既に実証されており、パルス幅変調駆動はＡＭＯＬＥＤの駆動法として有力な方法の一つではある。
しかしながら、前記第２の従来技術では、デジタル階調に対応した短い信号パルスを処理する必要があることから、駆動回路の動作周波数が高くなり、回路の消費電力が大きくなるという問題点があった。
また、通常は簡単な回路で済む垂直側走査回路が複雑になり回路面積が増大するという問題点があった。
【０００４】
本発明は、前記従来技術の問題点を解決するためになされたものであり、本発明の目的は、ＥＬ素子のような電流駆動型発光素子を有する表示装置において、従来よりも駆動回路の構成が簡単で、しかも、動画を表示した際に画質劣化を低減することが可能な駆動方法を提供することにある。
また、本発明の他の目的は、前記駆動方法を実施するために最適な表示装置を提供することにある。
本発明の前記並びにその他の目的と新規な特徴は、本明細書の記述及び添付図面によって明らかにする。
【０００５】
【課題を解決するための手段】
本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、下記の通りである。
即ち、本発明は、電流駆動型発光素子（例えば、有機エレクトロルミネッセンス素子）を有する画素を複数備える表示装置の駆動方法であって、１フレーム期間の初めの第１の期間に、全画素の前記電流駆動型発光素子の発光を停止させた状態で、前記各画素に映像信号電圧を書き込み、１フレーム期間の前記第１の期間に続く第２の期間に、前記各画素に書き込まれた映像信号電圧により決定される１回以上の発光期間内に、各画素内の前記電流駆動型発光素子を発光させる。
本発明によれば、１フレーム期間内に、電流駆動型発光素子の発光を停止する第１の期間を設けるようにしたので、動画を表示する場合に高画質の画像を表示させることが可能となる。
【０００６】
また、本発明は、電流駆動型発光素子と、スイッチングトランジスタと、前記スイッチングトランジスタに接続される保持容量素子とを有する画素を複数備える表示装置の駆動方法であって、１フレーム期間の初めの第１の期間に、前記全画素内の前記電流駆動型発光素子の発光を停止させた状態で、前記各画素の前記スイッチングトランジスタのゲート電極に走査駆動信号を印加して前記各画素の前記保持容量素子に映像信号電圧を書き込み、１フレーム期間の前記第１の期間に続く第２の期間に、前記各画素の前記スイッチングトランジスタのゲート電極に印加する走査駆動信号を停止するとともに、前記各画素の前記保持容量素子に書き込まれた映像信号電圧により決定される１回以上の発光期間内に、前記各画素の電流駆動型発光素子を発光させる。
本発明によれば、１フレーム期間内に、電流駆動型発光素子の発光を停止する第１の期間を設けるようにしたので、動画を表示する場合に高画質の画像を表示させることが可能となるばかりか、発光期間中、即ち、第２の期間中は前記スイッチングトランジスタのゲート電極に印加する走査駆動信号（例えば、走査クロック）を停止させるようにしたので、消費電力の増加を抑えることが可能となる。
【０００７】
また、本発明は、電流駆動型発光素子と、前記電流駆動型発光素子に駆動電流を供給する駆動トランジスタと、スイッチングトランジスタと、前記スイッチングトランジスタに接続される保持容量素子と、出力端子が前記駆動トランジスタのゲート電極に接続されるとともに、一方の入力端子に前記保持容量素子に保持される電圧が印加され、他方の入力端子に階調制御電圧が印加される比較器とを有する画素を複数備える表示装置であって、１フレーム期間の初めの第１の期間に、前記各画素の前記スイッチングトランジスタのゲート電極に走査駆動信号を印加して前記各画素の前記保持容量素子に映像信号電圧を書き込む第１の手段と、前記階調制御電圧として、前記第１の期間に、全画素内の前記駆動トランジスタをオフとする第１レベルの電圧を、また、１フレーム期間の前記第１の期間に続く第２の期間に、１回以上、前記第１レベルの電圧から、前記第１レベルの電圧とは異なる第２レベルの電圧まで変化する傾斜波形の電圧を供給する第２の手段とを備える。
本発明の一実施の形態では、前記第１の手段は、前記第２の期間に、前記各画素の前記スイッチングトランジスタのゲート電極に印加する走査駆動信号を停止する。
【０００８】
また、本発明は、電流駆動型発光素子と、出力端子に前記電流駆動型発光素子が接続されるインバータ回路と、スイッチングトランジスタと、前記スイッチングトランジスタと前記インバータ回路の入力端子との間に接続される保持容量素子とを有する画素を複数備える表示装置であって、１フレーム期間の初めの第１の期間に、前記各画素の前記インバータ回路の入力端子と出力端子とを短絡する第１の手段と、１フレーム期間の前記第１の期間に続く第２の期間に、前記各画素の前記スイッチングトランジスタのゲート電極に走査駆動信号を印加して前記各画素の保持容量素子に映像信号電圧を書き込む第２の手段と、１フレーム期間の前記第２の期間に続く第３の期間に、１回以上、前記各画素の前記保持容量素子の前記第１の端子に、第１レベルの電圧から、前記第１レベルの電圧とは異なる第２レベルの電圧まで変化する傾斜波形の階調制御電圧を印加する第３の手段とを備える。
【０００９】
本発明の一実施の形態では、前記第２の手段は、前記１フレーム期間の第１および第３の期間内に、前記各画素の前記スイッチングトランジスタのゲート電極に印加する走査駆動信号を停止する。
本発明の一実施の形態では、前記第３の手段は、前記各画素の前記保持容量素子の前記第１の端子に接続されるとともに、前記第３の期間にオンとなり前記階調制御電圧を前記保持容量素子の前記第１の端子に印加する第２のスイッチングトランジスタを有する。
本発明の一実施の形態では、前記複数の画素はマトリクス状に配置され、前記各画素列毎に設けられ、前記各画素の前記スイッチングトランジスタがオンのときに、前記各画素の前記保持容量素子に映像信号電圧を印加する複数の映像信号線と、前記各画素列毎に設けられ、前記階調制御電圧を印加する複数の階調信号線と、前記各画素列毎に設けられ、前記電流駆動型発光素子に駆動電流を供給する複数の電流供給線と、前記各画素行毎に設けられ、１ライン毎に前記各画素の前記スイッチングトランジスタのゲート電極に順次前記走査駆動信号を印加する複数の走査信号線とを備える。
【００１０】
【発明の実施の形態】
以下、図面を参照して本発明の実施の形態を詳細に説明する。
なお、実施の形態を説明するための全図において、同一機能を有するものは同一符号を付け、その繰り返しの説明は省略する。
［実施の形態１］
図１は、本発明の実施の形態１の表示装置の表示パネルの１画素の等価回路を示す回路図である。
本実施の形態において、各画素はマトリクス状に配置され、ｍ行ｎ列目の画素は、走査信号線（Ｇm，Ｇ(m+1)）と、映像信号線Ｄn（あるいは、階調信号線Ｋn）と、アノード電流供給線Ａnとで囲まれた領域で定義される。
各画素内部には、スイッチ用の薄膜トランジスタ（以下、スイッチＴＦＴという。）（Ｑｓ(m,n)）と、ＰＭＯＳトランジスタから成るＥＬ駆動ＴＦＴ（Ｑｄ(m,n)）と、保持容量素子Ｃｓｔ(m,n)と、比較器Ｃｏｐ(m,n)とが設けられる。
ＥＬ駆動ＴＦＴ（Ｑｄ(m,n)）のドレイン電極には、ＥＬ素子ＯＬＥＤ(m,n)のアノード電極が接続され、ゲート電極には、比較器Ｃｏｐ(m,n)の出力端子が接続される。ＥＬ素子ＯＬＥＤ(m,n)のカソード電極は接地電位（ＧＮＤ）に接続される。
比較器Ｃｏｐ(m,n)の一方の入力端子には、保持容量素子Ｃｓｔ(m,n)の一方の端子が接続され、他方の端子には、階調信号線Ｋnが接続される。
保持容量素子Ｃｓｔ(m,n)の一方の端子は、スイッチＴＦＴ（Ｑｓ(m,n)）を介して映像信号線Ｄnに接続され、また、保持容量素子Ｃｓｔ(m,n)の他方の端子は、接地電位（ＧＮＤ）に接続される。
【００１１】
比較のために、従来の表示装置の代表的な１画素の等価回路を図８に示す。この図８は、前述した特開２０００−１６３０１４号公報に記載されているものである。
この図８に示す等価回路は、比較器Ｃｏｐ(m,n)と階調信号線Ｋnとを備えず、かつ、保持容量素子Ｃｓｔ(m,n)の他方の端子が、アノード電流供給線（Ａn）に接続されている点で、図１に示す等価回路と相異する。
この図８に示す等価回路において、走査信号線Ｇが順次１ライン毎に走査され、スイッチＴＦＴ（Ｑｓ(m,n)）のゲート電極にＨｉｇｈレベル（以下、Ｈレベルという）の走査クロックが印加されると、スイッチＴＦＴ（Ｑｓ(m,n)）がオンとなり、これにより、スイッチＴＦＴ（Ｑｓ(m,n)）を介して、映像信号線Ｄnからアナログの映像信号電圧が保持容量素子Ｃｓｔ(m,n)に供給され、保持容量素子Ｃｓｔ(m,n)に保持される。
この保持容量素子Ｃｓｔ(m,n)に保持されたアナログの映像信号電圧は、ＥＬ駆動ＴＦＴ（Ｑｄ(m,n)）のゲート電極に供給され、これにより、ＥＬ駆動ＴＦＴ（Ｑｄ(m,n)）を流れる電流が制御され、即ち、アナログの映像信号電圧に対応する電流をＥＬ素子ＯＬＥＤ(m,n)に供給し、これにより、ＥＬ素子ＯＬＥＤ(m,n)が発光し、画像が表示される。
【００１２】
しかしながら、この図８に示す回路構成では、ＥＬ駆動ＴＦＴ（Ｑｄ(m,n)）を構成する半導体薄膜（多結晶シリコン膜）の結晶性の場所毎のバラツキにより、ＥＬ駆動ＴＦＴ（Ｑｄ(m,n)）のしきい電圧（Ｖｔｈ）や移動度（μ）が画素毎にバラツキが生じ、それにより、ＥＬ素子ＯＬＥＤ(m,n)の駆動電流値にバラツキが生じ、結果として、発光強度がバラツキ、表示上では微細なムラとなって見えるという問題点があった。
また、この図８に示す駆動方法は、１フレーム期間中、同一の画像を表示し続ける方法であり、画像が切り替わる毎に輝度が段階状に変化する。
このように常に画像を切れ目なしに表示する駆動方法では、前の画像から次の画像に切り替わると人間は２つの画像を重ねて認識し、結果的に画像の輪郭がぼやけてしまうという欠点があり、特に、動画を表示する場合に、表示画質を劣化させるという問題点があった。
【００１３】
以下、本実施の形態の駆動方法について説明する。
本実施の形態では、図２に示すように、１フレーム期間は、走査期間と発光期間とに分離される。
図２に示す走査期間は、全ての保持容量素子Ｃｓｔにアナログの映像信号電圧を書き込み期間であり、この期間内は、ＥＬ素子ＯＬＥＤの発光は停止される。
この走査期間内に、走査信号線Ｇが順次１ライン毎に走査され、１ライン毎に走査信号線Ｇに順次走査クロックが印加されると、全ての保持容量素子Ｃｓｔにアナログの映像信号電圧を書き込まれる。
例えば、図１において、スイッチＴＦＴ（Ｑｓ(m,n)）のゲート電極にＨレベルの走査クロックが印加されると、スイッチＴＦＴ（Ｑｓ(m,n)）がオンとなり、これにより、スイッチＴＦＴ（Ｑｓ(m,n)）を介して、映像信号線Ｄnからアナログの映像信号電圧が保持容量素子Ｃｓｔ(m,n)に供給され、保持容量素子Ｃｓｔ(m,n)に保持される。
また、本実施の形態では、階調信号線Ｋnには、図３に示すランプ波形の傾斜波電圧が印加される。
この図３に示す傾斜波電圧は、走査期間内は第１レベルの電圧（Ｖ１）であり、この第１レベルの電圧（Ｖ１）が比較器Ｃｏｐ(m,n)に入力されるため、比較器Ｃｏｐ(m,n)の出力はＨレベルを維持する。
そのため、全てのＥＬ駆動ＴＦＴ（Ｑｄ）がオフ状態を維持し、全てのＥＬ素子ＯＬＥＤの発光は停止される。即ち、走査期間内では、全てのＥＬ素子ＯＬＥＤは黒を表示する。
【００１４】
前述した走査期間に続く発光期間では、走査信号線Ｇに対する走査クロックの供給が停止される。
また、発光期間内に、階調信号線Ｋnに供給される傾斜波電圧が、図３に示すように、第１レベルの電圧（Ｖ１）から、第２レベルの電圧（Ｖ２）まで、ある傾斜をもって変化する。
そのため、保持容量素子Ｃｓｔに保持されている電圧値（図３では階調電圧と記す。）よりも、階調信号線Ｋnに供給される傾斜波電圧の電圧値が大きくなると、比較器ＣｏｐがＬｏｗレベル（以下、Ｌレベルという）となり、ＥＬ駆動ＴＦＴ（Ｑｄ）がオンとなり、ＥＬ素子ＯＬＥＤが発光する。
この場合に、各ＥＬ素子ＯＬＥＤを流れる電流（図３のＩｏｌｅｄ）は一定であり、各画素の発光輝度は、各画素のＥＬ素子ＯＬＥＤの発光時間に応じて変化する。即ち、図３に示すように、発光輝度が高い画素（明るい表示の画素）程、各画素のＥＬ素子ＯＬＥＤの発光時間が長くなる。
このように、本実施の形態では、ＥＬ駆動ＴＦＴ（Ｑｄ）を、完全にオフか、または完全にオン状態とする２値スイッチとして駆動させるので、ＥＬ駆動ＴＦＴ（Ｑｄ）を構成する半導体薄膜（多結晶シリコン膜）の結晶性の場所毎のバラツキにより、ＥＬ駆動ＴＦＴのしきい電圧（Ｖｔｈ）や移動度（μ）が画素毎にばらつくために生じる画像の不均一性を抑止することができる。
【００１５】
また、本実施の形態は、ＥＬ駆動ＴＦＴ（Ｑｄ）を、２値スイッチとして駆動し、画像の階調表示は発光の時間幅を変えるようにした点で、前述の第２の従来技術と類似している。
しかしながら、本実施の形態では、前述の第２の従来技術のように、デジタル階調に対応した短い信号パルスを処理する必要がないので、前述の第２の従来技術と比して、駆動回路の動作周波数を低くできるとともに、垂直側走査回路の構成を簡単できるので、回路面積を小さくすることができる。
さらに、本実施の形態では、発光期間中に、スイッチＴＦＴ（Ｑｓ）のゲート電極に印加する走査クロックを停止させるようにしたので、消費電力の増加を抑えることができる。
なお、本実施の形態では、図３に示すように、保持容量素子Ｃｓｔに保持されるアナログの映像信号は、発光輝度が高い程、第１レベルの電圧（Ｖ１）との間の電位差が小さく、発光輝度が低い程、第１レベルの電圧（Ｖ１）との間の電位差が大きくなる電圧である。
このように、本実施の形態では、１フレーム期間の走査期間内に、全てのＥＬ素子ＯＬＥＤの発光を停止するようにしたので、動画を表示する場合でも、表示画質の劣化を低減させることが可能となる。
【００１６】
図４は、本実施の形態の表示装置のマトリクス表示部と駆動回路を含めた表示部全体を示すブロック図である。
同図において、１０は表示パネル、２０は水平走査回路、３０は垂直走査回路である。
ここで、水平走査回路２０と、垂直走査回路３０とは、外部のタイミングコントローラからの制御信号（例えば、クロックパルス、スタートパルスなど）により制御され、また、水平走査回路２０は、映像信号線生成回路２１と、傾斜波電圧生成回路２２とで構成される。
図４において、垂直走査回路３０には、Ｍ本の走査信号線（Ｇ1〜ＧM）が接続され、垂直走査回路３０は、前述した走査期間内に、Ｍ個の走査信号線に順次Ｈレベルの走査クロックを出力する。なお、図４では、Ｇ1とＧMの２本の走査信号線のみを図示している。
映像信号線生成回路２１には、Ｎ本の映像信号線（Ｄ1〜ＤN）が接続され、映像信号線生成回路２１は、外部から入力される映像信号（Ｖｅｄｉｏ）に基づき、前述した走査期間内に、走査されるラインの画素に対応するアナログの映像信号電圧をＮ個の走査信号線に出力する。なお、図４では、Ｄ1とＤNの２本の映像信号線のみを図示している。
したがって、本実施の形態では、表示パネル１０は、Ｍ行Ｎ列の画素で構成されるが、図４では１個の画素のみを図示している。
また、傾斜波電圧生成回路２２には、Ｎ本の階調信号線（Ｋ1〜ＫN）が接続され、傾斜波電圧生成回路２２は、前述したランプ波形の傾斜波電圧を生成する。
なお、Ｎ本のアノード電流供給線（Ａ1〜ＡN）は、画素領域外で短絡（ショート）され、外部電源（ＶＤＤ）に接続される。
【００１７】
［実施の形態２］
前述の実施の形態の表示装置において、図３に示す明るい表示の場合のＥＬ素子ＯＬＥＤが発光する時点と、図３に示す暗い表示の場合のＥＬ素子ＯＬＥＤが発光する時点との間の時間差（Ｔａ）が大きくなると、動画を表示する場合に、動画ボケや擬似輪郭ノイズとなり、表示画像の画質の劣化が生じる恐れがある。
本実施の形態の表示装置は、前述した表示画像の画質の劣化を防止するものである。
図５は、本発明の実施の形態２の表示装置において、階調信号線Ｋに供給される傾斜波電圧の電圧波形を示す図である。
図３に示す傾斜波電圧は、第１レベルの電圧（Ｖ１）から、第２レベルの電圧（Ｖ２）まで一回のみ変化するものであるが、図５に示す傾斜波電圧は、第１レベルの電圧（Ｖ１）から、第２レベルの電圧（Ｖ２）まで複数回（図５では、６回）にわたって変化させるようにしたものである。
これにより、本実施の形態では、明るい表示の場合のＥＬ素子ＯＬＥＤが発光する時点と、暗い表示の場合のＥＬ素子ＯＬＥＤが発光する時点との間の時間差（Ｔｂ）を、図３のＴａよりも小さくできるので、動画を表示する場合に、動画ボケや擬似輪郭ノイズが生じるの防止することが可能となる。
なお、図５に示すランプ波形の傾斜波電圧は、図４に示す傾斜波電圧生成回路２２で生成される。
【００１８】
［実施の形態３］
図６は、本発明の実施の形態３の表示装置の表示パネルの１画素の等価回路を示す回路図である。
本実施の形態は、前述の各実施の形態における比較器Ｃｏｐに代えて、クランプドインバータ回路を使用する実施の形態である。
本実施の形態では、ＰＭＯＳトランジスタ（ＰＭ(m,n)）とＮＭＯＳトランジスタ（ＮＭ(m,n)）とから成るインバータ回路の出力端子に、ＥＬ素子ＯＬＥＤ(m,n)のアノード電極が接続され、ＥＬ素子ＯＬＥＤ(m,n)は、ＰＭＯＳトランジスタ（ＰＭ(m,n)）から駆動電流が供給される。
インバータ回路の入力端子と出力端子との間には、スイッチ用の薄膜トランジスタ（以下、第３のスイッチＴＦＴという。）（Ｑｓ3(m,n)）が接続され、インバータ回路の入力端子には、保持容量素子Ｃｓｔ(m,n)の一方の端子が接続される。
また、保持容量素子Ｃｓｔ(m,n)の他方の端子には、スイッチＴＦＴ（Ｑｓ(m,n)）を介して映像信号線Ｄnと、スイッチ用の薄膜トランジスタ（以下、第２のスイッチＴＦＴという。）（Ｑｓ2(m,n)）を介して階調信号線Ｋnが接続される。
【００１９】
図７は、図６に示す各スイッチＴＦＴのゲート電極、映像信号線Ｄn、および階調信号線Ｋnに印加される電圧波形を示す図である。
図７において、Ｖｒｅは、第３のスイッチＴＦＴ（Ｑｓ3(m,n)）のゲート電極に印加される電圧、Ｖｇ１は、スイッチＴＦＴ（Ｑｓ(m,n)）のゲート電極に印加される走査クロック、Ｖｓｉｇは、映像信号線Ｄnに供給されるアナログの映像信号、Ｖｇ２は、第２のスイッチＴＦＴ（Ｑｓ2(m,n)）のゲート電極に印加される電圧、Ｖｇｒａｙは、階調信号線Ｋnに印加されるランプ波形の傾斜波電圧、Ｉｏｌｅｄは、ＥＬ素子ＯＬＥＤ(m,n)を流れる駆動電流である。
以下、図７を用いて、本実施の形態の駆動方法について説明する。
本実施の形態においても、１フレームは、走査期間と発光期間とに分けられる。
本実施の形態において、Ｖｒｅの電圧は、走査期間の第１の期間にＨレベルとなるので、全ての画素内の第３のスイッチＴＦＴ（Ｑｓ3(m,n)）がオンなり、インバータ回路の入力端子と出力端子とが短絡される。
これにより、インバータ回路の入力端子ノードは、ＰＭＯＳトランジスタ（ＰＭ(m,n)）を流れる電流と、ＮＭＯＳトランジスタ（ＮＭ(m,n)）を流れる電流とが一致する電圧（Ｖcn）に設定される。
この場合に、ＰＭＯＳトランジスタ（ＰＭ(m,n)）、および、ＮＭＯＳトランジスタ（ＮＭ(m,n)）を構成する半導体薄膜（多結晶シリコン膜）の結晶性の場所毎のバラツキにより、ＰＭＯＳトランジスタ（ＰＭ(m,n)）、および、ＮＭＯＳトランジスタ（ＮＭ(m,n)）のしきい電圧（Ｖｔｈ）や移動度（μ）が画素毎にばらついても、前記電圧（Ｖcn）は、前述したバラツキに応じた電圧値となる。
【００２０】
次に、走査期間内の、第１の期間に続く第２の期間に、走査信号線Ｇが順次１ライン毎に走査され、即ち、１ライン毎に走査信号線Ｇに、順次走査クロックが印加され、全ての保持容量素子Ｃｓｔにアナログの映像信号電圧を書き込まれる。
例えば、スイッチＴＦＴ（Ｑｓ(m,n)）のゲート電極に印加される走査クロックがＨレベルとなると、スイッチＴＦＴ（Ｑｓ(m,n)）がオンとなり、スイッチＴＦＴ（Ｑｓ(m,n)）を介して、映像信号線Ｄnからアナログの映像信号電圧が保持容量素子Ｃｓｔ(m,n)に保持される。
この場合に、インバータ回路のＰＭＯＳトランジスタ（ＰＭ(m,n)）はオフであるので、全てのＥＬ素子ＯＬＥＤの発光は停止される。
次に、発光期間になると、Ｖｇ２の電圧がＨレベルとなるので、スイッチＴＦＴ（Ｑｓ2(m,n)）がオンとなり、各保持容量素子Ｃｓｔには、階調信号線Ｋからランプ波形の傾斜波電圧が印加される。
この図７に示す傾斜波電圧は、第１レベルの電圧（Ｖ１）から、第２レベルの電圧（Ｖ２）まで、ある傾斜もって変化する電圧である。
【００２１】
これにより、インバータ回路の入力端子ノードは、（Ｖcn−（Ｖｓｉｇ−Ｖ１））の電圧となり、インバータ回路のＰＭＯＳトランジスタ（ＰＭ(m,n)）がオンとなり、ＥＬ素子ＯＬＥＤが発光する。
図７に示す傾斜波電圧が、第１レベルの電圧（Ｖ１）から上昇し、保持容量素子Ｃｓｔ(m,n)に保持されている電圧（図７では、階調電圧と記す）になると、インバータ回路のＰＭＯＳトランジスタ（ＰＭ(m,n)）がオフとなり、ＥＬ素子ＯＬＥＤが発光を停止する。
この場合に、各ＥＬ素子ＯＬＥＤを流れる電流（図７のＩｏｌｅｄ）は一定であり、各画素の発光輝度は、各画素のＥＬ素子ＯＬＥＤの発光時間に応じて変化する。即ち、発光輝度が高い画素程、各画素のＥＬ素子ＯＬＥＤの発光時間が長くなる。
さらに、本実施の形態では、前記電圧（Ｖcn）は、インバータ回路のＰＭＯＳトランジスタ（ＰＭ(m,n)）、および、ＮＭＯＳトランジスタ（ＮＭ(m,n)）のしきい電圧（Ｖｔｈ）や移動度（μ）が画素毎にばらついても、前記電圧（Ｖcn）は、前述したバラツキに応じた電圧値となるので、本実施の形態では、インバータ回路を構成する薄膜トランジスタの特性のバラツキに起因する、複数の画素間での表示バラツキを低減し、ムラのない均一な表示を得ることが可能となる。
【００２２】
なお、本実施の形態では、図７に示すように、保持容量素子Ｃｓｔに保持されるアナログの映像信号は、発光輝度が高い程、第１レベルの電圧（Ｖ１）との間の電位差が大きく、発光輝度が低い程、第１レベルの電圧（Ｖ１）との間の電位差が小さくなる電圧である。
このように、本実施の形態でも、１フレーム期間の走査期間内に、全てのＥＬ素子ＯＬＥＤの発光を停止するようにしたので、動画を表示する場合でも、表示画質の劣化を低減させることが可能となる。
なお、本実施の形態において、表示装置のマトリクス表示部と駆動回路を含めた表示部全体の構成は、図４と同じであり、前述したランプ波形の傾斜波電圧は、傾斜波電圧生成回路２２で生成される。
また、本実施の形態においても、前述の実施の形態２のように、傾斜波電圧を、第１レベルの電圧（Ｖ１）から、第２レベルの電圧（Ｖ２）まで複数回にわたって変化させるようにしてもよい。
以上、本発明者によってなされた発明を、前記実施の形態に基づき具体的に説明したが、本発明は、前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲において種々変更可能であることは勿論である。
【００２３】
【発明の効果】
本願において開示される発明のうち代表的なものによって得られる効果を簡単に説明すれば、下記の通りである。
（１）本発明の表示装置によれば、１フレーム期間を、走査期間と発光期間とに分離し、走査期間内に、電流駆動型発光素子の発光を停止するようにしたので、動画を表示する場合に高画質の画像を表示させることが可能となる。
（２）本発明の表示装置によれば、１フレーム期間を、走査期間と発光期間とに分離し、発光期間中に、スイッチング薄膜トランジスタのゲート電極に印加する走査駆動信号（例えば、走査クロック）を停止させるようにしたので、消費電力の増加を抑えることが可能となる。
【図面の簡単な説明】
【図１】本発明の実施の形態１の表示装置の表示パネルの１画素の等価回路を示す回路図である。
【図２】本発明の実施の形態１の表示装置の駆動方法を説明するための図である。
【図３】本発明の実施の形態１の表示装置において、階調信号線に供給される傾斜波電圧の電圧波形を示す図である。
【図４】本発明の実施の形態１の表示装置のマトリクス表示部と駆動回路を含めた表示部全体を示すブロック図である。
【図５】本発明の実施の形態２の表示装置において、階調信号線に供給される傾斜波電圧の電圧波形を示す図である。
【図６】本発明の実施の形態３の表示装置の表示パネルの１画素の等価回路を示す回路図である。
【図７】図６に示す各スイッチＴＦＴのゲート電極、映像信号線Ｄn、階調信号線Ｋnに印加される電圧波形を示す図である。
【図８】従来の表示装置の表示パネルの１画素の等価回路を示す回路図である。
【符号の説明】
１０…表示パネル、２０…水平走査回路、２１…映像信号線生成回路、２２…傾斜波電圧生成回路、３０…垂直走査回路、Ａ…アノード電流供給線、Ｄ…映像信号線、Ｇ…走査信号線、Ｋ…階調信号線、Ｑｓ，Ｑｓ1、Ｑｓ2…スイッチ用薄膜トランジスタ、Ｑｄ…駆動用薄膜トランジスタ、Ｃｓｔ…保持容量素子、ＯＬＥＤ…有機エレクトロルミネッセンス素子、Ｃｏｐ…比較器、ＰＭ…ＰＭＯＳトランジスタ、ＮＭ…ＮＭＯＳトランジスタ。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a display device and a driving method thereof, and more particularly to a driving method of an active matrix organic electroluminescence display.
[0002]
[Prior art]
An active matrix driving organic electroluminescence display (hereinafter referred to as AMOLED) is expected as a flat panel display of the next generation of a conventional liquid crystal display.
Conventionally, as an AMOLED drive circuit, for example, a drive circuit for supplying a current to an organic electroluminescence element (hereinafter simply referred to as an EL element) as disclosed in Japanese Patent Application Laid-Open No. 2000-163014. A thin film transistor (hereinafter referred to as EL driving TFT), a holding capacitor connected to the gate electrode of the EL driving TFT and holding a video signal voltage, and a thin film transistor for switching (hereinafter referred to as a switch) for supplying the video signal voltage to the holding capacitor A circuit having a two-transistor structure composed of TFT) is known as the most basic pixel circuit. (Hereinafter referred to as the first prior art)
[0003]
[Problems to be solved by the invention]
A major problem with the basic pixel circuit having the two-transistor configuration, which is the first prior art, is due to variations in crystallinity of the semiconductor thin film (usually a polycrystalline silicon film) constituting the EL driving TFT. There is image non-uniformity that occurs because the threshold voltage (Vth) and mobility (μ) of the EL drive TFT vary from pixel to pixel.
Variations in threshold voltage and mobility directly result in variations in the drive current value of the EL element, resulting in variations in light emission intensity and fine irregularities on the display. This display unevenness is particularly problematic during halftone display with a small drive current value.
In order to suppress such display non-uniformity due to variations in the characteristics of the EL drive TFT, for example, Japanese Patent Application Laid-Open No. 2000-330527 discloses that the EL drive TFT is completely turned off or completely turned on. A driving method based on so-called pulse width modulation is disclosed in which it is driven as a value switch and gradation display of an image is displayed by changing the time width of light emission. (Hereinafter referred to as second prior art)
The effect of uniformizing image display according to the second prior art has already been demonstrated, and pulse width modulation driving is one of the effective methods for driving AMOLED.
However, in the second prior art, since it is necessary to process a short signal pulse corresponding to the digital gradation, there is a problem that the operating frequency of the drive circuit becomes high and the power consumption of the circuit increases. .
In addition, there is a problem that the vertical scanning circuit that usually requires a simple circuit becomes complicated and the circuit area increases.
[0004]
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a drive circuit configuration more than that of a conventional display device having a current-driven light emitting element such as an EL element. It is an object of the present invention to provide a driving method that is simple and that can reduce image quality degradation when a moving image is displayed.
Another object of the present invention is to provide an optimal display device for carrying out the driving method.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
[0005]
[Means for Solving the Problems]
Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
That is, the present invention is a method for driving a display device including a plurality of pixels each having a current-driven light-emitting element (for example, an organic electroluminescence element), and in the first period of one frame period, A video signal voltage is written to each pixel while light emission of the current-driven light emitting element is stopped, and a video signal written to each pixel in a second period following the first period of one frame period. The current-driven light emitting element in each pixel is caused to emit light within one or more light emission periods determined by the voltage.
According to the present invention, since the first period for stopping the light emission of the current driven light emitting element is provided within one frame period, it is possible to display a high quality image when displaying a moving image. Become.
[0006]
The present invention also provides a method for driving a display device including a plurality of pixels each having a current-driven light-emitting element, a switching transistor, and a storage capacitor connected to the switching transistor. In a period of 1, in a state where light emission of the current driven light emitting elements in all the pixels is stopped, a scanning drive signal is applied to the gate electrode of the switching transistor of each pixel, and the storage capacitor of each pixel A video signal voltage is written to the element, and in a second period following the first period of one frame period, the scanning drive signal applied to the gate electrode of the switching transistor of each pixel is stopped, and The current-driven light-emitting element of each pixel is within one or more light-emission periods determined by the video signal voltage written to the storage capacitor element. To emit light.
According to the present invention, since the first period for stopping the light emission of the current driven light emitting element is provided within one frame period, it is possible to display a high quality image when displaying a moving image. In addition, since the scanning drive signal (for example, scanning clock) applied to the gate electrode of the switching transistor is stopped during the light emission period, that is, during the second period, an increase in power consumption can be suppressed. It becomes possible.
[0007]
The present invention also provides a current-driven light-emitting element, a drive transistor that supplies a drive current to the current-driven light-emitting element, a switching transistor, a storage capacitor connected to the switching transistor, and an output terminal that drives the drive A plurality of pixels having a comparator connected to a gate electrode of the transistor, to which a voltage held in the holding capacitor element is applied to one input terminal and a gradation control voltage is applied to the other input terminal; In the display device, in a first period of one frame period, a scanning drive signal is applied to the gate electrode of the switching transistor of each pixel and a video signal voltage is written to the storage capacitor element of each pixel. The first means and the first control for turning off the driving transistors in all pixels as the gradation control voltage in the first period. And a second level voltage different from the first level voltage from the first level voltage at least once in a second period following the first period of one frame period. And a second means for supplying a voltage having a ramp waveform changing up to.
In one embodiment of the present invention, the first means stops the scanning drive signal applied to the gate electrode of the switching transistor of each pixel during the second period.
[0008]
The present invention also includes a current driven light emitting element, an inverter circuit having the output terminal connected to the current driven light emitting element, a switching transistor, and the switching transistor connected between the switching transistor and the input terminal of the inverter circuit. A display device comprising a plurality of pixels each having a storage capacitor element, wherein a first means for short-circuiting an input terminal and an output terminal of the inverter circuit of each pixel in a first period of one frame period In a second period following the first period of one frame period, a scanning drive signal is applied to the gate electrode of the switching transistor of each pixel, and a video signal voltage is written to the storage capacitor element of each pixel. The second means and the first terminal of the storage capacitor of each pixel at least once in the third period following the second period of one frame period From the first level voltage, and a third means for applying a gray scale control voltage ramp waveform that varies from a different second level voltage from said first level voltage.
[0009]
In one embodiment of the present invention, the second means stops the scanning drive signal applied to the gate electrode of the switching transistor of each pixel within the first and third periods of the one frame period. .
In an embodiment of the present invention, the third means is connected to the first terminal of the storage capacitor element of each pixel and is turned on in the third period to set the gradation control voltage. A second switching transistor applied to the first terminal of the storage capacitor;
In one embodiment of the present invention, the plurality of pixels are arranged in a matrix, provided for each pixel column, and when the switching transistor of each pixel is on, the storage capacitor element of each pixel A plurality of video signal lines for applying a video signal voltage to each pixel column, a plurality of gradation signal lines for applying the gradation control voltage, and a pixel signal line provided for each pixel column; A plurality of current supply lines for supplying a drive current to the drive type light emitting element and a plurality of current supply lines which are provided for each pixel row and sequentially apply the scanning drive signal to the gate electrode of the switching transistor of each pixel for each line. Scanning signal lines.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.
[Embodiment 1]
FIG. 1 is a circuit diagram showing an equivalent circuit of one pixel of the display panel of the display device according to Embodiment 1 of the present invention.
In this embodiment, the pixels are arranged in a matrix, and the pixels in the m-th row and the n-th column are the scanning signal line (Gm, G (m + 1)) and the video signal line Dn (or the gradation signal line). Kn) and the region surrounded by the anode current supply line An.
Within each pixel, a switching thin film transistor (hereinafter referred to as a switch TFT) (Qs (m, n)), an EL drive TFT (Qd (m, n)) composed of a PMOS transistor, and a storage capacitor element Cst ( m, n) and a comparator Cop (m, n) are provided.
The anode electrode of the EL element OLED (m, n) is connected to the drain electrode of the EL drive TFT (Qd (m, n)), and the output terminal of the comparator Cop (m, n) is connected to the gate electrode. Is done. The cathode electrode of the EL element OLED (m, n) is connected to the ground potential (GND).
One input terminal of the comparator Cop (m, n) is connected to one terminal of the storage capacitor element Cst (m, n), and the other terminal is connected to the gradation signal line Kn.
One terminal of the storage capacitor element Cst (m, n) is connected to the video signal line Dn via the switch TFT (Qs (m, n)), and the other terminal of the storage capacitor element Cst (m, n). The terminal is connected to the ground potential (GND).
[0011]
For comparison, FIG. 8 shows a typical equivalent circuit of one pixel of a conventional display device. FIG. 8 is described in Japanese Patent Laid-Open No. 2000-163014 described above.
The equivalent circuit shown in FIG. 8 does not include the comparator Cop (m, n) and the gradation signal line Kn, and the other terminal of the storage capacitor element Cst (m, n) is connected to the anode current supply line ( 1), and is different from the equivalent circuit shown in FIG.
In the equivalent circuit shown in FIG. 8, the scanning signal line G is sequentially scanned line by line, and a high level (hereinafter referred to as H level) scanning clock is applied to the gate electrode of the switch TFT (Qs (m, n)). Then, the switch TFT (Qs (m, n)) is turned on, whereby an analog video signal voltage is supplied from the video signal line Dn via the switch TFT (Qs (m, n)) to the holding capacitor element Cst. is supplied to (m, n) and held in the holding capacitor element Cst (m, n).
The analog video signal voltage held in the holding capacitor element Cst (m, n) is supplied to the gate electrode of the EL driving TFT (Qd (m, n)), thereby the EL driving TFT (Qd (m, n)). n)) is controlled, that is, a current corresponding to an analog video signal voltage is supplied to the EL element OLED (m, n), whereby the EL element OLED (m, n) emits light and the image Is displayed.
[0012]
However, in the circuit configuration shown in FIG. 8, the EL driving TFT (Qd (m, n) is affected by the variation in crystallinity of the semiconductor thin film (polycrystalline silicon film) constituting the EL driving TFT (Qd (m, n)). , n)) has a variation in threshold voltage (Vth) and mobility (μ) from pixel to pixel, thereby causing variations in the drive current value of the EL element OLED (m, n), resulting in emission intensity. However, there is a problem that the image appears to be fine and uneven on the display.
Further, the driving method shown in FIG. 8 is a method in which the same image is continuously displayed during one frame period, and the luminance changes stepwise every time the image is switched.
In such a driving method that always displays an image without a break, there is a disadvantage that when the previous image is switched to the next image, a human recognizes the two images in a superimposed manner, resulting in blurring of the image outline. In particular, there is a problem that the display image quality is deteriorated when a moving image is displayed.
[0013]
Hereinafter, the driving method of the present embodiment will be described.
In the present embodiment, as shown in FIG. 2, one frame period is divided into a scanning period and a light emission period.
The scanning period shown in FIG. 2 is a period during which an analog video signal voltage is written to all the storage capacitor elements Cst. During this period, light emission of the EL element OLED is stopped.
During this scanning period, the scanning signal line G is sequentially scanned line by line, and when a scanning clock is sequentially applied to the scanning signal line G for each line, an analog video signal voltage is applied to all the storage capacitor elements Cst. Written.
For example, in FIG. 1, when an H level scanning clock is applied to the gate electrode of the switch TFT (Qs (m, n)), the switch TFT (Qs (m, n)) is turned on. An analog video signal voltage is supplied from the video signal line Dn to the storage capacitor element Cst (m, n) via (Qs (m, n)) and is stored in the storage capacitor element Cst (m, n).
In the present embodiment, the ramp voltage having the ramp waveform shown in FIG. 3 is applied to the gradation signal line Kn.
The ramp voltage shown in FIG. 3 is the first level voltage (V1) during the scanning period, and this first level voltage (V1) is input to the comparator Cop (m, n). The output of the device Cop (m, n) is maintained at the H level.
Therefore, all the EL drive TFTs (Qd) are maintained in the off state, and the light emission of all the EL elements OLED is stopped. That is, all the EL elements OLED display black during the scanning period.
[0014]
In the light emission period following the above-described scanning period, the supply of the scanning clock to the scanning signal line G is stopped.
Further, as shown in FIG. 3, the ramp voltage supplied to the gradation signal line Kn within the light emission period has a certain slope from the first level voltage (V1) to the second level voltage (V2). Change with.
Therefore, when the voltage value of the ramp voltage supplied to the gradation signal line Kn becomes larger than the voltage value (denoted as gradation voltage in FIG. 3) held in the storage capacitor element Cst, the comparator Cop It becomes Low level (hereinafter referred to as L level), the EL drive TFT (Qd) is turned on, and the EL element OLED emits light.
In this case, the current flowing through each EL element OLED (Ioled in FIG. 3) is constant, and the light emission luminance of each pixel changes according to the light emission time of the EL element OLED of each pixel. That is, as shown in FIG. 3, the light emission time of the EL element OLED of each pixel becomes longer as the light emission luminance is higher (bright display pixel).
As described above, in the present embodiment, the EL driving TFT (Qd) is driven as a binary switch that is either completely off or completely turned on, so that the semiconductor thin film (EL) that constitutes the EL driving TFT (Qd) ( Due to the variation in the crystallinity of the polycrystalline silicon film), it is possible to suppress image non-uniformity caused by variations in threshold voltage (Vth) and mobility (μ) of the EL drive TFT from pixel to pixel. .
[0015]
In the present embodiment, the EL driving TFT (Qd) is driven as a binary switch, and the gradation display of the image is similar to the second prior art in that the light emission time width is changed. is doing.
However, in the present embodiment, unlike the second prior art described above, it is not necessary to process a short signal pulse corresponding to the digital gradation, so that the drive circuit is compared with the second prior art described above. Since the configuration of the vertical scanning circuit can be simplified, the circuit area can be reduced.
Furthermore, in this embodiment, since the scanning clock applied to the gate electrode of the switch TFT (Qs) is stopped during the light emission period, an increase in power consumption can be suppressed.
In the present embodiment, as shown in FIG. 3, the potential difference between the analog video signal held in the holding capacitor element Cst and the first level voltage (V1) is smaller as the emission luminance is higher. The lower the emission luminance, the larger the potential difference from the first level voltage (V1).
As described above, in this embodiment, since the light emission of all the EL elements OLED is stopped within the scanning period of one frame period, it is possible to reduce deterioration in display image quality even when a moving image is displayed. It becomes possible.
[0016]
FIG. 4 is a block diagram showing the entire display unit including the matrix display unit and the drive circuit of the display device of this embodiment.
In the figure, 10 is a display panel, 20 is a horizontal scanning circuit, and 30 is a vertical scanning circuit.
Here, the horizontal scanning circuit 20 and the vertical scanning circuit 30 are controlled by a control signal (for example, a clock pulse, a start pulse, etc.) from an external timing controller, and the horizontal scanning circuit 20 generates a video signal line. The circuit 21 and the ramp voltage generator 22 are configured.
In FIG. 4, M scanning signal lines (G1 to GM) are connected to the vertical scanning circuit 30, and the vertical scanning circuit 30 sequentially applies the H level to the M scanning signal lines within the above-described scanning period. Output scan clock. In FIG. 4, only two scanning signal lines G1 and GM are shown.
N video signal lines (D1 to DN) are connected to the video signal line generation circuit 21, and the video signal line generation circuit 21 is based on the video signal (Vedio) input from the outside within the above-described scanning period. In addition, analog video signal voltages corresponding to the pixels of the scanned line are output to the N scanning signal lines. In FIG. 4, only two video signal lines D1 and DN are shown.
Accordingly, in the present embodiment, the display panel 10 is configured by pixels of M rows and N columns, but FIG. 4 illustrates only one pixel.
In addition, N gradation signal lines (K1 to KN) are connected to the ramp wave voltage generation circuit 22, and the ramp wave voltage generation circuit 22 generates the ramp wave voltage having the ramp waveform described above.
Note that the N anode current supply lines (A1 to AN) are short-circuited (short-circuited) outside the pixel region and connected to an external power supply (VDD).
[0017]
[Embodiment 2]
In the display device of the above-described embodiment, the time difference between the time when the EL element OLED in the case of bright display shown in FIG. 3 emits light and the time when the EL element OLED in the case of dark display shown in FIG. When Ta) is increased, moving images are displayed as moving image blur or pseudo contour noise, which may cause deterioration in the image quality of the display image.
The display device according to the present embodiment prevents the deterioration of the image quality of the display image described above.
FIG. 5 is a diagram showing a voltage waveform of the ramp voltage supplied to the gradation signal line K in the display device according to the second embodiment of the present invention.
The ramp voltage shown in FIG. 3 changes only once from the first level voltage (V1) to the second level voltage (V2), but the ramp voltage shown in FIG. The voltage (V1) is changed over a plurality of times (6 times in FIG. 5) from the second level voltage (V2).
Thereby, in this embodiment, the time difference (Tb) between the time when the EL element OLED emits light in the case of bright display and the time when the EL element OLED emits light in the case of dark display is represented by Ta in FIG. Therefore, when moving images are displayed, it is possible to prevent the occurrence of moving image blur and pseudo contour noise.
5 is generated by the ramp voltage generation circuit 22 shown in FIG.
[0018]
[Embodiment 3]
FIG. 6 is a circuit diagram showing an equivalent circuit of one pixel of the display panel of the display device according to Embodiment 3 of the present invention.
In this embodiment, a clamped inverter circuit is used instead of the comparator Cop in each of the above-described embodiments.
In this embodiment, the anode electrode of the EL element OLED (m, n) is connected to the output terminal of the inverter circuit composed of the PMOS transistor (PM (m, n)) and the NMOS transistor (NM (m, n)). The EL element OLED (m, n) is supplied with a drive current from the PMOS transistor (PM (m, n)).
A thin film transistor for switching (hereinafter referred to as a third switch TFT) (Qs3 (m, n)) is connected between the input terminal and the output terminal of the inverter circuit, and is held at the input terminal of the inverter circuit. One terminal of the capacitive element Cst (m, n) is connected.
The other terminal of the storage capacitor element Cst (m, n) is connected to the video signal line Dn via the switch TFT (Qs (m, n)) and a switching thin film transistor (hereinafter referred to as a second switch TFT). .) The gradation signal line Kn is connected via (Qs2 (m, n)).
[0019]
FIG. 7 is a diagram showing voltage waveforms applied to the gate electrode, the video signal line Dn, and the gradation signal line Kn of each switch TFT shown in FIG.
In FIG. 7, Vre is a voltage applied to the gate electrode of the third switch TFT (Qs3 (m, n)), and Vg1 is a scan applied to the gate electrode of the switch TFT (Qs (m, n)). Clock, Vsig is an analog video signal supplied to the video signal line Dn, Vg2 is a voltage applied to the gate electrode of the second switch TFT (Qs2 (m, n)), and Vgray is a gradation signal line The ramp waveform voltage Ioled applied to Kn is a drive current flowing through the EL element OLED (m, n).
Hereinafter, the driving method of the present embodiment will be described with reference to FIG.
Also in this embodiment, one frame is divided into a scanning period and a light emission period.
In this embodiment, since the voltage of Vre becomes H level in the first period of the scanning period, the third switch TFT (Qs3 (m, n)) in all the pixels is turned on, and the inverter circuit The input terminal and output terminal are short-circuited.
As a result, the input terminal node of the inverter circuit is set to a voltage (Vcn) at which the current flowing through the PMOS transistor (PM (m, n)) matches the current flowing through the NMOS transistor (NM (m, n)). The
In this case, the PMOS transistor (PM (m, n)) and the semiconductor transistor (polycrystalline silicon film) constituting the NMOS transistor (NM (m, n)) vary depending on the crystallinity of each location. (PM (m, n)) and the threshold voltage (Vth) and mobility (μ) of the NMOS transistor (NM (m, n)) vary from pixel to pixel, the voltage (Vcn) is The voltage value corresponds to the variation.
[0020]
Next, in the second period following the first period in the scanning period, the scanning signal lines G are sequentially scanned line by line, that is, a scanning clock is sequentially applied to the scanning signal lines G for each line. Then, an analog video signal voltage is written to all the storage capacitor elements Cst.
For example, when the scanning clock applied to the gate electrode of the switch TFT (Qs (m, n)) becomes H level, the switch TFT (Qs (m, n)) is turned on and the switch TFT (Qs (m, n)) ), The analog video signal voltage is held in the holding capacitor element Cst (m, n) from the video signal line Dn.
In this case, since the PMOS transistor (PM (m, n)) of the inverter circuit is off, the light emission of all the EL elements OLED is stopped.
Next, in the light emission period, since the voltage of Vg2 becomes H level, the switch TFT (Qs2 (m, n)) is turned on, and each storage capacitor element Cst has a ramp waveform slope from the gradation signal line K. A wave voltage is applied.
The ramp voltage shown in FIG. 7 is a voltage that changes with a certain slope from the first level voltage (V1) to the second level voltage (V2).
[0021]
Thereby, the input terminal node of the inverter circuit becomes a voltage of (Vcn− (Vsig−V1)), the PMOS transistor (PM (m, n)) of the inverter circuit is turned on, and the EL element OLED emits light.
When the ramp voltage shown in FIG. 7 rises from the first level voltage (V1) and becomes a voltage held in the holding capacitor element Cst (m, n) (denoted as a gradation voltage in FIG. 7), The PMOS transistor (PM (m, n)) of the inverter circuit is turned off, and the EL element OLED stops emitting light.
In this case, the current flowing through each EL element OLED (Ioled in FIG. 7) is constant, and the light emission luminance of each pixel changes according to the light emission time of the EL element OLED of each pixel. That is, the higher the emission luminance, the longer the emission time of the EL element OLED of each pixel.
Furthermore, in the present embodiment, the voltage (Vcn) is the threshold voltage (Vth) or movement of the PMOS transistor (PM (m, n)) and NMOS transistor (NM (m, n)) of the inverter circuit. Even if the degree (μ) varies from pixel to pixel, the voltage (Vcn) has a voltage value corresponding to the above-described variation. In this embodiment, the voltage (Vcn) is caused by variation in characteristics of the thin film transistors constituting the inverter circuit. Thus, display variations among a plurality of pixels can be reduced, and uniform display without unevenness can be obtained.
[0022]
In the present embodiment, as shown in FIG. 7, the potential difference between the analog video signal held in the holding capacitor element Cst and the first level voltage (V1) increases as the emission luminance increases. The lower the emission luminance, the smaller the potential difference from the first level voltage (V1).
As described above, also in this embodiment, since the light emission of all the EL elements OLED is stopped within the scanning period of one frame period, it is possible to reduce deterioration in display image quality even when displaying a moving image. It becomes possible.
In the present embodiment, the configuration of the entire display unit including the matrix display unit and the drive circuit of the display device is the same as that in FIG. 4, and the ramp wave voltage of the ramp waveform described above is the ramp wave voltage generation circuit 22. Is generated.
Also in the present embodiment, the ramp voltage is changed from the first level voltage (V1) to the second level voltage (V2) a plurality of times as in the second embodiment. May be.
Although the invention made by the present inventor has been specifically described based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention. Of course.
[0023]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
(1) According to the display device of the present invention, one frame period is divided into a scanning period and a light emitting period, and the light emission of the current driven light emitting element is stopped within the scanning period. In this case, it is possible to display a high-quality image.
(2) According to the display device of the present invention, one frame period is divided into a scanning period and a light emitting period, and a scanning drive signal (for example, a scanning clock) applied to the gate electrode of the switching thin film transistor during the light emitting period. Since the operation is stopped, an increase in power consumption can be suppressed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing an equivalent circuit of one pixel of a display panel of a display device according to a first embodiment of the present invention.
FIG. 2 is a diagram for explaining a driving method of the display device according to the first embodiment of the present invention;
FIG. 3 is a diagram showing a voltage waveform of a ramp voltage supplied to a gradation signal line in the display device according to the first embodiment of the present invention.
4 is a block diagram showing an entire display unit including a matrix display unit and a drive circuit of the display device according to the first embodiment of the present invention. FIG.
FIG. 5 is a diagram showing a voltage waveform of a ramp voltage supplied to a gradation signal line in the display device according to the second embodiment of the present invention.
6 is a circuit diagram showing an equivalent circuit of one pixel of a display panel of a display device according to a third embodiment of the present invention. FIG.
7 is a diagram showing voltage waveforms applied to the gate electrode, video signal line Dn, and gradation signal line Kn of each switch TFT shown in FIG. 6;
FIG. 8 is a circuit diagram showing an equivalent circuit of one pixel of a display panel of a conventional display device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Display panel, 20 ... Horizontal scanning circuit, 21 ... Video signal line generation circuit, 22 ... Ramp wave voltage generation circuit, 30 ... Vertical scanning circuit, A ... Anode current supply line, D ... Video signal line, G ... Scan signal Line, K ... gradation signal line, Qs, Qs1, Qs2 ... thin film transistor for switching, Qd ... thin film transistor for driving, Cst ... holding capacitor element, OLED ... organic electroluminescence element, Cop ... comparator, PM ... PMOS transistor, NM ... NMOS transistor.

Claims (5)

比較器と電流駆動型発光素子とを有する画素を複数備える表示装置の駆動方法であって、
１フレーム期間中に第１の期間と、前記第１の期間よりも後の期間である第２の期間を有し、
前記第１の期間に、全画素内の前記電流駆動型発光素子の発光を停止させた状態で、前記各画素の比較器の一方の入力端子に接続された第１配線に対して映像信号電圧を書き込み、
前記第２の期間に、前記各画素の比較器の他方の入力端子に接続された第２配線に対して、第１レベルから第２レベルまで複数回にわたって変化する電圧を書き込み、前記各画素に書き込まれた映像信号電圧と該電圧とにより決定される期間、前記各画素の前記電流駆動型発光素子を発光させることを特徴とする表示装置の駆動方法。Pixels with a comparator and a current driven luminescent element A method of driving a plurality equipped display device,
A first period in one frame period, a second period is a period later than the first time period,
In the first period, the video signal voltage is applied to the first wiring connected to one input terminal of the comparator of each pixel in a state where the light emission of the current driven light emitting element in all the pixels is stopped. Write
In the second period, a voltage that changes multiple times from the first level to the second level is written to the second wiring connected to the other input terminal of the comparator of each pixel. A driving method of a display device, wherein the current-driven light emitting element of each pixel emits light for a period determined by a written video signal voltage and the voltage. 前記第１レベルから第２レベルまで複数回にわたって変化する電圧は、傾斜波電圧であることを特徴とする請求項１に記載の表示装置の駆動方法。  2. The method of driving a display device according to claim 1, wherein the voltage changing a plurality of times from the first level to the second level is a ramp voltage. 前記傾斜波電圧は、ランプ波形であることを特徴とする請求項２に記載の表示装置の駆動方法。  The display device driving method according to claim 2, wherein the ramp voltage is a ramp waveform. 前記映像信号電圧は、発光輝度が低い程第１レベルの電圧との電位差が小さくなる電圧であることを特徴とする請求項１に記載の表示装置の駆動方法。  2. The method of driving a display device according to claim 1, wherein the video signal voltage is a voltage in which a potential difference from a first level voltage is smaller as light emission luminance is lower. 前記映像信号電圧は、発光輝度が高い程第１レベルの電圧との電位差が大きくなる電圧であることを特徴とする請求項１に記載の表示装置の駆動方法。  2. The method of driving a display device according to claim 1, wherein the video signal voltage is a voltage that increases in potential difference from the first level voltage as the light emission luminance increases.
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