JP4572523B2 - Pixel circuit driving method, driving circuit, electro-optical device, and electronic apparatus - Google Patents

Description

The present invention relates to a driving method, a driving circuit, an electro-optical device, and an electronic apparatus for a pixel circuit having an electro-optical element such as an organic light-emitting diode element.

In recent years, organic light-emitting diodes (Organic) have been developed as next-generation light-emitting devices that replace liquid crystal elements.
Light Emitting Diode (hereinafter abbreviated as OLED as appropriate) is drawing attention. OLED
The element is also called an organic electroluminescence element or a light emitting polymer. Since this OLED element is a self-luminous type, it has less viewing angle dependency, and since it does not require a backlight or reflected light, it is suitable for low power consumption and thinning. In some cases, it has excellent characteristics.
Here, the OLED element does not have voltage holding property like the liquid crystal element, and when the current is interrupted,
This is a current-type driven element that cannot maintain the light emission state. For this reason, when driving an OLED element by an active matrix method, a voltage holding element is provided to hold the gate voltage of a driving transistor that supplies current to the OLED element, and according to the gradation of the pixel during the selection period. A configuration in which a voltage is written to the gate of a driving transistor is common. According to this configuration, since the gate voltage of the drive transistor is held by the voltage holding element even in the non-selection period, it is possible to continuously pass a current corresponding to the gate voltage to the OLED element.

By the way, in this configuration, the threshold voltage of the driving transistor varies, and the brightness of the OLED element is different for each pixel circuit, and the display quality is deteriorated. Therefore, in recent years, the drive transistor is diode-connected in the selection period, and the current flowing through the drive transistor and the data line is controlled to have a value corresponding to the image data indicating the gradation (luminance) of the pixel. Thus, a technique has been proposed that compensates for variations in threshold voltage characteristics of the drive transistor by programming the gate of the drive transistor to write a voltage corresponding to the current to be passed through the OLED element (for example, Patent Document 1).
Japanese Patent Laying-Open No. 2003-22049 (see FIG. 17)

However, in this technique, when the parasitic capacitance of the data line is large and the current flowing through the data line is small, it takes time to charge and discharge the parasitic capacitance, and the gate of the drive transistor is targeted within the selection period. A new problem was pointed out that the voltage to be written could not be written.
The case where the current passed through the data line is small corresponds to the case where the OLED element is darkened to emit light, and the writing error which is the difference between the voltage to be written to the gate and the actually written voltage will be described later. Thus, it depends on characteristics such as a threshold voltage of the driving transistor. In addition, since the writing cannot catch up within the selection period at the time of low gradation display and the characteristics of the driving transistor vary, the gate voltage of the driving transistor also varies, resulting in noticeable luminance unevenness.
The present invention has been made in view of the above-described circumstances, and an object thereof is OLE even when the parasitic capacitance of the data line is large and the current flowing through the data line is small.
It is an object of the present invention to provide a pixel circuit driving method, a driving circuit, an electro-optical device, and an electronic apparatus that can prevent luminance unevenness of an electro-optical element such as a D element.

In order to achieve the above object, a pixel circuit driving method according to the present invention is a pixel circuit provided at the intersection of a plurality of scanning lines and a plurality of data lines, each of which is selected when a scanning line is selected. A voltage holding element that holds a voltage corresponding to a current flowing through the data line, a drive transistor having a gate connected to one end of the voltage holding element, and an electro-optic element that emits light by a current controlled by the drive transistor. In the pixel circuit driving method, each pixel circuit is driven in a test period and a display period, and in the test period, a scanning line selection period is set longer than a horizontal scanning period in the display period, sequentially selecting the scanning lines, when selecting the scanning lines, flowing respectively a predetermined current to the data lines, a pre-selection of the scanning line have finished, the said drive transistor Of at timing after the gate voltage has reached the threshold voltage, the voltage of each data line is measured, the measured voltage, in the pixel circuit located at the intersection of the data line of the measurement of the scanning lines and voltage selected It obtains the characteristics of the driving transistor, in the display period, with sequentially selects the scanning lines for each of the horizontal scanning period, the image data for specifying the brightness of the electro-optical element in the pixel circuit located at the selected scanning line, the pixel Correction is performed based on the characteristics of the driving transistor obtained for the circuit, and a current corresponding to the corrected image data is supplied to the pixel circuit via the data line.
According to this driving method, when the characteristics of the driving transistor are obtained in the test period, the shortage of the current to be passed through the data line is found with respect to the current to be passed between the source and drain of the driving transistor. Therefore, by correcting the image data based on the characteristics of the driving transistor in the display period, the current with the added amount flows through the data line, so that the gate voltage of the driving transistor can be prevented from being written in time. The Further, according to this, since the horizontal scanning is performed at a slower speed than the display period in the test period, the target voltage is written at the timing before the end of the scanning line selection period. For this reason, when the voltage of the data line is measured at the timing, the drive transistor characteristic is accurately obtained.

In the driving method, in the test period, a threshold voltage is obtained as a characteristic of the driving transistor, correction data is calculated with reference to the threshold voltage, and the selected scanning line and voltage are measured with the correction data. Stored in association with the pixel circuit located at the intersection with the data line, and in the display period, the image data specifying the luminance of the electro-optic element of the pixel circuit located in the selected scanning line is associated with the pixel circuit. It is preferable to add the correction data stored in this way, and to pass a current corresponding to the added image data to the pixel circuit via the data line.
In the above driving method, the predetermined current may be varied for the test period, and the pixel circuit may be executed a plurality of times. This makes it possible to obtain the characteristics of the drive transistor with high accuracy.
In the above driving method, the voltage of each data line may be precharged to a predetermined voltage before the scanning line is selected in the test period and the display period. In this way, the state before the current is supplied to the data line does not depend on the previous write state and becomes uniform over all the data lines.
The present invention is not limited to the driving method of the electro-optical device, and can be realized as a driving circuit or an electro-optical device. Furthermore, since the electronic apparatus according to the present invention includes the electro-optical device as a display device, high-quality display with reduced occurrence of luminance unevenness can be achieved. Examples of such an electronic device include those described later.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of the electro-optical device according to the first embodiment of the present invention, and FIG. 2 is a block diagram illustrating a configuration of a display panel in the electro-optical device.
As shown in these drawings, in the electro-optical device 1, the display panel 100 is driven by the Y driver 12 and the X driver 20. In the display panel 100, pixel circuits 200 including OLED elements are arranged in a matrix of 240 rows × 320 columns as shown in FIG. In the present embodiment, the amount of current to the OLED element is converted to the pixel circuit 200 (pixel).
By controlling each time, a predetermined image is displayed in gradation. In the present embodiment, the array of the pixel circuits 200 is a matrix type of 240 rows × 320 columns, but the present invention is not limited to this array.

In the array of pixel circuits 200, 240 scanning lines 102 and lighting control lines 104 are provided so as to correspond to the number of rows in the matrix array, and each extend in the X direction. Each of the scanning line 102 and the lighting control line 104 forms a set and is also used as the pixel circuit 200 for one row.
The scanning signal GW is supplied to the scanning lines 102 in the first row, the second row, the third row _,.
RT-1 , G _WRT-2 , G _WRT-3 , ..., G _WRT-240 are supplied. here,
For convenience of explanation, a scanning signal supplied to the scanning line 102 in the i-th row (i is an integer satisfying 1 ≦ i ≦ 240) is denoted as _GWRT-i . The control signal G is applied to the lighting control line 104 in the i-th row.
_SET-i is supplied. These scanning line 102 and lighting control line 104 are respectively Y
It is driven by a driver (scanning line driving circuit) 12.

On the other hand, 320 data lines 112 are provided so as to correspond to the number of columns in the matrix arrangement, each extends in the Y direction, and one data line 112 corresponds to one column of the pixel circuit 2.
Also used for 00. The X driver (data line driving circuit) 20 applies data currents X-1, X-2, X-3 to the data lines 112 in the first, second, third,.
.., X-320 is supplied to drive these data lines 112. Here, for convenience of explanation,
A data current flowing through the data line 112 in the j-th column (j is an integer satisfying 1 ≦ j ≦ 320) is represented by X
Indicated as −j.

As shown in FIG. 2, each data line 112 is provided with an N-channel transistor 116 so as to correspond to each data line 112. The source of each transistor 116 is commonly connected to a power supply line 114 to which a high voltage Vdd of the power supply is applied, while the drain of the transistor 116 is connected to the corresponding data line 112. The gates of the transistors 116 are commonly connected to a control line 118 to which a control signal Pre is supplied. For this reason,
Since the transistor 116 is turned on when the control signal Pre becomes H level, each data line 1
12 is precharged to the voltage Vdd.
The power supply line 114 is connected to all the pixel circuits 200. In FIG. 2, the power line 11
4 extends in the Y direction in the matrix arrangement, but may extend in the X direction.
Although not shown in FIGS. 1 and 2, all the pixel circuits 200 are commonly grounded to the lower voltage Gnd of the power supply.

On the other hand, the control circuit 10 controls the operation of each unit such as the Y driver 12 and the X driver 20, and also specifies image data that specifies the gradation of each pixel in the form of a current to be passed through the OLED element.
Output for each pixel of 240 rows × 320 columns. In addition, the control circuit 10 controls the control signal Pr described above.
e and a signal Smp described later are also output.
The I / F (interface) 14 inputs image data output from the control circuit 10. The memory 16 has a storage area corresponding to pixels of 240 rows × 320 columns.
Then, the image data input by the I / F 14 is written in the memory 16 in the storage area of the pixel corresponding to the image data, and before the scanning line 102 is selected, the memory 16 is positioned on the scanning line. The image data for one line is read all at once.

On the other hand, the LUT (Look Up Table) 28 stores correction data for each gradation (luminance) for each pixel of 240 rows × 320 columns. The LUT 28 outputs correction data corresponding to the gradation specified by the image data corresponding to the pixels in the same row and column read from the memory 16. Since the image data is read for one row, the correction data for one row is also output from the LUT 28. Also,
The contents of the LUT 28 are rewritten by the correction data calculation circuit 26.
The correction circuit 18 corrects the image data read from the memory 16 with correction data of pixels in the same row and the same column as the image data.

The X driver 20 has a constant current circuit 22 for each data line 112. Here, each constant current circuit 22 will be described as a representative example corresponding to the data line 112 in the j-th column.
In the display period, when the scanning signal G _WRT-i becomes H level, the current specified by the image data of the pixel in the i-th row and j-th column is generated by the correction circuit 18 and is generated.
The data current X-j is supplied to the data line 112 in the jth column. On the other hand, in the test period, all constant current circuits 22 flow a current corresponding to a low gradation to the data line 112 as a data current Xj, as will be described later, regardless of the image data. Note that the direction in which the data current Xj flows is the direction from the data line 112 toward the constant current circuit 22 in the present embodiment.

The voltage measurement circuit 24 has voltages V−1 and V− of the data line 112 from the first column to the 320th column.
2, V-3,..., V-320 are respectively measured at timings specified by the signal Smp. The signal Smp is a timing immediately before the selection of each scanning line 102 from the first row to the 240th row in a test period to be described later, that is, the scanning signals G _WRT-1 , G _WRT-2 , G _{WRT. -3} ,..., _GWRT-240 is output at the timing immediately before switching from the H level to the L level, and is not output during the display period.
When the voltage measurement circuit 24 measures the voltages of the data lines 112 from the first column to the 320th column, the correction data calculation circuit 26 performs the following operation. That is, the correction data calculation circuit 26 will be described with reference to the voltage Vj of the data line 112 in the j-th column. First, the data line 112 was selected from the measured voltage Vj. A threshold voltage of a driving transistor (described later) included in the pixel circuit 200, which is located at the intersection with the scanning line 102, is obtained. Second, correction data is obtained from the threshold voltage for each gradation. Third, the correction data for the pixel in the stored contents of the LUT 28 is rewritten to the correction data for each calculated gradation. This operation is performed by the correction data calculation circuit 2
6 is executed for each pixel of one row from the first column to the 320th column.

Next, the electrical configuration of the pixel circuit 200 will be described in detail. FIG. 3 is a circuit diagram showing a configuration of the pixel circuit 200 located in i row and j column.
As shown in this figure, the pixel circuit 200 includes a driving transistor 212, transistors 214, 216, and 218 that function as switching elements, a capacitor 220 that functions as a voltage holding element, and an OLED element 230 that is an electro-optical element. Have. Of these, P
The source of the channel type driving transistor 212 is connected to the power supply line 114. The drain of the driving transistor 212 is connected to the source of the N-channel transistor 214 and the drains of the N-channel transistors 216 and 218, respectively.

The source of the transistor 218 is connected to the anode of the OLED element 230, and the OLED element 230
The cathode of the LED element 230 is grounded to the lower voltage Gnd of the power source. Transistor 2
The gate 18 is connected to the lighting control line 104 in the i-th row.
On the other hand, the gate of the driving transistor 212 is connected to one end of the capacitor 220 and the transistor 21.
4 drain. The other end of the capacitor 220 is connected to the power supply line 114. Further, the source of the transistor 216 is connected to the data line 112 in the j-th column, and the gate thereof is connected to the i-th scanning line 102 together with the gate of the transistor 214.

Although not directly related to the present invention, the pixel circuits 200 arranged in a matrix type are formed together with the scanning lines 102 and the data lines 112 on a transparent substrate such as glass. For this reason, the driving transistor 212 and the transistors 214, 216 as switching elements,
Reference numeral 218 denotes a TFT (thin film transistor) formed by a polysilicon process. The OLED element 230 has a structure in which a light emitting layer is sandwiched between a transparent electrode film such as ITO (indium tin oxide) as an anode and a single metal film such as aluminum or lithium or a laminated film thereof as a cathode on a substrate. It has become.

For convenience of explanation, the correction circuit 18, the voltage measurement circuit 24, the correction data calculation circuit 26, and the LUT 28 are not included, and the image data read from the memory 16 is not corrected.
The operation of the configuration (referred to as no correction configuration) supplied to the X driver 20 as it is will be described.
FIG. 4 is a timing chart for explaining the operation without correction. First, Y
The driver 12 starts from the start of one vertical scanning period (1F), the first row, the second row, the third row,.
The scanning lines 102 in the 240th row are selected one by one in order for each horizontal scanning period (1H), and only the scanning signal of the selected scanning line 102 is set to the H level. Here, the operation of the pixel circuit 200 will be described as a representative example of what is located in the i-th row and j-th column. First, before the scanning line 102 in the i-th row is selected, that is, the scanning signal G _WRT-i is Before becoming H level, the control signal Pr
Since e becomes H level, as a result of being precharged, the voltage V− of the data line 112 in the j-th column
j becomes the power supply voltage Vdd.

After that, when the scanning signal _GWRT-i becomes H level, the transistor 214 is turned on, so that the driving transistor 212 functions as a diode. Further, the scanning signal G _{WR
When Ti} is at H level, the transistor 216 is also turned on. However, the scanning signal G
_{Since the} lighting signal G _SET-i does not become H level during the period in which _WRT-i is at H level, the transistor 218 is in an off state. Therefore, the data current X-j is supplied from the power line 114.
The current flows through the path of the driving transistor 212 → the transistor 216 → the data line 112.
Accordingly, the gate voltage of the drive transistor 212 gradually reaches the voltage corresponding to the data current Xj from the precharge voltage Vdd and is written to one end of the capacitor 220. In this non-correction configuration, the constant current circuit 2 corresponding to the data line 112 in the j-th column
In 2, a data current X-j in which image data corresponding to a pixel in i row and j column is designated is supplied to the data line 112 in the j column.

Subsequently, when the scanning signal _GWRT-i becomes L level, the transistors 214 and 216 are both turned off, but the voltage holding state by the capacitor 220 is maintained. After that, the control signal G
_{When SET-i} becomes H level, the transistor 218 is turned on. So this time,
The current is the power line 114 → the driving transistor 212 → the transistor 218 → the OLED element 23.
It flows in the route of 0.
At this time, the current flowing through the OLED element 230 is determined by the gate voltage of the driving transistor 212. The gate voltage is the case where the scanning signal _GWRT-i is at the H level, and the data current Xj is the data line 112. Is a voltage held in the capacitive element 220 when flowing through the capacitor. For this reason, when the control signal G _SET-i becomes the H level, the current flowing through the OLED element 230 is equal to the data current X flowing through the data line 112 just before the sufficient writing time is secured. Since it substantially coincides with −j, the data current X−j that flows to the data line 112 when the scanning line 102 is selected flows to the OLED element 230 in a regenerated form. Thereafter, light emission is continued at a luminance corresponding to the current until the control signal G _SET-i becomes L level.

However, actually, even if the data current Xj flows through the data line 112, the data line 11
Due to the parasitic capacitance 113 (see FIG. 3) 2 and the like, one end of the capacitance 220, that is, the gate of the driving transistor 212 does not quickly reach the target voltage. The scanning line 102 is selected every horizontal scanning period (1H). When this period becomes shorter as the definition becomes higher, for example, only about 50 μsec can be secured, the scanning signal G _WRT-i is at the H level. The period is further shortened, and the selection of the gate of the driving transistor 212 is completed before reaching the target voltage to be finally written by flowing the data current Xj.
In detail, the gate voltage of the driving transistor 212 is the transistor 214,
If 216 is on, it appears on the data line 112 in the j-th column, and as shown in FIG. 4, before the voltage Vj of the data line 112 reaches the target voltage, the scanning signal G _W
RT-i becomes L level. For this reason, with no correction configuration, there is a difference between the target voltage and the voltage actually written to the gate of the drive transistor 212. This difference becomes a write error, and the current flowing through the OLED element 230 is the target. Deviation from current.

Here, the current Id (control signal G) flowing between the source and the drain of the driving transistor 212.
_The current that flows in the OLED element 230 when _SET-i becomes H level) and the data current Xj before correction are in a relationship as shown in FIG.
Consider a case where the luminance of the element 230 is designated by 8 gradations. That is, when the gradation levels 1 to 8 are specified by the image data, the current Id of the driving transistor 212 is set to be the gradation currents I-1 to I-8, respectively, and in that case, the data line Let us consider the case where the set currents to be passed through are Idata-1 to Idata-8, respectively.

FIG. 6 shows a case where horizontal scanning is performed at the timing shown in FIG.
That is, when the data current Xj is shaken in the case where one horizontal scanning period (1H) is 50 μsec), it is a diagram showing what the current Id that actually flows between the source and drain of the drive transistor 212 becomes. . As shown in this figure, as the data current Xj decreases (that is, as the current Id of the driving transistor is decreased to instruct the OLED element 230 to emit light darkly), the driving with respect to the set current is performed. The transistor 212 has a current Id
Does not flow, and it can be seen that the writing error is increased.
It can also be seen that the write error tends to increase as the threshold voltage of the drive transistor 212 increases. For this reason, if the threshold voltage of the driving transistor 212 varies for each pixel circuit 200, even if the same data current flows, the gate voltage of the driving transistor 212 varies particularly during low gradation display, and the current Id also varies. As a result, luminance unevenness is conspicuous.

By the way, it can be understood from FIG. 6 that if the threshold voltage of the driving transistor 212 can be obtained, the setting currents Idata-1 to Idata-8 are respectively set for the gradation currents I-1 to I-8 flowing in the OLED element 230. It is a point that an undercurrent with respect to can be obtained. Specifically, when the threshold voltage of the drive transistor 212 is obtained and is found to be characteristic a in FIG. 6, as shown in FIG. 7, for each of the grayscale currents I-1 to I-4, respectively. The shortage currents for the set currents Idata-1 to Idata-4 are shown in FIG.
a to Idata-4a. Since the writing error is small when the set current is large, for example, in FIG. 7, the shortage current with respect to the set currents Idata-5 to Idata-8 may be considered to be zero.
When the gradation levels are 1 to 4, the current corresponding to the data obtained by adding the shortage currents Idata-1a to Idata-4a to the set currents Idata-1 to Idata-4 is represented by the data current X-
If j is passed through the data line 112, the drain current I of the drive transistor 212 is
Since d becomes the gradation currents I-1 to I-4, the influence due to the writing error should be suppressed.

However, for this purpose, the threshold voltage of the drive transistor 212 must be obtained for each pixel circuit 200. For this reason, in the present embodiment, generally speaking, a test period is provided, and the threshold voltage of the drive transistor 212 is obtained for each pixel circuit 200, and correction data corresponding to an insufficient current is obtained from the threshold voltage by the pixel circuit. The configuration is calculated every 200 and set in the LUT 28.
This test period is, for example, at the time of factory shipment, immediately before the display is turned on (immediately after the power is turned on and before the display or immediately before returning from the standby mode), immediately after the display is turned off (immediately before the power is turned off and after the display, Alternatively, a period in which no display is performed is preferable, such as immediately after shifting to the standby mode. The test period is instructed by the control circuit 10.

First, the detailed operation during the test period in this embodiment will be described. FIG. 8 is a timing chart for explaining the operation in the test period. The operation in the test period is not fundamentally different from the operation without correction in FIG. 4, but each pixel circuit 200 is horizontally scanned at a speed 10 times slower than the scanning shown in FIG. That is, one horizontal scanning period (1H) in the test period is set to 500 μsec.

On the other hand, all of the constant current circuits 22 in the X driver 20 flow the set current Idata-1 corresponding to the lowest gradation current I-1 in the OLED element 230 to the data line 112 as a data current.
As shown in FIG. 4, when one horizontal scanning period (1H) is not sufficiently secured and the period during which the scanning signal G _WRT-i is at the H level is short, the gate of the driving transistor 212 reaches the target voltage. Before, the selection of the scanning line 102 is completed. As shown in FIG. 8, when the period during which the scanning signal G _WRT-i is at the H level is sufficiently long, the gate of the driving transistor 212 becomes the target voltage. And the selection of the scanning line 102 is completed.

By the way, the set current Idata-1 corresponds to the current when the drain current starts to flow in the driving transistor 212, in other words, the gate-source voltage at this time may be considered as the threshold voltage of the driving transistor 212.
Therefore, at the timing immediately before the scanning signal G _WRT-i becomes the L level, the voltage Vj is obtained, and the voltage Vj is subtracted from the voltage Vdd, whereby the selected scanning line 102 and the jth column are obtained. The threshold voltage of the driving transistor 212 located at the intersection with the data line 112 can be obtained. Strictly speaking, when calculating the threshold voltage, voltage drop due to the on-resistance of the transistor 216, the wiring resistance of the data line 112, the power supply line 114, and the like must be considered. Since it is small, the voltage drop at that time can be ignored.

In order to obtain the threshold voltage, in this embodiment, the voltage measurement circuit 24 uses the voltages V-1 to V-320 of the data lines 112 in the first to 320th columns at the timing indicated by the signal Smp.
Measure each.
When the voltages V-1 to V-320 are measured, the correction data calculation circuit 26 performs the following operation. That is, the correction data calculation circuit 26 first subtracts the voltage V-j measured, for example, at the data line 112 in the j-th column from the power supply voltage Vdd, and drives the driving transistor 212 in the pixel circuit 200 in the i-th row and j-th column. The threshold voltage is obtained. Secondly, as shown in FIG. 7, the correction data calculation circuit 26 converts the insufficient currents Idata-1a to Idata-8a necessary for flowing the grayscale currents from the obtained threshold voltage characteristics into grayscale levels. It asks for every level 1-8. Here, since the writing error is small in the region where the gradation level is large, the shortage may be set to zero. Thirdly, the correction data calculation circuit 26 determines the obtained undercurrent Idata-1a to Idata.
The data corresponding to −8a is converted into data and obtained as correction data, and written to the area corresponding to the pixel in i row and j column in the LUT 28.

The correction data calculation circuit 26 performs conversion and writing of such correction data over all the pixels from the first column to the 320th column located in the i-th row. In addition, this 1
The correction data calculation circuit 26 repeatedly performs the operation for the rows every time the scanning line 102 is selected over all rows from the first row to the 240th row. As a result, the correction data is written in the LUT 28 for every gradation level 1 to 8 over all the pixels of 240 rows × 320 columns. When the writing to the LUT 28 is completed for all pixels, the test period ends.

Next, the operation during the display period will be described. FIG. 9 is a timing chart for explaining the operation in the display period. The operation during the display period is not fundamentally different from the operation without correction in FIG. 4, but the constant current circuit 22 in the X driver 20 is not the current specified by the image data corresponding to the pixel in i row and j column, The current specified by the image data corrected by the correction data is supplied to the data line 112 in the jth column as the data current Xj.

More specifically, before the scanning signal G _WRT-i becomes H level, the memory 16 reads i
One row of image data of pixels located on the scanning line 102 in the row is read out. Of these, the pixel located at the intersection with the j-th data line, that is, the pixel in the i-th row and j-th column will be described as a representative example. Correction data corresponding to the gradation level specified by the image data of the pixel is as follows. LUT2
8 is read out. Further, the image data of the pixels in the i-th row and j-th column read from the memory 16 is added and corrected by the correction circuit 18 with the correction data for the pixels in the i-th row and j-th column read from the LUT 28. Of the constant current circuits 22 in the X driver 20, the constant current circuit 22 in the j _-th column corrects the image data corrected for the pixels in the i-th row and j-th column when the scanning signal G _WRT-i becomes H level. Is generated as data current Xj and j
The data is sent to the data line 112 in the column. As a result, the shortage current of the pixel is added to the set current based on the image data of the pixel. For example, if the gradation level is 1, the constant current circuit 22 in the j-th column has an insufficient current Idata indicated by the correction data in the set current Idata-1 as shown in FIG.
The constant current circuit 22 in the j-th column passes the current added with −1 to the data line 112 as the data current X−j.

For this reason, according to the present embodiment, immediately before the scanning signal _GWRT-i switches from the H level to the L level, the gate voltage of the driving transistor (that is, the voltage Vj of the data line 112 in the j-th column) is Since the voltage is such that a gradation current corresponding to the gradation level specified by the image data flows, it is possible to prevent the above-described writing error and display unevenness due to this. .
In the first embodiment, the setting current Idata-1 corresponding to the lowest luminance is supplied to the data line 112 during the test period. For example, the gradation level is relatively dark, for example, the gradation levels 2 to 2 are used. The threshold voltage of the drive transistor 212 may be obtained from the data voltage at that time by passing the set currents Idata-2 to Idata-4 corresponding to 4. However, when the current increases, the voltage drop must be taken into account, and the threshold voltage of the driving transistor 212 cannot be obtained with high accuracy, so that the set current I data − corresponding to the lowest luminance is also obtained.
1 is preferred.

Next, a second embodiment of the present invention will be described. In the first embodiment described above, the scanning speed is set slower than the display period in order to obtain the threshold voltage of the driving transistor 212.
For example, when the test period is executed immediately before the display is turned on, there is a disadvantage that it takes a long time until the display is actually started. Therefore, a second embodiment that eliminates this drawback will be described.

FIG. 10 is a timing chart for explaining the operation in the test period in the second embodiment. The scanning speed in the test period is the same as the display period in the first embodiment shown in FIG. However, in the first embodiment, the data current in the test period is the set current Idata-1 corresponding to the lowest luminance gradation level 1, whereas in the second embodiment, the highest luminance gradation is obtained. The difference is that the set current Idata-8 corresponds to level 8.

Explaining this difference, as shown in FIG. 7 described above, when the set current is increased, charging / discharging of the capacitor 113 and the like is completed within a short time. Therefore, the horizontal speed of the test period is set to be the same as that of the display period. However, the write error should be small enough to be ignored. Therefore,
Even when the horizontal scanning speed in the test period is the same as that in the display period, the gate of the driving transistor 212 (at the timing immediately before the scanning signal _GWRT-i switches from the H level to the L level)
One end of the capacitor 220 is considered to have reached the target voltage corresponding to the set current Idata-8.

However, since the set current Idata-8 is considerably large unlike the set current Idata-1 in the first embodiment, the correction data calculation circuit 26 performs the following operation of the drive transistor 21.
2 threshold voltage is obtained.
Here, when only the threshold voltage is different among the characteristics of the driving transistor 212, the characteristics of the gate-source voltage and the drain current change as shown in FIG. The current Idata-8 is supplied to change the drain current Id to the gradation current I-8, and the measured data voltage Vj at that time is subtracted from the power supply voltage Vdd to obtain the gate-source voltage of the drive transistor 212. The characteristic is uniquely determined by obtaining. Therefore, the correction data calculation circuit 26 determines the drain current I from the uniquely determined characteristic.
The threshold voltage at which d begins to flow can be determined.

The operation after the correction data calculation circuit 26 obtains the threshold voltage of the drive transistor 212 is the same as in the first embodiment.
Therefore, according to the second embodiment, the time required for the test period can be shortened, and in the subsequent display period, it is possible to prevent the above-described writing error and display unevenness due to this, respectively. It becomes.
In the second embodiment, the set current Idata-8 corresponding to the highest luminance is supplied to the data line 112 during the test period. If the write error is small enough to be ignored, for example,
A set current Idata− corresponding to a relatively bright gradation level, for example, gradation levels 5 to 7
It may be 5 to Idata-8.

In the second embodiment, it is assumed that only the threshold voltage is different among the characteristics of the driving transistor 212. However, in the characteristics of the driving transistor 212, when not only the threshold voltage but also the current amplification factor is different for each pixel circuit 200, as shown in FIG. Even if the source voltage is obtained, the characteristics of the gate-source voltage and the drain current of the driving transistor 212 cannot be uniquely determined.
Therefore, in the second embodiment, during the test period, the drain current Id of the driving transistor 212 is divided into a plurality of times so as to be different from each other, and the voltage of the data line 112 is measured at each time. The characteristics of the drain current and the gate-source voltage can be uniquely determined, and the insufficient current when the drain current Id is relatively small can be calculated more accurately.
Also in the first embodiment, it is needless to say that the drain current Id of the driving transistor 212 may be divided into a plurality of times so as to be different from each other during the test period.

Further, in the first and second embodiments, the Y driver 12 is, for example, the control signal G _SET-i.
Is set to L level immediately before the scanning signal G _WRT-i becomes H level, and the scanning signal G _WRT-i
Is set to H level immediately after the signal becomes L level, but the control signals G _SET-1 to G _{SET-24
It is sufficient} that all periods up to ₀ have the same H level period. Here, the control signal G
_{For all of SET-1} to _GSET-240 , if the H level period is shortened, the proportion of the light emission period in one vertical scanning period (1F) is shortened over all the OLED elements 230. On the other hand, if the period during which the level is H is lengthened, the display image becomes brighter, so that the brightness of the display image can be adjusted.

The present invention is not limited to the above-described embodiments, and various applications and modifications are possible.
For example, in the embodiment, gradation display is performed for a single-color pixel. However, color is generated in R (red), G (green), and B (blue) for each of the three pixels. In addition, the light emitting layer of the OLED element 230 may be selected, and one dot may be configured by these three pixels to perform color display. The OLED element 230 is an example of a current-driven element.
Instead of this, an inorganic EL element, a field emission (FE) element, another light emitting element such as an LED, an electrophoretic element, an electrochromic element, or the like may be used.
In the embodiment, the display is 8 gradations, but it is also possible to display 4 gradations with low gradations, or to 16, 32, 64, ..., gradations with higher gradations. Of course.

In the embodiment, the driving transistor 212 is a P-channel type, but may be an N-channel type. Further, the channel types of the transistors 214, 216, and 218 as switching elements are not limited to the embodiment, and may be P-channel types. Furthermore, if the transistors 214, 216, and 218 as switching elements are composed of transmission gates that are a combination of a P-channel type and an N-channel type, the voltage drop can be suppressed to an almost negligible level. It is preferable in that it can be obtained.
In addition, the OLED element 230 may be connected to the drain side of the transistor 214 instead of connecting the OLED element 230 to the source side of the transistor 214.

Next, an example in which the electro-optical device according to the above-described embodiment is used in an electronic device will be described.
First, a mobile phone in which the electro-optical device 1 is applied to a display unit will be described. FIG. 12 is a perspective view showing the configuration of this mobile phone.
In this figure, a mobile phone 1100 includes a plurality of operation buttons 1102 and an earpiece 11.
04, together with the mouthpiece 1106, the display panel 1 of the electro-optical device 1 described above as a display unit
00.

Next, a digital still camera using the above-described electro-optical device 1 as a finder will be described.
FIG. 13 is a perspective view showing the back surface of the digital still camera. The silver salt camera sensitizes the film with the optical image of the subject, whereas the digital still camera 1200 generates and stores an imaging signal by photoelectrically converting the optical image of the subject with an imaging device such as a CCD (Charge Coupled Device). To do. Here, the display panel 100 of the electro-optical device 1 described above is provided on the back surface of the case 1202 in the digital still camera 1200. Since the display panel 100 performs display based on the imaging signal, it functions as a finder for displaying the subject. In addition, a light receiving unit 1204 including an optical lens, a CCD, and the like is provided on the front side of the case 1202 (the back side in FIG. 12).

The photographer confirms the subject image displayed on the display panel 100, and the shutter button 1
When 206 is pressed, the CCD image pickup signal at that time is transferred and stored in the memory of the circuit board 1208. In the digital still camera 1200, the case 120
On the second side, a video signal output terminal 1212 for external display and an input / output terminal 1214 for data communication are provided.

In addition to the mobile phone of FIG. 12 and the digital still camera of FIG. 13, the electronic devices include a television, a viewfinder type, a monitor direct view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator. , Word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. And it cannot be overemphasized that the electro-optical apparatus mentioned above is applicable as a display part of these various electronic devices.

1 is a block diagram illustrating a configuration of an electro-optical device to which a driving method according to a first embodiment of the present invention is applied. 3 is a block diagram illustrating a configuration of a display panel in the same electro-optical device. FIG. 2 is a circuit diagram illustrating a configuration of a pixel circuit in the display panel. FIG. It is a figure for demonstrating the writing error in the same electro-optical apparatus. It is a figure which shows the relationship between the source-drain current of the drive transistor in the same display panel, and a data current. It is a figure which shows the relationship between the setting electric current in the same electro-optical apparatus, and the electric current sent through an OLED element. It is a figure which shows the calculation procedure of the correction data in the same electro-optical device. 3 is a timing chart showing an operation during a test period in the display panel. 4 is a timing chart showing an operation during a display period in the display panel. 12 is a timing chart for explaining an operation in a test period of an electro-optical device to which a driving method according to a second embodiment of the present invention is applied. It is a figure for demonstrating the drive method which concerns on the application form of this invention. It is a figure which shows the mobile telephone using the same electro-optical apparatus. It is a figure which shows the digital still camera using the same electro-optical apparatus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical device, 10 ... Control circuit, 12 ... Y driver, 18 ... Correction circuit, 20 ... X driver, 22 ... Constant current circuit, 24 ... Voltage measurement circuit, 26 ... Correction data calculation circuit, 28 ...
LUT, 100 ... display panel, 102 ... scanning line, 104 ... lighting control line, 112 ... data line, 114 ... power line, 200 ... pixel circuit, 212 ... drive transistor, 212, 214, 2
16, 218 ... transistor, 220 ... capacitor, 230 ... OLED element, 1100 ... mobile phone, 1200 ... digital still camera

Claims (7)

A pixel circuit provided at the intersection of a plurality of scanning lines and a plurality of data lines, each of which
A voltage holding element that holds a voltage corresponding to a current flowing through the data line when the scanning line is selected;
A driving transistor having a gate connected to one end of the voltage holding element;
In a driving method of a pixel circuit having an electro-optic element that emits light by a current controlled by the driving transistor,
Drive each pixel circuit divided into test period and display period,
In the test period,
A scanning line selection period is set longer than a horizontal scanning period in the display period, and the scanning lines are sequentially selected,
When a scanning line is selected, a predetermined current is supplied to each data line,
Before the selection of the scanning line is completed, at the timing after the gate voltage of the driving transistor reaches the threshold voltage, the voltage of each data line is measured,
From the measured voltage, determine the characteristics of the drive transistor in the pixel circuit located at the intersection of the selected scan line and the data line where the voltage was measured,
In the display period,
The scanning lines are sequentially selected for each horizontal scanning period, and image data specifying the luminance of the electro-optic element of the pixel circuit located on the selected scanning line is corrected based on the characteristics of the driving transistor obtained for the pixel circuit. And
A method for driving a pixel circuit, wherein a current corresponding to the corrected image data is supplied to the pixel circuit via a data line. Prior Symbol test period, as a characteristic of the driving transistor, the threshold voltage determined, to calculate the correction data with reference to the threshold voltage, the correction data, and the data line of the measurement of the selected scanning lines and the voltage Stored in association with the pixel circuit located at the intersection of
In the display period, the correction data stored in association with the pixel circuit is added to the image data designating the luminance of the electro-optical element of the pixel circuit located on the selected scanning line, and the current corresponding to the added image data The pixel circuit driving method according to claim 1, wherein the current is supplied to the pixel circuit via a data line. For the previous Symbol test period,
The method of driving a pixel circuit according to claim 1, wherein the predetermined current is varied and executed for each pixel circuit a plurality of times. Before SL before selecting the scanning lines in the test period and the display period, the driving method of the pixel circuit according to claim 1 for precharging the voltage of each data line to a predetermined voltage. A pixel circuit provided at intersections of the multiple scanning lines and a plurality of data lines, each of which
A voltage holding element that holds a voltage corresponding to a current flowing through the data line when the scanning line is selected;
A driving transistor having a gate connected to one end of the voltage holding element;
A driving circuit for driving a pixel circuit having an electro-optic element that emits light by a current controlled by the driving transistor in a test period and a display period;
A scanning line driving circuit that sequentially selects the scanning lines during the test period and the display period, wherein the scanning lines are sequentially selected for each horizontal scanning period during the display period, and scanning during the test period; A scanning line driving circuit for setting a line selection period longer than the horizontal scanning period of the display period;
In the test period, a voltage measuring circuit that measures the voltage of each data line before the scanning line selection ends and at a timing after the gate voltage of the driving transistor reaches a threshold voltage,
Correction data for obtaining a threshold voltage in a driving transistor of a pixel circuit located at the intersection of the selected scanning line and the data line for which the voltage is measured from the measured voltage and calculating correction data with reference to the threshold voltage A calculation circuit;
A table for storing the calculated correction data in association with the pixel circuit located at the intersection of the selected scanning line and the data line whose voltage is measured;
In the display period, a correction circuit that corrects the image data specifying the luminance of the electro-optical element of the pixel circuit located on the selected scanning line with the correction data stored in the table in association with the pixel circuit;
In the test period, a predetermined current is supplied to each data line, while in the display period, when a scanning line is selected, a current corresponding to the corrected image data is supplied to the pixel circuit via the data line. And a data line driving circuit for flowing through the pixel circuit. A pixel circuit provided at intersections of the multiple scanning lines and a plurality of data lines, each of which is a voltage holding element for holding a voltage corresponding to the current flowing through the data line when the scanning line is selected A pixel circuit having a drive transistor having a gate connected to one end of the voltage holding element, and an electro-optic element that emits light by a current controlled by the drive transistor;
An electro-optical device comprising: the drive circuit according to claim 5 . An electronic apparatus, comprising a display device the electro-optical device according to 請 Motomeko 6.

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