JP4030784B2 - 層間接続方法と装置及び多層基板 - Google Patents

層間接続方法と装置及び多層基板 Download PDF

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Publication number
JP4030784B2
JP4030784B2 JP2002088265A JP2002088265A JP4030784B2 JP 4030784 B2 JP4030784 B2 JP 4030784B2 JP 2002088265 A JP2002088265 A JP 2002088265A JP 2002088265 A JP2002088265 A JP 2002088265A JP 4030784 B2 JP4030784 B2 JP 4030784B2
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substrate
hole
intermediate electrode
inner chamber
conductor portion
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Expired - Fee Related
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Japanese (ja)
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JP2003283124A (ja
JP2003283124A5 (cg-RX-API-DMAC7.html
Inventor
博 早田
昌裕 山本
忠司 木村
信 長谷川
裕子 大谷
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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JP2002088265A 2002-03-27 2002-03-27 層間接続方法と装置及び多層基板 Expired - Fee Related JP4030784B2 (ja)

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JP2002088265A JP4030784B2 (ja) 2002-03-27 2002-03-27 層間接続方法と装置及び多層基板

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JP2002088265A JP4030784B2 (ja) 2002-03-27 2002-03-27 層間接続方法と装置及び多層基板

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JP2003283124A JP2003283124A (ja) 2003-10-03
JP2003283124A5 JP2003283124A5 (cg-RX-API-DMAC7.html) 2005-09-15
JP4030784B2 true JP4030784B2 (ja) 2008-01-09

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Publication number Priority date Publication date Assignee Title
IT201700083957A1 (it) * 2017-07-24 2019-01-24 Wise S R L Metodo e apparato per il trattamento di pannelli

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