JP4024954B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP4024954B2
JP4024954B2 JP02996999A JP2996999A JP4024954B2 JP 4024954 B2 JP4024954 B2 JP 4024954B2 JP 02996999 A JP02996999 A JP 02996999A JP 2996999 A JP2996999 A JP 2996999A JP 4024954 B2 JP4024954 B2 JP 4024954B2
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Japan
Prior art keywords
drain
diffusion layer
substrate
impurity diffusion
source
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Expired - Fee Related
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JP02996999A
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English (en)
Japanese (ja)
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JPH11289089A (ja
JPH11289089A5 (enrdf_load_stackoverflow
Inventor
一也 松澤
彰 西山
建 内田
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Toshiba Corp
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Toshiba Corp
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Priority to JP02996999A priority Critical patent/JP4024954B2/ja
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Publication of JPH11289089A5 publication Critical patent/JPH11289089A5/ja
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  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP02996999A 1998-02-06 1999-02-08 半導体装置及びその製造方法 Expired - Fee Related JP4024954B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP02996999A JP4024954B2 (ja) 1998-02-06 1999-02-08 半導体装置及びその製造方法

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2571298 1998-02-06
JP10-25712 1998-09-08
JP02996999A JP4024954B2 (ja) 1998-02-06 1999-02-08 半導体装置及びその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007239588A Division JP2008053739A (ja) 1998-02-06 2007-09-14 半導体装置

Publications (3)

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JPH11289089A JPH11289089A (ja) 1999-10-19
JPH11289089A5 JPH11289089A5 (enrdf_load_stackoverflow) 2005-10-06
JP4024954B2 true JP4024954B2 (ja) 2007-12-19

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JP02996999A Expired - Fee Related JP4024954B2 (ja) 1998-02-06 1999-02-08 半導体装置及びその製造方法

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JP (1) JP4024954B2 (enrdf_load_stackoverflow)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4592649B2 (ja) * 2000-07-11 2010-12-01 株式会社東芝 半導体装置の製造方法
KR100975523B1 (ko) * 2003-12-30 2010-08-13 삼성전자주식회사 조절된 이동도를 가지는 반도체 소자 및 이를 적용한 ｔｆｔ
JP5091403B2 (ja) * 2005-12-15 2012-12-05 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
WO2009090974A1 (ja) * 2008-01-16 2009-07-23 Nec Corporation 半導体装置及びその製造方法
US9190346B2 (en) 2012-08-31 2015-11-17 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9817928B2 (en) 2012-08-31 2017-11-14 Synopsys, Inc. Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits
US9379018B2 (en) 2012-12-17 2016-06-28 Synopsys, Inc. Increasing Ion/Ioff ratio in FinFETs and nano-wires
US8847324B2 (en) 2012-12-17 2014-09-30 Synopsys, Inc. Increasing ION /IOFF ratio in FinFETs and nano-wires

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Publication number Publication date
JPH11289089A (ja) 1999-10-19

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