JP3994676B2 - Liquid crystal display - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal display device and a drive circuit thereof, and more particularly to a drive circuit that provides a liquid crystal display device with excellent display quality.
[0002]
[Prior art]
In the liquid crystal display device, each pixel arranged in a matrix has an active element such as a TFT (Thin Film Transistor), the gate electrode of each active element is connected to a common gate line in the row direction, and the drain electrode is As a method of driving an active matrix liquid crystal panel connected to a common drain line in the column direction, the voltage applied to the common electrode (hereinafter referred to as common electrode) of each pixel is constant, and gradation display is realized by changing the voltage applied to the source electrode. There is a way to do it. In this driving method, for each pixel, a source voltage having a polarity different from that of a pixel adjacent in the gate direction (here, the polarity indicates the polarity of the pixel electrode voltage with respect to the common electrode voltage) is applied, There is a driving method in which source voltages having different polarities are applied to pixels adjacent in the drain line direction, and this driving method is hereinafter referred to as 1-line dot inversion driving. Similarly, for each pixel, there is a driving method in which source voltages having different polarities are applied to pixels adjacent in the gate direction, and source voltages having different polarities are applied every N pixels in the drain line direction. Hereinafter, this driving method is referred to as N-line dot inversion driving. FIG. 10 shows the polarity of the pixel electrode voltage when N = 2 in the one-line dot inversion driving and the N-line dot inversion driving described above.
[0003]
As a method for improving image quality in one-line dot inversion driving, for example, there is JP-A-2000-305534.
[0004]
[Problems to be solved by the invention]
The line dot inversion drive has a problem in that flicker is strongly generated because the drain voltage applied per frame is biased to the positive side or the negative side in a specific display pattern as shown in FIG. Hereinafter, such a display pattern is referred to as a cancel pattern. As a method for preventing this, it is possible to eliminate gaps by performing alternating current every even number of lines, such as two-line dot inversion, and thus flicker can be greatly reduced.
[0005]
However, in the case of two-line alternating current, as shown in FIG. 12, when the same source voltage is to be written to the pixel electrode, the resistance changes and the capacitance component of the drain line changes from a line whose polarity has changed compared to the previous line. The voltage values to be written in the lines that are not used differ, and even when solid display is performed, display unevenness and horizontal stripes may occur.
[0006]
An object of the present invention is to provide a liquid crystal display device with less display unevenness in N-line dot inversion driving.
[0007]
[Means for Solving the Problems]
In order to solve the above object, the liquid crystal display device of the present invention changes the period during which the TFT of each pixel is turned on in accordance with the AC cycle. Specifically, the period in which the TFT is turned on is relatively long in the line where the alternating current is performed, and the period is relatively short in the line where the alternating current is not performed.
[0008]
Also, a reference voltage (a substantially intermediate voltage between positive and negative polarity) is applied to the drain line of the line whose polarity does not change before applying the drain voltage.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the first embodiment will be described with reference to FIGS. The first embodiment is a system having a gradation voltage generation circuit externally (for example, a liquid crystal controller or the like), and here, an example in the case of alternating current with two lines is shown.
[0010]
FIG. 1 is a diagram showing a configuration of a liquid crystal display device according to the first embodiment, in which 101 is a liquid crystal display panel, 102 is a display signal group input from an external system (not shown), and 103 is a display signal group 102. Liquid crystal control circuits A and 104 for converting signals suitable for 101 are a drain driver control signal group and display data, 105 is a gate driver control signal group, 106 is a liquid crystal control circuit B, 107 is a gate selection signal, and 108 is a gradation voltage. Control signal, 109 is an external input voltage, 110 is a power supply circuit, 111 is a drain driver input voltage, 112 is a gate driver input voltage, 113 is a gradation voltage generation circuit, 114 is a gradation voltage, 115 is a drain driver, 116 Is a gate driver.
[0011]
FIG. 2 shows the configuration of the liquid crystal control circuit B106. 201 is a frequency dividing circuit, 202 is a 2-bit counter circuit, 203 is an exclusive OR circuit, 204 is a counter circuit, and 205 is counted by the counter 204. The count values 206 and 208 are comparison circuits that output a high level in a period in which the stored value and the input signal coincide with each other during a period in which the selection signal is at a high level. A comparison circuit that outputs a low level during a period in which the stored value and the input signal coincide with each other, 210 is a NOR circuit, and 211 is an OR circuit.
[0012]
FIG. 3 is a diagram showing a configuration of the power supply circuit 110, where VEE and VSS are voltage values of reference gradation voltages input from the power supply circuit 110, 301-0 to 301-11 are voltage dividing circuits configured by resistors, and V0. ˜V9 are gradation voltages generated by the voltage dividing circuits 302-0 to 301-11, Vcen is a center voltage, 302-0 to 302-9 are analog switches switched by the gradation voltage control signal 106, and 303-0. Reference numerals 303-9 to 9 are voltage follower circuits, and 304-0 to 304-9 are capacitors.
[0013]
FIG. 4 is a diagram showing the operation timing of the additional control circuit in the first embodiment.
[0014]
FIG. 5 is a diagram showing the timing of the voltage applied to the liquid crystal display panel 101 in the first embodiment.
[0015]
Based on the above drawings, the operation of the first embodiment will be described in detail. In FIG. 1, a display signal group 101 sent from a system device (not shown) such as a personal computer includes a drain driver control signal group which is a display signal and a timing signal for a liquid crystal driving circuit in a liquid crystal control circuit 103. A part of the display data 104 and the gate driver control signal group 105 is generated.
[0016]
Here, the drain driver control signal group 104 includes a data synchronization signal synchronized with display data, a drain output signal for determining the output timing to the drain line, and an alternating signal for determining the inversion timing of the output voltage shown in FIG. And the display data, and the gate driver control signal 105 includes a frame signal and a gate selection signal shown in FIG. Next, the operation of the additional control circuit will be described with reference to FIGS. A frame signal generated by the liquid crystal control circuit 103 and indicating that the first line of the liquid crystal panel is valid is divided by the frequency dividing circuit 201, thereby obtaining a signal that becomes a high level and a low level every frame period. At the same time, the counter 202 counts the drain output signal and outputs 2-bit count values Q1 and Q0. Since the counter 202 is reset by a frame signal, the output pattern in each frame is always constant. The frequency-divided signal of the frame signal generated in this way and the output Q1 of the counter 202 are calculated by the exclusive OR circuit 203 to generate an alternating signal. Therefore, the AC signal has a specification in which the high level and the low level change every two lines from the head of each frame, and the high level and the low level are switched every time the frame signal is input. At the same time, the data synchronization signal is counted by the counter 204 to generate a count value 205. The counter 204 is reset every time the drain output signal becomes high level, and performs the counting operation again. Q0 which is the lower bit of the counter 202 is input to the comparison circuits 206 to 208 as a selection signal. Therefore, the comparison circuits 206 and 208 perform the comparison operation only when Q0 is at the high level, and the comparison circuits 207 and 209 perform the comparison operation only when Q0 is at the low level. Here, each of the comparison circuits 207 to 209 has a comparison value inside, and generates a high level signal if the count value is equal to the internal comparison circuit. The internal comparison value is set for each comparison circuit, and is different depending on each liquid crystal panel and the driving frequency. Here, the output signals from the comparison circuits 206 and 207 pass through the NOR circuit 210 to generate a gate selection signal, and the output signals from the comparison circuits 208 and 209 pass through the OR circuit 211 to turn on the gradation voltage selection signal. 108 is generated.
[0017]
Next, the operation of the gradation voltage control circuit will be described with reference to FIG. As shown in FIG. 3, the gradation voltage generation circuit 113 divides the voltage values of VEE and VSS generated by the power supply circuit 110 by the voltage dividing circuits 301-0 to 301-11, thereby Generate a voltage value. Here, each voltage level satisfies V0 <V1 <... <V4 <Vcen <V5 <. Each voltage generated in this way is input to the analog switches 302-0 to 302-9. To each analog switch, a voltage value of Vi (i = 0, 1,..., 9) is applied to one side, a voltage value of Vcen is applied to the other side, and a gradation voltage control signal 108 as a switching signal is applied. Vcen is output when the level is high, and Vi is output when the level is low. This voltage is V′i. The above V′i is subjected to impedance conversion by the corresponding voltage follower circuits 303-0 to 303-9, and high frequency noise is removed by the capacitors 304-0 to 304-9. The voltage follower circuits 303-0 to 303-9 and the capacitors 304-0 to 304-9 are not necessarily required depending on the circuit configuration including the drain driver 115. Therefore, the gradation voltage output from the gradation voltage generation circuit 113 is not necessary. V′i may be regarded as outputting Vcen when the gradation voltage control signal 108 is at high level, and Vi when it is at low level.
[0018]
The liquid crystal driving voltage in the above configuration will be described with reference to FIG. As shown in FIG. 5, the gradation reference voltages V′9 to V′0 have values of Vcen when the gradation voltage control signal is at a high level and take values of V9 to V0 during a period of a low level. Therefore, the voltage output from the drain driver 115 also temporarily changes to the Vcen level every time the drain output signal is input regardless of the AC cycle. The period during which the Vcen level is reached is determined by the comparison circuits 208 and 209. Therefore, in the drain voltage output period corresponding to the line that is exchanged compared to the previous line, the period for outputting the voltage Vcen is TC1, and in the drain voltage output period corresponding to the line that is not exchanged, the period for outputting the voltage Vcen is TC2. In this case, the change width of the drain voltage of the AC line is larger than the change width of the non-AC drain voltage, so by setting “TC1 <TC2”, the change width is canceled and the TFT is applied. Such a voltage value can be made constant. Furthermore, when the period for applying the gate-on voltage to the line that is exchanged compared to the previous line is TG1, and the period for applying the gate-on voltage to the line that is not exchanged is TG2, the period during which the gate-on voltage is applied is the gate selection signal. From the falling edge to the next falling period, the timing width of TG1 and TG2 can be changed by changing the comparison value of the comparison circuits 207 and 208, and by setting so that TG1> TG2. Furthermore, the voltage value applied to the TFT can be made constant.
[0019]
Next, as a second embodiment, a drain driver having a discharge function for once setting the drain voltage to the Vcen level will be described with reference to FIGS.
[0020]
FIG. 6 is a diagram showing the configuration of the drain driver in this embodiment, in which 601 is a discharge signal generation circuit, 602 is a discharge signal, 603 is a gradation voltage discharge circuit, and 604 is a liquid crystal drive voltage.
[0021]
FIG. 7 is a diagram showing the configuration of the discharge signal generation circuit, in which 701 is a latch circuit, 702 is an alternating signal latched by the latch circuit 701, 703 is an exclusive OR circuit, 704 is a latch circuit, and 705 is a selection signal. It is. 706 is a counter circuit having a reset operation, 707 is a count value obtained by counting the data synchronization signal by the counter circuit 706, and 708 is an input signal and a set value held therein when the selection signal is at a high level. A comparison circuit that compares and outputs a high level if the comparison results are the same, and 710 is an output signal thereof. Reference numeral 709 denotes a comparison circuit that compares the input signal with the set value held therein when the selection signal is at a low level, and outputs a high level if the comparison result is the same value. Reference numeral 711 denotes the output signal. Reference numeral 712 denotes a NOR circuit.
[0022]
FIG. 8 is a diagram showing the configuration of the gradation voltage discharge circuit, in which 801 and 802 are voltage followers, 803 and 804 are resistors, and 805-0 to 805-9 are analog switches.
[0023]
FIG. 9 is a timing chart showing the operation of the drain driver input / output signal and discharge signal generation circuit in this embodiment.
[0024]
The operation of the present embodiment will be described based on the above drawings. In FIG. 6, when the input selection signal becomes valid, the latch address generation circuit counts the data synchronization signal and generates the latch address. When all the latch addresses become valid, the latch address generation circuit generates the output selection signal and connects to the next stage. The operation of the drain driver is valid. The generated latch address is input to the latch circuit (1), and display data is sequentially latched. The display data latched in this way is latched based on the drain output signal in the latch circuit (2), so that the display data is transferred to the liquid crystal driving circuit at a time. Based on the display data transferred as described above and the alternating signal latched by the drain output signal, the liquid crystal driving circuit generates a drain output voltage corresponding to the polarity based on the display data and the alternating signal, and displays the liquid crystal display. Outputs to the panel drain line. The operation up to the above is not significantly different from the above-mentioned JP-A-2000-305534.
[0025]
Next, the operation of the discharge signal generation circuit 601 will be described with reference to FIGS. The AC signal input from the outside is latched in the latch circuit 701 based on the drain output signal, and an AC signal 702 is generated. The latched AC signal 702 and the input AC signal are subjected to an exclusive OR operation in an exclusive OR circuit 703. This signal is latched by the latch circuit 704 to generate a selection signal 705.
[0026]
Here, as shown in FIG. 6, since the AC signal is once latched by the drain output signal and then input to the liquid crystal driving circuit, the drain output during the period when the output of the exclusive OR circuit 703 becomes high level. The drain output is converted into an alternating current at the rising edge of the signal, and conversely, the alternating current is not applied at the rising edge of the drain output signal in the low level period. That is, the drain output voltage during the period in which the selection signal 705 is at the high level is Compared to the line, AC is performed, and AC is not performed in the low level period.
[0027]
The counter 706 performs a reset operation at the rising edge of the drain output signal, counts the data synchronization signal, and generates a count value 707. When the selection signal 705 is at a high level, that is, during a period in which a signal synchronized with the rising edge of the drain output signal for which alternating current is performed is input, the comparison value in the comparison circuit 708 is compared with the count value 707. Outputs a signal 710 having a high level, and when the selection signal 705 is at a low level, the set value held in the comparison circuit 709 is compared with the count value 707. Is output. The above signals 710 and 711 are logically ORed by an OR circuit 712 to generate a discharge signal 603.
[0028]
Next, the operation of the gradation voltage discharge circuit 603 will be described with reference to FIG. To the gradation voltage discharge circuit 603, the discharge signal 602 generated by the discharge signal generation circuit 601 and the gradation reference voltages V0 to V9 are input from the outside. Here, each voltage value is V0 <V1 <... <V8 <V9, V0 to V4 are negative voltage levels, and V5 to V9 are positive voltage levels.
[0029]
Among the gradation reference voltages, V4 and V5 having a low differential voltage between the positive polarity voltage and the negative polarity voltage are input to the voltage followers 801 and 802, respectively, and then divided by the resistors 803 and 804 to obtain a voltage value Vcen. The analog switches 805-0 to 805-9 perform switching between the generated Vcen and the gradation reference voltages V0 to V9 based on the discharge signal 603.
[0030]
As a result of the above, as shown in FIG. 9, the output voltage from the drain driver has a change in polarity compared to the case where the drain voltage is applied to a row having a change in polarity compared to the previous line and a case where the polarity changes compared to the previous line. When a drain voltage is applied to a non-row, the period of transition to the Vcen level can be changed, so that the voltage applied to each pixel electrode can be equalized based on the same display data. This makes it possible to provide a good liquid crystal display device with no display unevenness.
[0031]
【The invention's effect】
According to the present invention, even in N-line dot inversion driving, the voltage level applied to the drain line can be made the same voltage level regardless of the presence or absence of polarity inversion, thereby generating bright lines generated for each line. As a result, it is possible to obtain an excellent display quality with little display unevenness.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a liquid crystal display device according to a first embodiment.
FIG. 2 is a diagram showing a configuration of a control circuit 106;
3 is a diagram showing a configuration of a power supply circuit 110. FIG.
FIG. 4 is a diagram illustrating operation timing of a control circuit.
FIG. 5 is a view showing the timing of a voltage applied to the liquid crystal display panel 101. FIG.
FIG. 6 is a diagram showing a configuration of a drain driver.
FIG. 7 is a diagram showing a configuration of a discharge signal generation circuit.
FIG. 8 is a diagram showing a configuration of a gradation voltage discharge circuit.
FIG. 9 is a timing chart showing the operation of the drain driver input / output signal and discharge signal generation circuit.
FIG. 10 is a diagram showing a 1-line dot inversion method and an N-line dot inversion method.
FIG. 11 is a diagram illustrating an example of a cancel pattern.
FIG. 12 is a diagram showing drain line voltage and gate line voltage in a 2-line dot inversion method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 101 ... Liquid crystal display panel, 102 ... Display signal group, 103 ... Liquid crystal control circuit A, 104 ... Drain driver control signal group and display data, 105 ... Gate driver control signal group, 106 ... Liquid crystal control circuit B, 107 ... Gate selection signal , 108 ... gradation voltage control signal, 109 ... input voltage, 110 ... power supply circuit, 111 ... drain driver input voltage, 112 ... gate driver input voltage, 113 ... gradation voltage generation circuit, 114 ... 114 is a gradation voltage, 115 DESCRIPTION OF SYMBOLS ... Drain driver, 116 ... Gate driver, 201 ... Frequency dividing circuit, 202 ... Counter, 203 ... Exclusive OR circuit, 204 ... Counter circuit, 205 ... Count value, 206 ... Comparison circuit, 207 ... Comparison circuit, 208 ... Comparison Circuit 209 ... comparison circuit 210 ... NOR circuit 211 ... OR circuit 301 0-301-11 ... voltage divider circuit, 302-0 to 302-9 ... analog switch, 303-0 to 303-9 ... voltage follower circuit, 304-0 to 304-9 ... capacitor, 601 ... discharge signal generation circuit, 602 ... Discharge signal, 603 ... Grayscale voltage discharge circuit, 604 ... Liquid crystal drive voltage, 701 ... Latch circuit, 702 ... AC signal latched by the latch circuit 701, 703 ... Exclusive OR circuit, 704 ... Latch circuit, 705... Selection signal, 706... Counter circuit, 707... Count value, 708... Comparison circuit, 709... Output signal from comparison circuit 708 710... Comparison circuit, 711 ... Output signal from comparison circuit 710, 712. Voltage follower, 802... Voltage follower, 803... Resistance, 804. -1～805-9 ... analog switch.

Claims (4)

A liquid crystal display panel having pixel electrodes arranged in a matrix and a common counter electrode for each pixel electrode, and a liquid crystal driver for outputting a liquid crystal display voltage corresponding to display data in the column direction of each pixel electrode And a scanning circuit that performs scanning by applying a selection voltage to the row direction of each pixel electrode, and each pixel electrode transmits transmitted light according to a potential difference between the liquid crystal display voltage and a voltage applied to the counter electrode. Alternatively, in a liquid crystal display device that performs gradation display by changing the amount of reflected light,
Change the polarity of the liquid crystal applied voltage with respect to the counter electrode every time a plurality of rows are scanned, and apply a reference voltage every time a row is scanned, then apply a liquid crystal applied voltage according to the display data,
Period for applying said reference to become voltage when scanning the unchanged rows of the polarity, rather long than the period for applying the reference become voltage when scanning the altered line of the polar,
The scanning period of the row having the changed polarity is longer than the scanning time of the row having the changed polarity,
The period from the start of application of the selection voltage of the row having the changed polarity to the start of application of the reference voltage is from the start of application of the selection voltage of the row having no change in polarity. than the period before the start of application in relation to the standard voltage the liquid crystal display device comprising a length Ikoto. The liquid crystal display device according to claim 1.
The pixel electrode of the row with the changed polarity is located in the first row of the pixel electrodes of the plurality of rows, and the pixel electrode of the row with the polarity not changed is after the second row of the pixel electrodes of the plurality of rows. A liquid crystal display device characterized by being positioned. The liquid crystal display device according to claim 1 or 2,
The reference voltage value is an intermediate potential between a positive voltage and a negative voltage. The liquid crystal display device according to claim 1.
The reference voltage is a positive voltage close to a negative voltage among a plurality of positive voltages prepared in the liquid crystal driver, and a positive voltage among a plurality of negative voltages prepared in the liquid crystal driver. The liquid crystal display device is produced based on a negative polarity voltage close to.

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