JP2002287701A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device having little display unevenness in N-line dot inversion driving. SOLUTION: Firstly, even when a drain voltage is applied to selection lines unchanged in polarity, the voltage is once shifted to about an intermediate level between positive polarity and negative polarity before pre-specified drain voltage according to display data is applied thereto. Further, a selection line changed in polarity and a selection line unchanged in polarity are made to differ in a time width of a gate-on period from each other. Thus, a source electrode value is made constant irrespective of the presence or absence of the polarity change, to eliminate a display unevenness and a bright line.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device and a driving circuit thereof, and more particularly to a driving circuit for providing a liquid crystal display device having excellent display quality.

[0002]

2. Description of the Related Art In a liquid crystal display device, each pixel arranged in a matrix is provided with an active element such as a TFT (Thin Film Transistor), and a gate electrode of each active element is connected to a common gate line in a row direction. The drain electrode is a driving method of an active matrix liquid crystal panel connected to a common drain line in a column direction. A voltage applied to a common electrode (hereinafter, a common electrode) of each pixel is fixed.
There is a method of realizing gradation display by changing the voltage applied to the source electrode. In this driving method, for each pixel,
A source voltage having a different polarity with respect to the pixel adjacent in the gate direction (the polarity here indicates the polarity of the pixel electrode voltage with respect to the common electrode voltage) is applied, and a pixel adjacent in the drain line direction is also applied. There is a driving method for applying source voltages having different polarities, and this driving method is hereinafter referred to as one-line dot inversion driving. Similarly, there is a driving method in which, for each pixel, a source voltage having a different polarity is applied to a pixel adjacent in the gate direction, and a source voltage having a different polarity is applied every N pixels in the drain line direction. Hereinafter, this driving method is referred to as N-line dot inversion driving. FIG. 10 shows the polarity of the pixel electrode voltage when N = 2 in the one-line dot inversion driving and the N-line dot inversion driving described above.

As a method for improving image quality in one-line dot inversion driving, there is, for example, JP-A-2000-305534.

[0004]

In the above-described line dot inversion driving, in a specific display pattern as shown in FIG. 11, the drain voltage applied per frame is biased to the positive side or the negative side. There is a problem to do. Hereinafter, such a display pattern is referred to as a cancel pattern. As a method of preventing this, the gap can be eliminated by performing an alternating current for every even-numbered line, such as two-line dot inversion, and the flicker can be greatly reduced.

However, in the case of two-line AC, FIG.
As shown in FIG. 2, when the same source voltage is to be written to the pixel electrode, the voltage value to be written in the line whose polarity has changed and the line which does not change compared to the previous line due to the resistance component and the capacitance component of the drain line However, even when a solid display is performed, uneven display or horizontal stripes may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal display device having less display unevenness in N-line dot inversion driving.

[0007]

In order to solve the above-mentioned object, in the liquid crystal display device of the present invention, the period during which the TFT of each pixel is on is changed in accordance with the AC cycle. Specifically, the period during which the TFT is on is relatively long in a line where AC is performed, and the period is relatively short in a line where AC is not performed.

A reference voltage (approximately an intermediate voltage between positive and negative polarities) is applied to the drain line of a line whose polarity does not change before applying a drain voltage.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment will be described below with reference to FIGS. The first embodiment has a method in which a gradation voltage generation circuit is provided outside (for example, a liquid crystal controller or the like). Here, an example in which two lines are used for alternating current is shown.

FIG. 1 is a diagram showing the configuration of a liquid crystal display device according to a first embodiment, wherein reference numeral 101 denotes a liquid crystal display panel,
Reference numeral 2 denotes a display signal group input from an external system (not shown).
Liquid crystal control circuits A and 10 for converting signals suitable for
4 is a drain driver control signal group and display data, 10
5 is a gate driver control signal group, 106 is a liquid crystal control circuit B, 107 is a gate selection signal, 108 is a gradation voltage control signal, 109 is an external input voltage, 110 is a power supply circuit, 111 is a drain driver input voltage, 112 Is a gate driver input voltage, 113 is a gradation voltage generation circuit,
114 is a gradation voltage, 115 is a drain driver, 116
Is a gate driver.

FIG. 2 shows the structure of the liquid crystal control circuit B106, wherein 201 is a frequency dividing circuit, 202 is a 2-bit counter circuit, 203 is an exclusive OR circuit, 20
4 is a counter circuit, 205 is a count value counted by the counter 204, 206 and 208 are comparison circuits that output a high level during a period when the selection signal is at a high level and a storage value stored therein matches an input signal, Reference numerals 207 and 209 denote comparison circuits which output a low level during a period when the selection signal is at a high level and a storage value stored therein matches an input signal, and reference numeral 210 denotes a NOR circuit.
A circuit 211 is an OR circuit.

FIG. 3 is a diagram showing the configuration of the power supply circuit 110. VEE and VSS are voltage values of a reference gray scale voltage input from the power supply circuit 110, and 301-0 to 301-11 are voltage dividers formed by resistors. Circuits, V0 to V9 are voltage dividing circuits 30
2c is a gradation voltage generated by 0 to 301-11, Vcen is a center voltage, and 302-0 to 302-9.
Is an analog switch switched by the grayscale voltage control signal 106, 303-0 to 303-9 are voltage follower circuits, and 304-0 to 304-9 are capacitors.

FIG. 4 is a diagram showing the operation timing of the additional control circuit in the first embodiment.

FIG. 5 is a diagram showing the timing of the voltage applied to the liquid crystal display panel 101 in the first embodiment.

The operation of the first embodiment will be described in detail with reference to the above drawings. In FIG. 1, a display signal group 101 sent from a system device (not shown) such as a personal computer includes a drain driver control signal group, which is a display signal and a timing signal for a liquid crystal driving circuit, and a liquid crystal control circuit 103. The display data 104 and a part of the gate driver control signal group 105 are generated.

Here, the drain driver control signal group 10
4 includes a data synchronization signal synchronized with the display data, a drain output signal that determines the output timing to the drain line, an AC signal that determines the inversion timing of the output voltage, and display data shown in FIG. As the driver control signal 105, the frame signal shown in FIG.
It has a gate selection signal. Next, the operation of the additional control circuit will be described with reference to FIGS. The frame signal generated by the liquid crystal control circuit 103 and indicating that the first line of the liquid crystal panel is valid is frequency-divided by the frequency dividing circuit 201, so that a signal that goes high and low every frame period is obtained. At the same time, the counter 202 counts the drain output signal and outputs 2-bit count values Q1 and Q0. This counter 202
Is reset by the frame signal, the output pattern in each frame is always constant. The frequency-divided signal of the frame signal thus generated and the output Q1 of the counter 202 are operated by an exclusive OR circuit 203 to generate an AC signal. Therefore, the alternating signal has a specification in which the high level and the low level change every two lines from the beginning of each frame, and the high level and the low level are switched every time a frame signal is input. At the same time, the data synchronization signal is counted by the counter 204 and the count value is 20.
5 is generated. The counter 204 is reset every time the drain output signal goes high, and performs the counting operation again. Q0 which is the lower bit of the counter 202 is input to the comparison circuits 206 to 208 as a selection signal. Therefore, the comparison circuits 206 and 208 perform the comparison operation only when Q0 is at the high level, and conversely, the comparison circuit 20
7 and 209 perform the comparison operation only when Q0 is at the low level. Here, each of the comparison circuits 207 to 209 has a comparison value inside, and generates a high level signal if the count value and the internal comparison circuit are equal. The internal comparison value is set for each comparison circuit, and differs depending on each liquid crystal panel and the driving frequency. Here, the comparison circuit 2
Output signals from 06 and 207 pass through a NOR circuit 210 to generate a gate selection signal, and output signals from comparison circuits 208 and 209 pass through an OR circuit 211 to generate a gradation voltage selection signal 108.

Next, the operation of the gradation voltage control circuit will be described with reference to FIG. As shown in FIG.
Are VEE, VSS generated by the power supply circuit 110.
Is divided by the voltage dividing circuits 301-0 to 301-11 to generate voltage values V0 to V9 and Vcen. Here, each voltage level is V0 <V1 <... <V4 <V
.. <V9. Each voltage generated in this manner is connected to the analog switches 302-0 to 302-0.
Input to 302-9. A voltage value of Vi (i = 0, 1,..., 9) is applied to one of the analog switches, a voltage value of Vcen is applied to one of the analog switches, and a gradation voltage control signal 108 as a switching signal is applied to each analog switch. Vc at high level
and outputs Vi when the signal is at a low level.
This voltage is defined as V′i. The above V'i is a voltage follower circuit 303-0 to 303-9 corresponding to each.
, And high-frequency noise is removed by the capacitors 304-0 to 304-9. The voltage follower circuits 303-0 to 303
−9 and the capacitors 304-0 to 304-9 are not necessarily required depending on the configuration of the circuit including the drain driver 115. Therefore, the gray scale voltage V′i output from the gray scale voltage generation circuit 113 is a gray scale voltage control signal. It may be considered that Vcen is output when 108 is at a high level, and Vi is output when 108 is at a low level.

The liquid crystal driving voltage in the above configuration will be described with reference to FIG. As shown in FIG. 5, the gray scale reference voltages V'9 to V'0 take the value of Vcen when the gray scale voltage control signal is at a high level, and take the values of V9 to V0 during the low level. Therefore, the drain driver 1
The voltage output from 15 also transitions to the Vcen level once regardless of the AC cycle every time the drain output signal is input. The period during which the voltage is at the Vcen level is determined by the comparison circuits 208 and 209. Therefore, in the drain voltage output period corresponding to the line to be exchanged with the previous line, the period during which the voltage Vcen is output is TC1, and in the drain voltage output period corresponding to the line not to be exchanged, the period during which the voltage Vcen is output is TC2. In this case, the change width of the drain voltage of the line to be AC is larger than the change width of the drain voltage not to be AC. Therefore, by setting “TC1 <TC2”, the change width acts in a direction in which the change is canceled, and the TFT is operated. Such a voltage value can be kept constant. Furthermore, if the period during which the gate-on voltage is applied to the line that is to be AC compared to the previous line is TG1 and the period during which the gate-on voltage is applied to the line that is not AC is TG2, the period during which the gate-on voltage is applied is the gate selection signal. From the fall to the next fall period, the timing width of TG1 and TG2 can be changed by changing the comparison values of the comparison circuits 207 and 208, and by setting so that TG1> TG2. Further, the voltage value applied to the TFT can be made constant.

Next, as a second embodiment, a drain driver having a discharge function for temporarily setting the drain voltage to the Vcen level, in which the AC cycle is 4 lines, will be described with reference to FIGS.

FIG. 6 is a diagram showing the configuration of the drain driver in this embodiment. Reference numeral 601 denotes a discharge signal generation circuit, 602 denotes a discharge signal, 603 denotes a grayscale voltage discharge circuit, and 604 denotes a liquid crystal drive voltage.

FIG. 7 is a diagram showing the configuration of a discharge signal generation circuit, in which 701 is a latch circuit, 702 is an alternating signal latched by the latch circuit 701, 703 is an exclusive OR circuit, 704 is a latch circuit, and 705 Is a selection signal. 706, a counter circuit having a reset operation;
07 is a count value obtained by counting the data synchronization signal by the counter circuit 706, and 708 compares the input signal when the selection signal is at a high level with the set value held therein, and the comparison result is the same. If there is, it is a comparison circuit that outputs a high level, and 710 is its output signal. Reference numeral 709 denotes a comparison circuit which compares the input signal when the selection signal is at a low level with a set value held therein, and outputs a high level if the comparison result is the same, and 711 denotes an output signal of the comparison circuit. 712 is a NOR circuit.

FIG. 8 is a diagram showing the configuration of the gray scale voltage discharge circuit. Reference numerals 801 and 802 denote voltage followers, 803 and 804 denote resistors, and 805-0 to 805-9 denote analog switches.

FIG. 9 is a timing chart showing the operation of the input / output signals of the drain driver and the discharge signal generation circuit in this embodiment.

The operation of the present embodiment will be described with reference to the above drawings. In FIG. 6, when the input selection signal becomes valid, the latch address generation circuit counts the data synchronization signal to generate a latch address, and when all the latch addresses become valid, generates an output selection signal and connects to the next stage. The operation of the drain driver is valid. The generated latch address is input to the latch circuit (1), and the display data is sequentially latched. The display data thus latched is latched in the latch circuit (2) based on the drain output signal, so that the display data is transferred to the liquid crystal drive circuit at one time. Based on the display data transferred as described above and the alternating signal also latched by the drain output signal, the liquid crystal driving circuit generates a drain output voltage corresponding to the polarity based on the display data and the alternating signal, and Output to the drain line of the panel. The operation up to the above is described in the above-mentioned JP-A-2000-305.
It does not differ greatly from 534 mag.

Next, the operation of the discharge signal generation circuit 601 will be described with reference to FIGS. An alternating signal input from the outside is latched in a latch circuit 701 based on a drain output signal, and an alternating signal 702 is generated. An exclusive OR circuit 703 performs an exclusive OR operation on the latched AC signal 702 and the input AC signal. This signal is latched by a latch circuit 704 to generate a selection signal 705.

Here, as shown in FIG. 6, since the alternating signal is once latched by the drain output signal and then inputted to the liquid crystal driving circuit, the period during which the output of the exclusive OR circuit 703 becomes high level , The alternating of the drain output is performed at the rising of the drain output signal, and conversely, the alternating of the drain output signal is not performed at the rising of the drain output signal during the period of the low level.
During the high level period, the drain output voltage is converted into an alternating current as compared with the previous line, and during the low level period, the alternating output is not performed.

The counter 706 performs a reset operation at the rising edge of the drain output signal, counts the data synchronization signal, and generates a count value 707. In a period in which the selection signal 705 is at a high level, that is, in a period in which a signal synchronized with the rise of the drain output signal to be converted is input, the comparison value of the comparison circuit 708 is compared with the count value 707. Outputs a high-level signal 710. When the selection signal 705 is at a low level, the comparison circuit 709 compares the internal set value with the count value 707. If the result matches, the high-level signal 711 is output. Is output. The above-described signals 710 and 711 are subjected to a logical sum operation in an OR circuit 712 to generate a discharge signal 603.

Next, the operation of the gradation voltage discharge circuit 603 will be described with reference to FIG. For the grayscale voltage discharge circuit 603, the discharge signal 6 generated by the discharge signal generation circuit 601 is output.
02 and the gray scale reference voltages V0 to V9 are input from outside.
Here, each voltage value is V0 <V1 <... <V8 <V9, V0 to V4 are negative voltage levels, and V5 to V9 are positive voltage levels.

Of the gray scale reference voltages, V4 and V5 having a low difference voltage between the positive polarity voltage and the negative polarity voltage are input to the voltage followers 801 and 802, respectively, and then the resistances 803 and 804 are set.
To obtain a voltage value Vcen. The analog switches 805-0 to 805-9 switch between the thus generated Vcen and the gradation reference voltages V0 to V9 based on the discharge signal 603.

As a result, as shown in FIG. 9, the output voltage from the drain driver is different between the case where the drain voltage is applied to a row having a change in polarity as compared with the previous line and the case where the polarity is compared with the previous line. In the case where a drain voltage is applied to a row having no change, the period during which the voltage shifts to the Vcen level can be changed, so that, based on the same display data, the voltage applied to each pixel electrode is also made equal. This makes it possible to provide a good liquid crystal display device without display unevenness.

[0031]

According to the present invention, even in the N-line dot inversion driving, the voltage level applied to the drain line can be set to the same voltage level regardless of the presence or absence of the polarity inversion. It is possible to suppress the generation of the generated bright line, and thus, it is possible to obtain an effect of obtaining good display quality with less display unevenness.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a liquid crystal display device according to a first embodiment.

FIG. 2 is a diagram showing a configuration of a control circuit 106.

FIG. 3 illustrates a configuration of a power supply circuit 110.

FIG. 4 is a diagram showing operation timings of a control circuit.

FIG. 5 is a diagram showing timing of a voltage applied to the liquid crystal display panel 101.

FIG. 6 illustrates a configuration of a drain driver.

FIG. 7 is a diagram showing a configuration of a discharge signal generation circuit.

FIG. 8 is a diagram illustrating a configuration of a gradation voltage discharge circuit.

FIG. 9 is a timing chart showing an operation of an input / output signal of a drain driver and a discharge signal generation circuit.

FIG. 10 is a diagram showing a one-line dot inversion method and an N-line dot inversion method.

FIG. 11 is a diagram showing an example of a cancel pattern.

FIG. 12 is a diagram showing a drain line voltage and a gate line voltage in a two-line dot inversion method.

[Explanation of symbols]

101: liquid crystal display panel, 102: display signal group, 103
... Liquid crystal control circuits A and 104. Drain driver control signal group and display data. 105. Gate driver control signal group. 106. Liquid crystal control circuits B and 107.
Gate selection signal, 108 ... Grayscale voltage control signal, 109 ...
Input voltage, 110: power supply circuit, 111: drain driver input voltage, 112: gate driver input voltage, 113
... A gradation voltage generation circuit, 114.
5 ... Drain driver, 116 ... Gate driver, 20
1 ... frequency divider circuit, 202 ... counter, 203 ... exclusive OR circuit, 204 ... counter circuit, 205 ... count value,
206: comparison circuit, 207: comparison circuit, 208: comparison circuit, 209: comparison circuit, 210: NOR circuit, 211 ...
OR circuit, 301-0 to 301-11 ... voltage dividing circuit, 30
2-0 to 302-9: Analog switch, 303-0
303-9: Voltage follower circuit, 304-0 to 3
04-9: capacitor, 601: discharge signal generation circuit, 602: discharge signal, 603: gradation voltage discharge circuit, 604: liquid crystal drive voltage, 701
.., A latch circuit, 702, an alternating signal latched by the latch circuit 701, 703, an exclusive OR circuit, 704, a latch circuit, 705, a selection signal, 706, a counter circuit,
707: count value, 708: comparison circuit, 709: output signal of the comparison circuit 708, 710: comparison circuit, 711: output signal of the comparison circuit 710, 712: NOR circuit, 801
... Voltage follower, 802 ... Voltage follower,
803: resistance, 804: resistance, 805-1 to 805-9
... Analog switches.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 3/20 642 G09G 3/20 642A (72) Inventor Masaaki Kitajima 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. 2H093 NA31 NA41 NA51 NC34 ND06 ND60 5C006 AA16 AC27 AF42 AF45 BB16 BC03 BC12 BF04 BF06 BF14 BF22 BF26 FA22 5C080 AA10 BB05 DD05 EE29 FF11 JJ01 JJ01 JJ02 JJ04

Claims (6)

[Claims] 1. A liquid crystal display panel having pixel electrodes arranged in a matrix and a common electrode common to each pixel electrode, and a liquid crystal display voltage corresponding to display data in a column direction of each pixel electrode. An LCD driver that outputs
A scanning circuit that performs scanning by applying a selection voltage to a row direction of each pixel electrode, wherein each pixel electrode transmits or reflects light according to a potential difference between the liquid crystal display voltage and a voltage applied to a counter electrode. In a liquid crystal display device that performs gradation display by changing the amount of light, the polarity of the liquid crystal display voltage with respect to the counter electrode is changed for each of a plurality of rows of pixel electrodes. A liquid crystal display device characterized in that the scanning time is longer than that of the pixel electrodes in a row whose polarity does not change. 2. The liquid crystal display device according to claim 1, wherein the pixel electrodes of the row whose polarity has changed are located on the first row of the pixel electrodes of the plurality of rows, and the pixel electrodes of the row whose polarity does not change are A liquid crystal display device located on the second and subsequent rows of the plurality of rows of pixel electrodes. 3. A liquid crystal display panel having pixel electrodes arranged in a matrix and a common electrode common to each pixel electrode, and a liquid crystal display voltage corresponding to display data in a column direction of each pixel electrode. An LCD driver that outputs
A scanning circuit that performs scanning by applying a selection voltage to a row direction of each pixel electrode, wherein each pixel electrode transmits or reflects light according to a potential difference between the liquid crystal display voltage and a voltage applied to a counter electrode. In a liquid crystal display device that performs gradation display by changing the amount of light, the polarity of the liquid crystal applied voltage with respect to the counter electrode is changed each time scanning is performed for a plurality of rows, and when a row whose polarity does not change is scanned, a reference is used. A liquid crystal display device comprising: applying a liquid crystal application voltage according to display data after applying a predetermined voltage. 4. The liquid crystal display device according to claim 3, wherein the reference voltage value is substantially an intermediate potential between a positive voltage and a negative voltage. 5. A liquid crystal display panel having pixel electrodes arranged in a matrix and a common electrode common to each pixel electrode, and a liquid crystal display voltage corresponding to display data in a column direction of each pixel electrode. An LCD driver that outputs
A scanning circuit that performs scanning by applying a selection voltage to a row direction of each pixel electrode, wherein each pixel electrode transmits or reflects light according to a potential difference between the liquid crystal display voltage and a voltage applied to a counter electrode. In a liquid crystal display device that performs gradation display by changing the amount of light, the liquid crystal driver determines the polarity of the liquid crystal display voltage based on the inversion signal, and determines whether the polarity of the liquid crystal display voltage changes, A liquid crystal display device characterized by applying a voltage value that does not correspond to the display data of the row, and then outputs a liquid crystal display voltage according to the display data, at least when the voltage does not change. 6. A liquid crystal display panel having pixel electrodes arranged in a matrix and a common electrode common to each pixel electrode, and a liquid crystal display voltage corresponding to display data in a column direction of each pixel electrode. An LCD driver that outputs
A scanning circuit that performs scanning by applying a selection voltage to the row direction of each pixel electrode, and each pixel electrode transmits or reflects light according to a potential difference between the liquid crystal display voltage and a voltage applied to a counter electrode. In a liquid crystal display device that performs gradation display by changing the amount of light, the liquid crystal driver determines the polarity of the liquid crystal display voltage based on the inversion signal, and determines whether the polarity of the liquid crystal display voltage changes, At least, when there is no change, output a negative voltage if the row is positive, output a positive voltage if the row is negative, and then output a liquid crystal display voltage according to the display data. A liquid crystal display device characterized by the above-mentioned.