JP3984786B2 - 異なる待ち時間を伴う命令のスケジューリング - Google Patents
異なる待ち時間を伴う命令のスケジューリング Download PDFInfo
- Publication number
- JP3984786B2 JP3984786B2 JP2000565456A JP2000565456A JP3984786B2 JP 3984786 B2 JP3984786 B2 JP 3984786B2 JP 2000565456 A JP2000565456 A JP 2000565456A JP 2000565456 A JP2000565456 A JP 2000565456A JP 3984786 B2 JP3984786 B2 JP 3984786B2
- Authority
- JP
- Japan
- Prior art keywords
- register
- latency
- issue group
- expected
- instruction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
- G06F9/3863—Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Advance Control (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US09/132,043 | 1998-08-11 | ||
| US09/132,043 US6035389A (en) | 1998-08-11 | 1998-08-11 | Scheduling instructions with different latencies |
| PCT/US1999/017948 WO2000010076A1 (en) | 1998-08-11 | 1999-08-10 | Scheduling instructions with different latencies |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002522841A JP2002522841A (ja) | 2002-07-23 |
| JP2002522841A5 JP2002522841A5 (https=) | 2006-09-14 |
| JP3984786B2 true JP3984786B2 (ja) | 2007-10-03 |
Family
ID=22452183
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000565456A Expired - Fee Related JP3984786B2 (ja) | 1998-08-11 | 1999-08-10 | 異なる待ち時間を伴う命令のスケジューリング |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US6035389A (https=) |
| JP (1) | JP3984786B2 (https=) |
| CN (1) | CN1138205C (https=) |
| AU (1) | AU5550699A (https=) |
| HK (1) | HK1041947B (https=) |
| WO (1) | WO2000010076A1 (https=) |
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| JP3881763B2 (ja) * | 1998-02-09 | 2007-02-14 | 株式会社ルネサステクノロジ | データ処理装置 |
| US6304953B1 (en) * | 1998-07-31 | 2001-10-16 | Intel Corporation | Computer processor with instruction-specific schedulers |
| US6304955B1 (en) * | 1998-12-30 | 2001-10-16 | Intel Corporation | Method and apparatus for performing latency based hazard detection |
| US6219781B1 (en) * | 1998-12-30 | 2001-04-17 | Intel Corporation | Method and apparatus for performing register hazard detection |
| US6631452B1 (en) * | 2000-04-28 | 2003-10-07 | Idea Corporation | Register stack engine having speculative load/store modes |
| US7127422B1 (en) * | 2000-05-19 | 2006-10-24 | Etp Holdings, Inc. | Latency monitor |
| US20040064679A1 (en) * | 2002-09-30 | 2004-04-01 | Black Bryan P. | Hierarchical scheduling windows |
| US20040064678A1 (en) * | 2002-09-30 | 2004-04-01 | Black Bryan P. | Hierarchical scheduling windows |
| US7454747B2 (en) * | 2003-02-07 | 2008-11-18 | Sun Microsystems, Inc. | Determining maximum acceptable scheduling load latency using hierarchical search |
| US20040158694A1 (en) * | 2003-02-10 | 2004-08-12 | Tomazin Thomas J. | Method and apparatus for hazard detection and management in a pipelined digital processor |
| US7590063B2 (en) * | 2003-11-10 | 2009-09-15 | Honeywell International Inc. | Real-time estimation of event-driven traffic latency distributions when layered on static schedules |
| US7502912B2 (en) * | 2003-12-30 | 2009-03-10 | Intel Corporation | Method and apparatus for rescheduling operations in a processor |
| US20050147036A1 (en) * | 2003-12-30 | 2005-07-07 | Intel Corporation | Method and apparatus for enabling an adaptive replay loop in a processor |
| US20050216900A1 (en) * | 2004-03-29 | 2005-09-29 | Xiaohua Shi | Instruction scheduling |
| US7257700B2 (en) * | 2004-06-03 | 2007-08-14 | Sun Microsystems, Inc. | Avoiding register RAW hazards when returning from speculative execution |
| US7418625B2 (en) * | 2004-09-09 | 2008-08-26 | Broadcom Corporation | Deadlock detection and recovery logic for flow control based data path design |
| JPWO2006134693A1 (ja) * | 2005-06-15 | 2009-01-08 | 松下電器産業株式会社 | プロセッサ |
| US20160098279A1 (en) * | 2005-08-29 | 2016-04-07 | Searete Llc | Method and apparatus for segmented sequential storage |
| GB2447907B (en) * | 2007-03-26 | 2009-02-18 | Imagination Tech Ltd | Processing long-latency instructions in a pipelined processor |
| US7913067B2 (en) * | 2008-02-20 | 2011-03-22 | International Business Machines Corporation | Method and system for overlapping execution of instructions through non-uniform execution pipelines in an in-order processor |
| US20090271237A1 (en) * | 2008-04-28 | 2009-10-29 | Rail Insight, Llc | Optimizing Rail Shipments for Commodity Transactions |
| US8467623B2 (en) | 2010-03-26 | 2013-06-18 | Brain Corporation | Invariant pulse latency coding systems and methods systems and methods |
| US9122994B2 (en) | 2010-03-26 | 2015-09-01 | Brain Corporation | Apparatus and methods for temporally proximate object recognition |
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| US9152915B1 (en) | 2010-08-26 | 2015-10-06 | Brain Corporation | Apparatus and methods for encoding vector into pulse-code output |
| JP2012173755A (ja) * | 2011-02-17 | 2012-09-10 | Nec Computertechno Ltd | 情報処理装置及び情報処理方法 |
| US9047568B1 (en) | 2012-09-20 | 2015-06-02 | Brain Corporation | Apparatus and methods for encoding of sensory data using artificial spiking neurons |
| US9070039B2 (en) | 2013-02-01 | 2015-06-30 | Brian Corporation | Temporal winner takes all spiking neuron network sensory processing apparatus and methods |
| US9098811B2 (en) | 2012-06-04 | 2015-08-04 | Brain Corporation | Spiking neuron network apparatus and methods |
| TWI643063B (zh) * | 2012-03-06 | 2018-12-01 | 智邦科技股份有限公司 | Detection method |
| US9224090B2 (en) | 2012-05-07 | 2015-12-29 | Brain Corporation | Sensory input processing apparatus in a spiking neural network |
| US9129221B2 (en) | 2012-05-07 | 2015-09-08 | Brain Corporation | Spiking neural network feedback apparatus and methods |
| US9412041B1 (en) | 2012-06-29 | 2016-08-09 | Brain Corporation | Retinal apparatus and methods |
| US9311594B1 (en) | 2012-09-20 | 2016-04-12 | Brain Corporation | Spiking neuron network apparatus and methods for encoding of sensory data |
| US9218563B2 (en) | 2012-10-25 | 2015-12-22 | Brain Corporation | Spiking neuron sensory processing apparatus and methods for saliency detection |
| US9183493B2 (en) | 2012-10-25 | 2015-11-10 | Brain Corporation | Adaptive plasticity apparatus and methods for spiking neuron network |
| US9111226B2 (en) | 2012-10-25 | 2015-08-18 | Brain Corporation | Modulated plasticity apparatus and methods for spiking neuron network |
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| US9177245B2 (en) | 2013-02-08 | 2015-11-03 | Qualcomm Technologies Inc. | Spiking network apparatus and method with bimodal spike-timing dependent plasticity |
| US9009545B2 (en) * | 2013-06-14 | 2015-04-14 | International Business Machines Corporation | Pulsed-latch based razor with 1-cycle error recovery scheme |
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| US11210098B2 (en) * | 2013-07-15 | 2021-12-28 | Texas Instruments Incorporated | Variable latency instructions |
| US9552546B1 (en) | 2013-07-30 | 2017-01-24 | Brain Corporation | Apparatus and methods for efficacy balancing in a spiking neuron network |
| US9489623B1 (en) | 2013-10-15 | 2016-11-08 | Brain Corporation | Apparatus and methods for backward propagation of errors in a spiking neuron network |
| US9939253B2 (en) | 2014-05-22 | 2018-04-10 | Brain Corporation | Apparatus and methods for distance estimation using multiple image sensors |
| US9713982B2 (en) | 2014-05-22 | 2017-07-25 | Brain Corporation | Apparatus and methods for robotic operation using video imagery |
| US10194163B2 (en) | 2014-05-22 | 2019-01-29 | Brain Corporation | Apparatus and methods for real time estimation of differential motion in live video |
| US9848112B2 (en) | 2014-07-01 | 2017-12-19 | Brain Corporation | Optical detection apparatus and methods |
| US10057593B2 (en) | 2014-07-08 | 2018-08-21 | Brain Corporation | Apparatus and methods for distance estimation using stereo imagery |
| US10055850B2 (en) | 2014-09-19 | 2018-08-21 | Brain Corporation | Salient features tracking apparatus and methods using visual initialization |
| US9881349B1 (en) | 2014-10-24 | 2018-01-30 | Gopro, Inc. | Apparatus and methods for computerized object identification |
| US9563428B2 (en) * | 2015-03-26 | 2017-02-07 | International Business Machines Corporation | Schedulers with load-store queue awareness |
| US10197664B2 (en) | 2015-07-20 | 2019-02-05 | Brain Corporation | Apparatus and methods for detection of objects using broadband signals |
| TWI587218B (zh) * | 2016-09-10 | 2017-06-11 | 財團法人工業技術研究院 | 記憶體事務層級模型模擬方法及系統 |
| US10558460B2 (en) * | 2016-12-14 | 2020-02-11 | Qualcomm Incorporated | General purpose register allocation in streaming processor |
| CN108334326A (zh) * | 2018-02-06 | 2018-07-27 | 江苏华存电子科技有限公司 | 一种低延迟指令调度器的自动管理方法 |
| US11263013B2 (en) * | 2020-04-07 | 2022-03-01 | Andes Technology Corporation | Processor having read shifter and controlling method using the same |
| US11461103B2 (en) * | 2020-10-23 | 2022-10-04 | Centaur Technology, Inc. | Dual branch execute and table update with single port |
| US12443412B2 (en) | 2022-01-30 | 2025-10-14 | Simplex Micro, Inc. | Method and apparatus for a scalable microprocessor with time counter |
| US11829762B2 (en) | 2022-01-30 | 2023-11-28 | Simplex Micro, Inc. | Time-resource matrix for a microprocessor with time counter for statically dispatching instructions |
| US12001848B2 (en) | 2022-01-30 | 2024-06-04 | Simplex Micro, Inc. | Microprocessor with time counter for statically dispatching instructions with phantom registers |
| US11954491B2 (en) | 2022-01-30 | 2024-04-09 | Simplex Micro, Inc. | Multi-threading microprocessor with a time counter for statically dispatching instructions |
| US11829767B2 (en) | 2022-01-30 | 2023-11-28 | Simplex Micro, Inc. | Register scoreboard for a microprocessor with a time counter for statically dispatching instructions |
| US11829187B2 (en) | 2022-01-30 | 2023-11-28 | Simplex Micro, Inc. | Microprocessor with time counter for statically dispatching instructions |
| US12190116B2 (en) | 2022-04-05 | 2025-01-07 | Simplex Micro, Inc. | Microprocessor with time count based instruction execution and replay |
| US12169716B2 (en) | 2022-04-20 | 2024-12-17 | Simplex Micro, Inc. | Microprocessor with a time counter for statically dispatching extended instructions |
| US12141580B2 (en) | 2022-04-20 | 2024-11-12 | Simplex Micro, Inc. | Microprocessor with non-cacheable memory load prediction |
| US12106114B2 (en) | 2022-04-29 | 2024-10-01 | Simplex Micro, Inc. | Microprocessor with shared read and write buses and instruction issuance to multiple register sets in accordance with a time counter |
| US12288065B2 (en) | 2022-04-29 | 2025-04-29 | Simplex Micro, Inc. | Microprocessor with odd and even register sets |
| US12112172B2 (en) | 2022-06-01 | 2024-10-08 | Simplex Micro, Inc. | Vector coprocessor with time counter for statically dispatching instructions |
| US12541369B2 (en) | 2022-07-13 | 2026-02-03 | Simplex Micro, Inc. | Executing phantom loops in a microprocessor |
| US12147812B2 (en) | 2022-07-13 | 2024-11-19 | Simplex Micro, Inc. | Out-of-order execution of loop instructions in a microprocessor |
| US12282772B2 (en) | 2022-07-13 | 2025-04-22 | Simplex Micro, Inc. | Vector processor with vector data buffer |
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| US12566610B2 (en) | 2023-03-14 | 2026-03-03 | Simplex Micro, Inc. | Microprocessor with apparatus and method for replaying load instructions |
| US12566613B2 (en) * | 2023-11-13 | 2026-03-03 | Simplex Micro, Inc. | Microprocessor with speculative and in-order register sets |
| US12340216B1 (en) * | 2023-12-22 | 2025-06-24 | Arm Limited | Control of instruction issue based on issue groups |
| US12613698B2 (en) | 2024-03-19 | 2026-04-28 | Simplex Micro, Inc. | Apparatus and method for hiding vector load latency in a time-based vector coprocessor |
| CN120335872B (zh) * | 2025-06-20 | 2025-09-12 | 南京沁恒微电子股份有限公司 | 能够精确延时控制的cpu及精确延时控制方法 |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5404469A (en) * | 1992-02-25 | 1995-04-04 | Industrial Technology Research Institute | Multi-threaded microprocessor architecture utilizing static interleaving |
| US5657315A (en) * | 1995-06-01 | 1997-08-12 | International Business Machines Corporation | System and method for ring latency measurement and correction |
| US5745724A (en) * | 1996-01-26 | 1998-04-28 | Advanced Micro Devices, Inc. | Scan chain for rapidly identifying first or second objects of selected types in a sequential list |
| US5828868A (en) * | 1996-11-13 | 1998-10-27 | Intel Corporation | Processor having execution core sections operating at different clock rates |
-
1998
- 1998-08-11 US US09/132,043 patent/US6035389A/en not_active Expired - Lifetime
-
1999
- 1999-08-10 AU AU55506/99A patent/AU5550699A/en not_active Abandoned
- 1999-08-10 JP JP2000565456A patent/JP3984786B2/ja not_active Expired - Fee Related
- 1999-08-10 WO PCT/US1999/017948 patent/WO2000010076A1/en not_active Ceased
- 1999-08-10 HK HK02103640.6A patent/HK1041947B/zh not_active IP Right Cessation
- 1999-08-10 CN CNB998120030A patent/CN1138205C/zh not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2002522841A (ja) | 2002-07-23 |
| CN1138205C (zh) | 2004-02-11 |
| AU5550699A (en) | 2000-03-06 |
| US6035389A (en) | 2000-03-07 |
| CN1323412A (zh) | 2001-11-21 |
| HK1041947A1 (en) | 2002-07-26 |
| WO2000010076A1 (en) | 2000-02-24 |
| HK1041947B (zh) | 2004-12-10 |
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