JP3983482B2 - 高速ディスプレースメント付きｐｃ相対分岐方式 - Google Patents

高速ディスプレースメント付きｐｃ相対分岐方式 Download PDF

Info

Publication number
JP3983482B2
JP3983482B2 JP2001026253A JP2001026253A JP3983482B2 JP 3983482 B2 JP3983482 B2 JP 3983482B2 JP 2001026253 A JP2001026253 A JP 2001026253A JP 2001026253 A JP2001026253 A JP 2001026253A JP 3983482 B2 JP3983482 B2 JP 3983482B2
Authority
JP
Japan
Prior art keywords
bit
address
instruction
instruction word
displacement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001026253A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002229778A (ja
JP2002229778A5 (enExample
Inventor
雄樹 近藤
修 西井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2001026253A priority Critical patent/JP3983482B2/ja
Priority to US10/017,198 priority patent/US7003651B2/en
Publication of JP2002229778A publication Critical patent/JP2002229778A/ja
Publication of JP2002229778A5 publication Critical patent/JP2002229778A5/ja
Application granted granted Critical
Publication of JP3983482B2 publication Critical patent/JP3983482B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/382—Pipelined decoding, e.g. using predecoding
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/324—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address using program counter relative addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2001026253A 2001-02-02 2001-02-02 高速ディスプレースメント付きｐｃ相対分岐方式 Expired - Fee Related JP3983482B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001026253A JP3983482B2 (ja) 2001-02-02 2001-02-02 高速ディスプレースメント付きｐｃ相対分岐方式
US10/017,198 US7003651B2 (en) 2001-02-02 2001-12-18 Program counter (PC) relative addressing mode with fast displacement

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001026253A JP3983482B2 (ja) 2001-02-02 2001-02-02 高速ディスプレースメント付きｐｃ相対分岐方式

Publications (3)

Publication Number Publication Date
JP2002229778A JP2002229778A (ja) 2002-08-16
JP2002229778A5 JP2002229778A5 (enExample) 2006-06-08
JP3983482B2 true JP3983482B2 (ja) 2007-09-26

Family

ID=18891096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001026253A Expired - Fee Related JP3983482B2 (ja) 2001-02-02 2001-02-02 高速ディスプレースメント付きｐｃ相対分岐方式

Country Status (2)

Country Link
US (1) US7003651B2 (enExample)
JP (1) JP3983482B2 (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7111148B1 (en) 2002-06-27 2006-09-19 Intel Corporation Method and apparatus for compressing relative addresses
US7010665B1 (en) 2002-06-27 2006-03-07 Intel Corporation Method and apparatus for decompressing relative addresses
JP3862642B2 (ja) * 2002-09-17 2006-12-27 株式会社日立製作所 データ処理装置
US8006071B2 (en) 2004-03-31 2011-08-23 Altera Corporation Processors operable to allow flexible instruction alignment
CN1329839C (zh) * 2005-04-13 2007-08-01 柴钰 一种计算机cpu抗干扰的设计方法
US7792150B2 (en) 2005-08-19 2010-09-07 Genband Us Llc Methods, systems, and computer program products for supporting transcoder-free operation in media gateway
JP2008204249A (ja) 2007-02-21 2008-09-04 Renesas Technology Corp データプロセッサ
US20100161950A1 (en) * 2008-12-24 2010-06-24 Sun Microsystems, Inc. Semi-absolute branch instructions for efficient computers
CN103984637A (zh) * 2013-02-07 2014-08-13 上海芯豪微电子有限公司 一种指令处理系统及方法
CN104731718A (zh) * 2013-12-24 2015-06-24 上海芯豪微电子有限公司 一种缓存系统和方法
US10261911B2 (en) * 2016-09-08 2019-04-16 The Johns Hopkins University Apparatus and method for computational workflow management

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5608886A (en) * 1994-08-31 1997-03-04 Exponential Technology, Inc. Block-based branch prediction using a target finder array storing target sub-addresses
JP3599499B2 (ja) * 1996-10-25 2004-12-08 株式会社リコー 中央処理装置
US6243805B1 (en) * 1998-08-11 2001-06-05 Advanced Micro Devices, Inc. Programming paradigm and microprocessor architecture for exact branch targeting
US6237087B1 (en) * 1998-09-30 2001-05-22 Intel Corporation Method and apparatus for speeding sequential access of a set-associative cache
US6502185B1 (en) * 2000-01-03 2002-12-31 Advanced Micro Devices, Inc. Pipeline elements which verify predecode information

Also Published As

Publication number Publication date
JP2002229778A (ja) 2002-08-16
US20020108029A1 (en) 2002-08-08
US7003651B2 (en) 2006-02-21

Similar Documents

Publication Publication Date Title
JP3958662B2 (ja) プロセッサ
JP3842474B2 (ja) データ処理装置
JP3547139B2 (ja) プロセッサ
JP2816248B2 (ja) データプロセッサ
JP5357181B2 (ja) コンピュータ・システム、その動作方法、及び、コンピュータ・プログラム
JPH1091443A (ja) 情報処理回路、マイクロコンピュータ及び電子機器
JP2009230339A (ja) 単精度浮動小数点データの格納方法およびプロセサ
JP3983482B2 (ja) 高速ディスプレースメント付きｐｃ相対分岐方式
US6687808B2 (en) Data processor using indirect register addressing
JPH09269895A (ja) データ処理装置
US5815420A (en) Microprocessor arithmetic logic unit using multiple number representations
JP2669158B2 (ja) データ処理装置
JPH04260930A (ja) データ処理装置
JPH1049369A (ja) データ処理装置
JP2020502669A (ja) ベクトル生成命令
US5966514A (en) Microprocessor for supporting reduction of program codes in size
JP3345787B2 (ja) データ処理装置
JPH07239780A (ja) １クロック可変長命令実行処理型命令読み込み電子計 算機
JP2008204249A (ja) データプロセッサ
JP2556182B2 (ja) デ−タ処理装置
JP4228241B2 (ja) 演算処理装置
JP3532835B2 (ja) データ処理装置およびプログラム変換装置
JP2504312B2 (ja) プライオリティエンコ―ダ及びそれを備えたデ―タ処理装置
JPH04260926A (ja) ビット検索回路及びそれを備えたデータ処理装置
JPH08212789A (ja) 連想メモリ回路及びｔｌｂ回路

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060411

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060411

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20060411

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20061116

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061121

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070122

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070703

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070704

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100713

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110713

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110713

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110713

Year of fee payment: 4

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees