JP3968382B2 - Pipeline A / D Converter Test Method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method of testing a pipeline type A / D converter for A / D converting an analog signal into a digital signal.
[0002]
[Prior art]
Conventionally, as a pipeline type A / D converter, for example, the one shown in FIG. 6 is known.
As shown in FIG. 6, this pipeline type A / D converter includes unit blocks 1-1 to 1-4 from the first stage to the fourth stage, and an A / D converter 2 at the fifth stage. These are connected in five stages in cascade.
[0003]
Further, in this pipeline type A / D converter, the unit blocks 1-1 to 1-4 and the A / D converter 2 have m ₁ = 3 bits out of 14-bit digital signals output from the encoder 3, m ₂ = 3 bits, m ₃ = 3 bits, m ₄ = 3 bits, and m ₅ = 2 bits.
For this reason, the encoder 3 can obtain a digital output signal of m ₁ + m ₂ + m ₃ + m ₄ + m ₅ = 14 bits. Here, m ₁ is the most significant side and m ₅ is the least significant side.
[0004]
Since the unit blocks 1-1 to 1-4 have the same configuration, the configuration of the unit block 1-1 will be described.
That is, the unit block 1-1 includes a sub A / D converter 4, a D / A converter 5, a subtractor 6, and an amplifier 7, as shown in FIG.
The sub A / D converter 4 performs A / D conversion of the analog input signal Vin into a digital signal of (2 ^{m1 + 1} −1) value. That is, since m ₁ = 3 bits, it is converted into a 15-value digital signal. The digital signals are output to the encoder 3 and the D / A converter 5, respectively.
[0005]
The D / A converter 5 D / A converts the 15-value digital signal from the sub A / D converter 4 into a corresponding analog signal Va and outputs the analog signal Va to the subtracter 6. The subtracter 6 subtracts the analog signal Va from the analog input signal Vin and outputs the subtracted output signal (Vin−Va) to the amplifier 7. The amplifier 7 amplifies the output signal from the subtracter 6 by a predetermined factor and outputs the amplified signal to the next unit block 1-2.
[0006]
Next, the operations of the sub A / D converter 4 in the first stage unit block 1-1 and the sub A / D converter (not shown) in the second stage unit block 1-2 will be described with reference to FIG. I will explain.
In FIG. 7, each vertical axis represents the input range of the analog input signal of the sub A / D converter 4 of the unit block 1-1 of the first stage and the sub A / D converter of the unit block 1-2 of the second stage. Represents.
[0007]
As shown in the figure, if the analog input signal Vin has the value shown in the figure, the conversion value (digital code) of the A / D conversion of the sub-A / D converter 4 in the first stage is “5”. The second-stage sub A / D converter enlarges (amplifies) this portion in order to further A / D convert the range of “5”. There is an amplifier 7 for the purpose of this amplification.
However, if the amplifier 7 simply amplifies the analog input signal Vin, the output signal of the amplifier 7 exceeds the input range of the second-stage sub A / D converter. For this reason, in order to match the input range, it is necessary to subtract a certain analog value by the subtractor 6 according to the result of the A / D conversion of the sub A / D converter 4. In this example, when an analog value corresponding to the digital value “4” is subtracted, the output of the amplifier 7 falls within the input range of the second-stage sub A / D converter. For this purpose, the D / A converter 5 is required.
[0008]
[Problems to be solved by the invention]
By the way, in the conventional pipeline type A / D converter operating as described above, the characteristics of the output signals with respect to the input signals of the unit blocks 1-1 to 1-4 in the first stage to the fourth stage are shown in FIG. It has the characteristics shown in Fig. 1 and has discontinuities. That is, as shown in FIG. 8, the transition of the output code of the sub-A / D converter 4 of the unit block becomes a discontinuity point.
[0009]
8 indicate digital codes of the sub A / D converter 4 and the D / A converter 5.
In this way, since the input / output characteristics of the unit block have discontinuous points as described above, there is a possibility that code loss may occur at the discontinuous points, resulting in a defective product. It is necessary to test with a good product selection test.
Here, the lack of code means that a specific digital code is missing without being output among the output codes of the entire pipeline type A / D converter.
[0010]
If the analog input signal is just a voltage at a discontinuous point, whether the output signal Vout of the unit block 1-1 at the first stage is the upper or lower pole of the sawtooth wave shown in FIG. Is unknown. However, the same code must be output as the output code of the entire A / D converter (since the input is the same, the same code is output if there is no circuit failure).
For this reason, even when the output signal Vout of the unit block 1-1 at the first stage is the upper pole or the lower pole, the width of the discontinuous point is set so that the digital output code as the whole A / D converter is the same. (Sawtooth tooth height) is designed.
[0011]
However, if the width of the discontinuous point deviates from the design value due to a circuit failure, the digital output code of the entire A / D converter changes between the upper and lower poles, and the digital output code is equivalent to the amount of change. The inconvenience of not coming out or coming out too much will occur.
In addition, the location where the discontinuity where code loss may occur varies from product to product due to the random offset of the secondary A / D converter or D / A converter, and it is difficult to predict where the discontinuity will be output.
[0012]
For this reason, in the conventional A / D converter non-defective product selection test, the analog input signal is changed over the entire range in order to cover the entire input range of the A / D converter, and all codes are output accordingly. It was necessary to check if. As a result, conventionally, it took a long time to test the A / D converter.
Therefore, in view of the above points, the object of the present invention is to select only before and after the discontinuity point of the input / output characteristics of the unit block so that the operation test can be performed, thereby shortening the operation test time and improving the productivity. It is to provide a pipeline type a / D converter testing method which is adapted achieved.
[0013]
[Means for Solving the Problems]
In order to solve the above problems and achieve the object of the present invention, the invention described in claim 1 is configured as follows.
That is, according to the first aspect of the present invention, a sub A / D converter that A / D converts an analog input signal into a digital signal, and a D / A converter that D / A converts the A / D converted digital signal into an analog signal. An A converter, a subtracter that subtracts the output analog signal of the D / A converter from the analog input signal, and an amplifier that amplifies the output of the subtractor are used as a unit block, and one or a plurality of the unit blocks are cascaded. A pipeline that is connected and includes an A / D converter that A / D converts an analog signal output from the last stage of the unit block into a digital signal, and can obtain an N-bit digital output as a whole. In the test method of the type A / D converter, the sub-A / D converter of the unit block is used as the input of the D / A converter of the unit block of the first stage. Input a predetermined code out of the codes that can be output from the data, change the analog input signal within the test range corresponding to the predetermined code, and measure the output code of the pipeline type A / D converter in response to the change The first step and the codes that can be output from the sub-A / D converter of the unit block in the first stage are sequentially input, and at this time, the values corresponding to the respective codes are sequentially input as the analog input signals. And a second step of measuring an output code of the pipeline type A / D converter with respect to the change of the code.
[0016]
According to the present invention that Do such a configuration, it is possible to improve the productivity by shortening the pipelined A / D converter test time.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the configuration of the first embodiment of the pipeline type A / D converter of the present invention will be described with reference to FIG.
As shown in FIG. 1, the first embodiment includes unit blocks 11-1 to 11-4 from the first stage to the fourth stage and an A / D converter 12 at the fifth stage, and these are the whole. With 5 stages cascade connection.
[0018]
The pipeline type A / D converter includes unit blocks 11-1 to 11-4 and the A / D converter 12 includes m ₁ = 3 bits out of 14-bit digital signals output from the encoder 13, m ₂ = 3 bits, m ₃ bits = 3, m ₄ = 3 bits, and m ₅ bits = 2. For this reason, the encoder 13 can obtain a digital output signal of m ₁ + m ₂ + m ₃ + m ₄ + m ₅ = 14 bits. Here, m ₁ is the most significant side and m ₅ is the least significant side.
[0019]
As shown in FIG. 1, the unit block 11-1 includes a sub A / D converter 14, a D / A converter 15, a subtracter 16, an amplifier 17, and a changeover switch 18.
The sub A / D converter 14 A / D converts the analog input signal Vi into a digital signal (digital code) having a value of (2 ^{m1 + 1} +1). That is, since m ₁ = 3 bits, it is converted into a 17-value digital signal (see FIG. 2).
[0020]
The sub A / D converter 14 includes, for example, a resistor (not shown) that equally divides the input range into 2 ^{m1 + 1} = 16, and 16 pieces that determine the center of each of the divided ranges. A comparator (not shown) is included, and a 17-value digital code of “0 to 16” is output.
A changeover switch 18 is disposed between the sub A / D converter 14 and the D / A converter 15. The changeover switch 18 selectively inputs the output digital code D1 of the sub A / D converter 14 and the test digital code D2 input from the outside during the test as described later to the D / A converter 15. is there.
[0021]
Further, the output digital code D1 and the test digital code D2 of the sub A / D converter 14 which are selectively input to the D / A converter 15 by the changeover switch 18 are supplied to the encoder 13. Yes.
The D / A converter 15 converts the 17-value digital code D1 from the sub A / D converter 14 or the test digital code D2 input from the outside into an analog signal Va and outputs the analog signal Va to the subtracter 16. ing.
[0022]
The subtracter 16 subtracts the analog signal Va from the analog input signal Vin and outputs the subtracted output signal (Vin−Va) to the amplifier 17. The amplifier 17 amplifies the output signal from the subtracter 16 by a predetermined factor (8 times) and outputs the amplified signal to the next unit block 11-2.
Since the unit blocks 11-2 to 11-4 are configured similarly, the unit block 11-2 will be described.
[0023]
As shown in FIG. 1, the unit block 11-2 includes a sub A / D converter 24, a D / A converter 25, a subtractor 26, and an amplifier 27. This configuration is the unit block 1 shown in FIG. -2.
That is, the sub A / D converter 24 A / D converts the analog input signal Vi into a digital signal having a value of (2 ^{m2 + 1} −1). That is, since m ₂ = 3 bits, it is converted into a 15-value digital signal. The digital signals are output to the encoder 13 and the D / A converter 25, respectively.
[0024]
The D / A converter 25 D / A converts the 15-value digital signal from the sub A / D converter 24 into a corresponding analog signal and outputs it to the subtractor 26. The subtractor 26 subtracts the output analog signal of the D / A converter 25 from the output signal of the amplifier 17 and outputs the subtracted output signal to the amplifier 27. The amplifier 27 amplifies the output signal from the subtractor 26 by 8 times and outputs the amplified signal to the next unit block 11-3.
[0025]
Next, in the first embodiment having such a configuration, the normal operation of the first-stage unit block 11-1 and the second-stage unit block 11-2 will be described with reference to FIGS. explain. During this normal operation, the changeover contact of the changeover switch 18 is in the position shown in FIG.
In FIG. 2, each vertical axis represents the input range of the analog input signal of the sub A / D converter 14 of the first unit block 11-1 and the sub A / D converter 24 of the second unit block 11-2. Represents each.
[0026]
Now, when the analog input signal Vin is input to the sub A / D converter 14 of the unit block 11-1 shown in FIG. 1, the sub A / D converter 14 selects “0” according to the magnitude of the analog input signal Vin. To 16 "digital code D1. For example, when the analog input signal Vin has a value as shown in FIG. 2, the corresponding digital code D1 is “5”.
The D / A converter 15 converts the analog signal Va as shown in the following equation (1) according to the digital code D1.
[0027]
Va = D1 × (Vref / 8) (1)
Here, Vref in the equation (1) is a reference voltage that determines the gain of the D / A converter 15.
The subtractor 16 subtracts the analog signal Va from the analog input signal Vin and outputs the subtracted output signal (Vin−Va) to the amplifier 17. The amplifier 17 amplifies the output signal from the subtracter 16 by 8 times. Therefore, the output signal Vout of the unit block 11-1 is expressed by the following equation (2).
[0028]
Vout = 8 × [Vin−D1 × (Vref / 8)] = 8 × Vin−D1 × Vref (2)
In this embodiment that operates as described above, the output signal Vout of the unit block 11-1 at the first stage has characteristics as shown in FIG. 3 with respect to the analog input signal Vin. Here, the numerical values 0, 1, 2, 3,... In the figure indicate the digital codes of the sub A / D converter 14 and the D / A converter 15, and are “0” and “16” as compared with the conventional case. Is added (see FIG. 8).
[0029]
As can be seen from FIG. 3, the output signal range of the amplifier 17 is as shown in B, and can be halved as compared with the output signal range A in the conventional case. Can be halved.
Therefore, according to this embodiment, the power supply voltage of the amplifier 17 can be greatly reduced, so that low power consumption can be realized.
Next, a test method of an operation test for determining whether or not the operation is normal in this embodiment will be described with reference to FIGS.
[0030]
FIG. 4 shows the relationship of the above equation (2), and there is a discontinuity point in the output signal Vout at the point where the output digital code D1 (0 to 16) of the sub A / D converter 14 changes. To do. If there is a difference in the output code as a 14-bit A / D converter before and after the discontinuous point, code loss occurs.
Therefore, at the time of the operation test, the switching contact of the changeover switch 18 is switched to the opposite side of FIG. 1 and the test digital code D2 is input to the D / A converter 15 via the changeover switch 18.
[0031]
In the operation test of the first embodiment, a discontinuous point is arbitrarily generated, and it is confirmed that there is no change in the output code as a 14-bit A / D converter before and after the discontinuous point. Make sure there are no chips.
Next, specific test procedures will be described below.
(1) The switching contact of the selector switch 18 is switched to the opposite side of FIG.
(2) Check whether the lower 11 bits are operating normally.
[0032]
The value of the test digital code D2 is set to D2 = 8, and the analog input signal Vin is changed within the range of the test range Vtest (the range of the test digital code D2) shown in FIG. Then, it is checked whether or not all the lower 11 bits of output digital codes are output from the encoder 13 corresponding to the change.
As a result, when all the codes of the lower 11 bits are output from the encoder 13, the operations of the unit blocks 11-2 to 11-4 in the second to fourth stages and the A / D converter 12 are normal. is there.
[0033]
The same circuit is used for the lower 11 bits not only for the test range Vtest but also for the analog input signal Vin in other ranges, so if the test is performed in the test range Vtest, There is no need for testing.
(3) It is confirmed whether or not the output digital code of the encoder 13 is the same when the test code D2 changes from D2 = 0 to D2 = 1.
At this time, the analog input signal Vin is set to Vin≈V1 (see FIG. 4), and when D2 = 0 and D2 = 1, the 14-bit output digital code output from the encoder 13 is measured, and both outputs are measured. Check if the digital codes are the same.
[0034]
In this case, when both output digital codes do not match, it becomes defective.
(4) Furthermore, the point that the test code D2 changes from D2 = 1 to D2 = 2, D2 = 2 to D2 = 3,... D2 = 15 to D2 = 16 is the same as (3). In addition, it is confirmed whether or not the output digital code of the encoder 13 is the same at the change point.
At this time, the analog input signal Vin must be changed so that Vin≈V2 from D2 = 1 to D2 = 2 and Vin≈V3 from D2 = 2 to D2 = 3.
[0035]
From the tests (1) to (4) as described above, it is possible to confirm whether or not all 14-bit output digital codes to be output from the encoder 13 are output according to the analog input signal Vin. In this case, most of the test time is the time taken for the operation test of the lower 11 bits in (2).
On the other hand, in the conventional test method, the tests (1), (3), and (4) are unnecessary. However, in (2), this is equivalent to expanding the test range Vtest of the analog input signal Vin to the entire range of the sub A / D converter 14 and confirming that all 14-bit output codes are output from the encoder 13. As a result, the test range Vtest is about eight times wider.
[0036]
Therefore, according to the operation test according to the first embodiment, the time for the operation test can be shortened to １ ／ compared to the conventional case.
Next, the configuration of the second embodiment of the pipeline type A / D converter of the present invention will be described with reference to FIG.
In the second embodiment, the unit block 11-1 of the first embodiment shown in FIG. 1 is replaced with a unit block 11-1A as shown in FIG.
[0037]
That is, the unit block 11-1A of the second embodiment includes a sub A / D converter 14A, a D / A converter 15A, a subtracter 16, an amplifier 17, and a changeover switch 18, as shown in FIG. It is configured.
The sub A / D converter 14 A / D converts the analog input signal Vin into a digital signal (digital code) having a value of (2 ^{m1 + 1} −1). That is, since m ₁ = 3 bits, it is converted into a 15-value digital signal.
[0038]
Further, a changeover switch 18 is disposed between the sub A / D converter 14A and the D / A converter 15A. The changeover switch 18 selectively inputs the output digital code D1 of the sub A / D converter 14A and the test digital code D2 input from the outside during the test to the D / A converter 15A.
Further, the output digital code D1 and the test digital code D2 of the sub A / D converter 14A selectively inputted to the D / A converter 15A by the changeover switch 18 are supplied to the encoder 13A. .
[0039]
The D / A converter 15A converts the 15-value digital code D1 from the sub A / D converter 14A or the test digital code D2 input from the outside into an analog signal Va and outputs the analog signal Va to the subtracter 16. ing.
The subtracter 16 subtracts the analog signal Va from the analog input signal Vin and outputs the subtracted output signal (Vin−Va) to the amplifier 17. The amplifier 17 amplifies the output signal from the subtractor 16 by 8 times and outputs the amplified signal to the next unit block 11-2.
[0040]
In addition, since the structure of the other part of this 2nd Embodiment is the same as that of the structure of 1st Embodiment of FIG. 1, the description is abbreviate | omitted.
In the second embodiment configured as described above, the operation test can be performed by the same procedure as in the first embodiment. For this reason, the time for the operation test can be shortened to about 1/8 compared with the conventional method.
[0042]
As described above , according to the test method of the present invention, it is possible to shorten the operation test time of the pipeline type A / D converter and improve the productivity.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a pipeline type A / D converter of the present invention.
2 is an explanatory diagram for explaining the operation of a sub A / D converter and the like of the unit block in the first stage of FIG. 1; FIG.
FIG. 3 is a characteristic diagram showing the relationship between the input and output of the unit block in the first stage of FIG.
FIG. 4 is a diagram for explaining an operation test method according to the first embodiment;
FIG. 5 is a block diagram showing a configuration of a second embodiment of a pipeline type A / D converter of the present invention.
FIG. 6 is a block diagram showing a configuration of a conventional pipeline type A / D converter.
7 is an explanatory diagram for explaining the operation of a sub A / D converter and the like of the unit block in the first stage of FIG. 6;
8 is a characteristic diagram showing the relationship between the input and output of the unit block in the first stage of FIG. 6. FIG.
[Explanation of symbols]
11-1 to 11-4 Unit block 12 A / D converter 13, 13A Encoder 14, 24 Sub A / D converter 15, 25 D / A converter 16, 26 Subtractor 17, 18 Amplifier

Claims (1)

A sub A / D converter for A / D converting an analog input signal into a digital signal, a D / A converter for D / A converting the A / D converted digital signal into an analog signal, and the analog input signal to the D A subtracter for subtracting the output analog signal of the A / A converter and an amplifier for amplifying the output of the subtractor are used as a unit block, and one or a plurality of the unit blocks are connected in cascade, and the last stage of the unit block A pipeline type A / D converter test method comprising an A / D converter for A / D converting an analog signal output from a digital signal into a digital signal, so that an N-bit digital output can be obtained as a whole.
As the input of the D / A converter of the unit block of the first stage, a predetermined code among the codes that can be output from the sub A / D converter of the unit block is input, and the analog input signal corresponds to the predetermined code A first step of changing within a range and measuring the output code of the pipelined A / D converter for the change;
A code that can be output from the sub-A / D converter of the unit block in the first stage is sequentially input. At this time, a value corresponding to each code is sequentially input as the analog input signal. A second step of measuring the output code of the pipelined A / D converter for
A test method for a pipelined A / D converter, comprising:

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