JP2005214849A - Automatic gain control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve AD resolution per 1dB to reduce errors generated by hardware, while reducing the number of convergence cycles of an automatic gain control (AGC) circuit to speed up the convergence speed. <P>SOLUTION: The AGC circuit for controlling the level of received signals by a gain control signal comprises an A/D converter 105 for converting the logarithmic data, obtained by applying logarithmic compression on the received signals into digital data, and a generating means 116 for a gain control signal for generating the gain control signal that offsets the error component between logarithmic data digital converted by the A/D converter and predetermined reference data. If the dynamic range of the A/D converter is set in a range narrower than the gain control range of the AGC circuit and if there is an input of level exceeding the dynamic range of the A/D converter, in the next automatic gain control cycle it is controlled so as to be forcedly made to lie within the dynamic range of the A/D converter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an automatic gain control circuit, and more particularly to an automatic gain control circuit in which the number of convergence cycles is reduced and AD resolution per 1 dB is improved to reduce errors caused by hardware.

  As an example of a conventional automatic gain control circuit (hereinafter referred to as “AGC (Automatic Gain Control circuit)”), the AGC circuit described in Patent Document 1 is used in a radar receiver, and a received pulsed received signal level is set to a predetermined level. A first means for extracting a change characteristic of the signal level of logarithmic data obtained by logarithmically compressing and amplifying the received signal, and an average logarithm representing an average value of the extracted change characteristics A second means for generating data; and a third means for generating the gain control signal at a level that cancels an error component between the generated average logarithmic data and predetermined reference data.

  In this AGC circuit, as shown in FIG. 1, the received signal amplified to the reference level for the signal output unit 10 by the variable gain amplifier 101 is demultiplexed by the coupler 102 and then input to the logarithmic compression amplifier 103. It is converted into a compressed signal (hereinafter referred to as “log data”) and output.

  This logarithmic data is detected by the detector 104, and a change feature of the signal level is extracted. The detected received signal is input to an A / D converter (analog / digital conversion circuit) 105 and is digitally converted. The converted received signal is input to the logarithmic value / true value conversion circuit 106 and converted to a true number. The received signal converted to a true number is added by the adder 107. The addition result of the received signal, which is the output of the adder 107, is divided by the number of additions in the divider 112, and the average value of the received signal is output. The average value of the received signal is converted to a logarithmic value by the true value / logarithmic value conversion circuit 114 (hereinafter referred to as “average logarithmic data”) and input to the error calculation circuit 116.

  The error calculation circuit 116 calculates a difference between the average log data and preset reference data, and outputs the error calculation circuit 116 latched in a flip-flop circuit (hereinafter referred to as “F / F”) 117, that is, The previous gain control signal is fed back to the error calculation circuit 116, and this difference is added to or subtracted from the previous gain control signal and output to the variable gain amplifier 101 as a gain control signal.

  Next, the function of each part of the AGC circuit will be described in more detail with reference to FIG.

  The logarithmic compression amplifier 103 converts and amplifies the received signal into logarithmic data, and the dynamic range of the logarithmic compression amplifier 103 covers a gain control range value necessary for the AGC circuit. Hereinafter, description will be made assuming that the dynamic range of the logarithmic compression amplifier 103 is 40 dB. Also, the output of the logarithmic compression amplifier 103 should not exceed the input range of the A / D converter 105. An example of the output characteristic of the logarithmic compression amplifier 103 is shown in FIG. As shown in the figure, when the input of the logarithmic compression amplifier 103, that is, the output of the variable gain amplifier 101 changes from +20 dBm to -20 dBm, the output of the logarithmic compression amplifier 103 changes linearly from 0V to 4V.

  The detector 104 detects the logarithmic data from the logarithmic compression amplifier 103 and extracts the amplitude component of the received signal. As shown in FIG. 2, the output of the detector 104 is a pulsed signal.

  The A / D converter 105 converts the amplitude component of the extracted logarithmic data into a digital value (binary number). As a result, the level of the sampled received signal is detected as a logarithmic value. Here, the number of bits required for the A / D converter 105 depends on the gain control accuracy required of the AGC circuit in the change of the output voltage of the logarithmic compression amplifier 103 to be used. For example, when ± 1 dB is required for the gain control accuracy, the output voltage change amount of the logarithmic compression amplifier 103 when the input is changed by 1 dB is determined to be a value that can be detected by the A / D converter 105. In the example shown in FIG. 3, the A / D converter 105 uses an 8-bit A / D converter with an input voltage range of 10V.

The logarithmic value / true value conversion circuit 106 converts logarithmic data converted into a digital value into a true number (binary number). This is to convert a digital value detected as a logarithmic value into a true value in order to add the received signal level by the adder 107, and is realized by using, for example, a ROM (Read Only Memory). A digital value converted from the A / D converter 105 is input to the input address of the ROM (106R), and a true value converted corresponding to the input address value is output. The true value Y to be output is given that the input address value is X.
Y = 10Λ (C × X)
Calculated by Note that the symbol Λ indicates a power. Symbol C is a value determined according to the non-linearity of the logarithmic compression amplifier 103 and is changed according to the hardware.

An example of data stored in the ROM (106R) is shown in FIG. In the example shown in the figure, the analog input voltage of the A / D converter 105 corresponds to 10V, and the output is 8 bits. Therefore, the input range of the ROM (106R) is from “0” to “255”. Become. When the ROM output value (decimal number) is Y and the ROM input address value (decimal number) is X, the output true value is expressed by the following equation.
Y = 10Λ (X × 10VOLT / 256)

  Since the input address “102” or higher is premised on the output of the logarithmic compression amplifier 103 being saturated at 4V, the ROM output is fixed to “9732”. Input addresses “0” and “102” correspond to inputs “0” and “4” of the A / D converter 105, respectively. The number of bits necessary to represent the ROM output value “9732” is at least 14 bits.

  For example, the adder 107 includes an F / F 109 at the output of the full adder 108 having two inputs, and connects the output of the logarithmic value / true value conversion circuit 106 as one input of the full adder 108. Connect the output of F / F109 as the other input. As shown in FIG. 2, the number of additions in the adder 107 is determined by the product of the number of times of sampling within one pulse signal period and the received signal within the observation period. From the radar receiver system control unit (not shown) The trigger signal 111 is input to the F / F 109. Further, the number of bits required for the full adder 108 needs to have a bit number that does not overflow the digit of the full adder 108 even if the maximum level of the received pulse signal is added the maximum number of times.

  The counter 110 gives the number of additions in the adder 107 to the divider 112. Divider 112 divides the total added value of the signal level of the received signal output from adder 107 by the total number of additions, and obtains the average value of the received signal. For the total number of additions, the counter 110 counts the trigger signal input to the F / F 109. If the total number of additions is a multiple of 2, it is equivalent to dividing by 2 by shifting the output of the adder 107 to the 1-bit LSB side, so the structure of the divider 112 is simplified. can do. In this case, the divider 112 can be realized by connecting the required number of n: 1 data selectors in parallel.

The true value / logarithmic value conversion circuit 114 converts the average value of the received signal output from the divider 112 into a logarithmic value (binary number), that is, average logarithmic data. For example, a ROM (114R) is used. Realized. The average value of the received signal, which is a true value, is input to the input address of the ROM (114R). The average logarithmic data Y to be output is Y = 10log (10) X where X is the input address value.
Calculated by

  A data example of the ROM (114R) is shown in FIG. However, the set numerical value shall follow the example of FIG.3 and FIG.4. The data input to the ROM (114R) is output from the ROM (106R) used in the logarithmic value / true value conversion circuit 106 shown in FIG. As for the data structure, the input / output relationship of the ROM (106R) may be reversed. For example, when the ROM input address in FIG. 5 is “9732”, “40” is output as the average logarithmic data. Six bits are required to represent this average log data.

  The error calculation circuit 116 calculates an error amount (logarithm) between the average logarithmic data and a logarithmic value (hereinafter referred to as “reference data”) indicating a reference level as an output of the variable gain amplifier 101 using a ROM (116R). The gain control signal 115 is output. The logarithmic data is input to the input address of the ROM (116R), and a new gain control signal with corrected error is output. The gain control signal is latched by the F / F 117 and fed back to the input address side of the error calculation circuit 116. The output (logarithm) Y of the error calculation circuit 116 changes under the following conditions when the average logarithmic data is X and the reference data is α. However, d = | α−X |.

(1) In the case of (α−X = 0),
The reception level is the reference data α, and the output Y does not change the setting.
(2) In the case of (α−X> 0),
The reception level is lower than the reference data α, and the output Y is (Y−d).
(3) In the case of (α−X <0),
The reception level is higher than the reference data α, and the output Y is (Y + d).

  A data example of the ROM (116R) is shown in FIG. The average logarithmic data input to the ROM (116R) is 6 bits from FIG. 5, and since the ROM (116R) output is feedback connected to the input of the ROM (116R), the input address signal is input. Therefore, 12 bits are required. Here, if the reference level is 4 V at the output of the logarithmic compression amplifier 103, the data shown in FIG. 6 is output. Although the numerical value on the right side is omitted due to space limitations, the numerical value decreases to 0 by 1 in the right direction.

  For example, the ROM (116R) when the average log data is input to the upper 6 bits of the input address of the ROM (116R) and the output of the F / F 117 fed back to the lower 6 bits of the input address is input. When the average logarithmic data is “40” and the previously set gain control signal is “40”, the output is “40” from FIG. 6, and the gain control signal output to the variable gain amplifier 101 is , “40”.

  The F / F 117 holds the output of the error calculation circuit 116, outputs a gain control signal to the variable gain amplifier 101, and inputs the feedback to the error calculation circuit 116. The latch signal 118 input to the F / F 117 is input after the necessary total number of additions in the adder 107 has elapsed, as shown in FIG. The gain control signal held in the F / F 117 performs AGC control on the variable gain amplifier 101.

  Next, the operation of the AGC circuit will be described with reference to FIG. The graph shown in FIG. 3 shows the output characteristics of the logarithmic compression amplifier 103 when the output value of the variable gain amplifier 101 is 40 dB. Further, as setting conditions, it is assumed that the input of the variable gain amplifier 101 changes from +20 dBm to −20 dBm, the reference voltage of the A / D converter 105 is 10 V, and the output is a digital value represented by 8 bits. The output of the variable gain amplifier 101 is AGC controlled so that the output of the logarithmic compression amplifier 103 becomes 4V. At this time, when the input of the variable gain amplifier 101 is +20 dBm or more, the output of the logarithmic compression amplifier 103 is slightly higher than 4V. Let's saturate. The gain control signal (data) used for AGC control of the variable gain amplifier 101 is 6 bits.

  The minimum number of output bits required for the ROM (106R) is 14 bits, and the input address of the ROM (114R) also requires 14 bits. 4 and 5 show data examples of the ROM (106R) and ROM (114R), respectively. FIG. 6 is a data example of the ROM (116R).

  The operation of the error calculation circuit 116 under the above setting conditions will be described. When the previously set gain control signal is “40” and the current average logarithmic data is “40”, the new gain control signal output from the ROM (116R) is the upper 6 bits from FIG. The intersection between “40” and the lower 6 bits “40”, that is, “40”. As shown in FIG. 2, the latch signal input from the radar receiver system control unit is input after the necessary total number of additions in the adder 107 has elapsed. By this latch signal, the F / F 117 holds the output of the ROM (116R) (“40” this time) and outputs it as a gain control signal to the variable gain amplifier 101 to perform an AGC operation (where the gain control signal Is given as an attenuation).

  Here, if the observation target is changed and the average logarithmic data is changed to “33”, the previously set gain control signal is “40”, so the upper 6 bits “33” and the lower 6 bits from FIG. “33”, which is the intersection with “40”, is newly selected and becomes the output of the ROM (116R).

  When a latch signal is input to the F / F 117, the currently selected “33” is latched by the F / F 117 and fed back to the lower 6 bits of the ROM (116R), and at the same time, this data becomes a gain control signal. The gain of the variable gain amplifier 101 is changed. At this time, since the attenuation of the variable gain amplifier 101 decreases from “40” to “33”, the level of the received signal increases, and the average logarithmic data in the next observation period becomes 33+ (40−33) = 40. .

  In this observation period, the average logarithmic data changes to “40”, and the previously set gain control signal is “33”. Therefore, the upper 6 bits “40” and the lower 6 bits “33” from FIG. The intersection “33” is newly selected and becomes the ROM (116R) output. When a latch signal is input to the F / F 117, the currently selected “33” is latched by the F / F 117 and fed back to the lower 6 bits of the ROM (116R), and at the same time, this data becomes a gain control signal. Since the gain control signal does not change, the level of the received signal does not change and AGC control is stabilized. With this series of operations, the output of the variable gain amplifier 101 is always kept constant within the control range of the error calculation circuit 116.

  However, in the example described in Patent Document 1, the AGC control is set so that the output voltage of the logarithmic compression amplifier 103 is 4 V at the convergence point of AGC, but this AGC circuit does not operate normally. The reason is that since the output value is limited to 9732 at the input addresses 102 to 255 of the ROM (106R) of the logarithmic value / true value conversion circuit 106, a value greater than 9733 is not output, and true The ROM (114R) of the value / logarithm conversion circuit 114 is set so that the output 4V of the logarithmic compression amplifier 103 is set to the input address 9732 and the average reception level as an output value does not exceed 41 or more. This is because the control can be performed in the direction of increasing the gain of 101 but not in the direction of decreasing. Furthermore, when the input level is higher than the convergence level (4V), the output voltage of the logarithmic compression amplifier 103, which is an error signal, needs to be higher than 4V, but the output of the logarithmic compression amplifier 103 is saturated at over 4V. Therefore, it is also difficult to control the output level in the direction of lowering.

  In the AGC circuit described in Patent Document 1, the output voltage range of the logarithmic compression amplifier 103 is set to be narrower than the input voltage range of the A / D converter 105, and even when the change in the input level is large, a single AGC operation is performed. The purpose is to converge, but when the dynamic range of the variable gain amplifier 101 is wider or the input voltage range of the A / D converter 105 is narrow, the resolution of the A / D converter per 1 dB is lowered. In order to avoid this, normally, the variable amount of the variable gain amplifier 101 in one AGC operation is reduced, and the number of convergence cycles is increased to several times so that the resolution of the A / D converter 105 does not decrease. .

  Based on the above, an example of the prior art in which the setting of each part is reviewed with the same circuit configuration as the AGC circuit described in Patent Document 1 will be described below with reference mainly to FIG.

  The dynamic range of the variable gain amplifier 101 is set to 25 dB and is set to converge at the output of the variable gain amplifier 101 of −10 dBm. The output of the logarithmic compression amplifier 103 at this time is set to 2V. The A / D converter 105 has an operating voltage range of 1.5 to 2.5 V and does not carry even if the operating voltage range is exceeded (even if there is an input of 2.5 V or more, the output is limited to 255, On the contrary, the output becomes 0 even when the input is 1.5 V or less). The sensitivity (resolution) of the A / D converter 105 is 50 mV / dB, and the variable amount of the variable gain amplifier 101 that can be changed at a time is 10 dB.

  FIG. 7 shows the relationship between the output of the variable gain amplifier 101 and the logarithmic compression amplifier 103 and the output of the logarithmic compression amplifier 103 and the output of the A / D converter 105. As shown in the figure, the output of the logarithmic compression amplifier 103 needs to be linear between the output of the variable gain amplifier 101 and 0 to −20 dBm. Further, since the operating voltage range of the A / D converter 105 is narrower than the dynamic range of the logarithmic compression amplifier 103, when the output level of the variable gain amplifier 101 is 0 dBm or more, the output of the A / D converter 105 is 255. On the other hand, in the case of −20 dBm or less, the output of the A / D converter 105 is 0 and is limited. Since this AGC circuit performs an AGC operation using the deviation (relative value) from the convergence level as information, when the output of the variable gain amplifier 101 is -20 dBm, the relative value from the convergence level is -10 dB, and when the output is 0 dBm. The relative value from the convergence level is 10 dB.

8 and 9 are diagrams showing the settings of the logarithmic value / true value conversion circuit 106 and the true value / logarithmic value conversion circuit 114. FIG. The level data quantized by the A / D converter 105 is converted into a true value by the logarithmic value / true value conversion circuit 106, and is input to the true value / logarithmic value conversion circuit 114 through integration / average processing. Is converted to In this setting example, the data in the true value / logarithmic value conversion ROM 114 requires 21 steps of data including a gain control signal ± 10 dB that can be changed at once and a convergence level of 0. It is only necessary that the maximum value 20 of the values can be output. Therefore, in the true value / logarithmic value conversion ROM 114, if the data is Y,
Y = 10 * LOG10 (X)
An address may be set to a value that becomes. In addition, the logarithmic value / true value conversion circuit 106 has an input address X and the maximum value A of the true value / logarithmic value conversion ROM 114,
Y = 10Λ (A * ((X + 1) / 256) / 10) = 10Λ ((X + 1) × 0.00781
Given in. Since the ROM data is an integer, the obtained Y is rounded off.

  FIG. 10 is a diagram showing the relationship between the input voltage of the A / D converter 105 and the output of the true value / logarithmic value conversion ROM 114. For example, when 2 V, which is the convergence level, is continuously input to the input voltage of the A / D converter 105, a value “meaning the convergence level” is obtained by the operation from the A / D converter 105 to the true / logarithmic value conversion ROM 114. 10 "is output. Similarly, if a voltage of 1.5 V or less continues to be input, the deviation from the convergence level is “−10 dB” from the true / logarithmic conversion ROM 114, and if a voltage of 2.5 V or more is continuously input, the convergence level is reached. “20” with a shift of 10 dB is output and output to the error calculation circuit 116.

  Further, as shown in FIG. 7, since the center value 127 of the output of the A / D converter 105 is set to the convergence level and the resolution per 1 dB is 50 mV / dB, the output of the true value / logarithmic value conversion ROM 114 is Only when “0” or “20”, the input voltage range of the A / D converter 105 is 25 mV (the input voltage range of the A / D converter 105 is half of the other values, but 1.5 V or less. If the voltage is 2.5 V or higher, the output of the A / D converter 105 is limited, so there is substantially no problem).

  FIG. 11 is a diagram showing the contents of the ROM (116R) of the error calculation circuit 116. As shown in FIG. The vertical column in the figure shows the current gain control signal held by the F / F 117 at the subsequent stage of the error calculation circuit 116, and is input to the lower 5 bits of the input address of the error calculation ROM 116. On the other hand, the horizontal column indicates the output of the true value / logarithmic value conversion ROM 114 and is input to the upper 5 bits of the input address of the error calculation ROM 116. The output of the input true value / logarithmic value conversion ROM 114 serves as data representing a deviation from the convergence level in this AGC circuit, and the level difference shown on the right side of the output value of the true value / log value conversion ROM 114 is shown. Think of it as data and do not enter it into the actual ROM.

  The operation of the AGC circuit having the above configuration will be described. A case where the current gain control signal is 17 dB will be described. When the output signal level is −20 dBm and the detection voltage is 1.5 V, the data quantized by the A / D converter 105 undergoes an integration / average process, and the true value / logarithmic value conversion ROM 114 of FIG. It is converted to “0” at the output. In the converted data, “7” given at the intersection of “0” in the upper 5 bits (row) of the error calculation ROM (116R) of FIG. 11 and the current gain control signal 17 dB is the next gain control signal. The signal is output to the F / F 117, the output level becomes −10 dBm which is the convergence level, and the first AGC operation is completed. When the input level does not change, in the second AGC operation, the detected voltage value 2V of −10 dBm is converted into the output “10” of the true value / logarithmic value conversion ROM 114 through the same processing as in the first time. 11 outputs “7” at the intersection of “10” of the upper 5 bits (row) of the error calculation ROM (116R) and “7” of the current gain control signal, and holds it until the input level changes. The AGC operation is performed.

Japanese Patent Laid-Open No. 11-94928

  However, in the conventional AGC circuit based on the AGC circuit described in Patent Document 1, the first problem is that the variable amount of the variable gain amplifier 101 is 10 dB positively and negatively. The dynamic range of the amplifier 101 has a problem that when there is a change in the input level that needs to be changed to 25 dB full, at least three AGC operations are required until convergence, and the convergence speed is slow. .

  Further, as a second problem, when the variable amount of the variable gain amplifier 101 is increased in order to avoid the above problem, the resolution per 1 dB is lowered and is generated in the variable gain amplifier 101 to the detector 104. There is a problem that the setting accuracy is lowered due to an error in the convergence level due to hardware temperature fluctuations, an initial setting error of the reference voltage of the A / D converter 105, and a change in sensitivity when the input level to the detector 104 changes. .

  Therefore, the present invention has been made in view of the problems in the AGC circuit described above, and reduces the number of AGC convergence cycles to increase the convergence speed, and improves the AD resolution per 1 dB, resulting from hardware. An object of the present invention is to provide an AGC circuit capable of reducing errors.

  To achieve the above object, the present invention provides an AGC circuit for controlling the level of a received signal by a gain control signal, and an A / D converter that converts logarithmic data obtained by logarithmically compressing the received signal into digital data. And a gain control signal generating means for generating the gain control signal for canceling an error component between the logarithmic data digitally converted by the A / D converter and predetermined reference data, the dynamics of the A / D converter When the range is set to be narrower than the gain control range of the AGC circuit and there is an input having a level exceeding the dynamic range of the A / D converter, the A / D is forcibly applied in the next automatic gain control cycle. Control is performed so as to be within the dynamic range of the converter.

  According to the present invention, since the dynamic range of the A / D converter is set narrower than the gain control range of the AGC circuit, the AD resolution per 1 dB can be improved, and the setting is made by reducing the error caused by hardware. Accuracy is improved. Further, when there is an input having a level exceeding the dynamic range of the A / D converter, in the next automatic gain control cycle, control is performed so as to forcibly enter the dynamic range of the A / D converter. The convergence speed can be increased by reducing the number of control convergence cycles to a maximum of two.

  In the AGC circuit, the A / D converter samples logarithmic data within a predetermined period to convert it into digital data, averages the logarithmic data digitally converted by the A / D converter based on the number of sampling times, The gain control signal generation means may generate the gain control signal for canceling an error component between the averaged logarithmic data and the predetermined reference data.

Further, the gain control signal generation means includes a ROM that records a relational value between the signal level of the current received signal and the previous gain control signal, and has an input with a level exceeding the dynamic range of the A / D converter. In some cases, it may be configured to include a table that controls to force to enter the dynamic range of the A / D converter in the next automatic gain control cycle.

  Furthermore, the dynamic range of the A / D converter can be set to approximately 1/3 of the gain control range of the AGC circuit.

  As described above, according to the present invention, it is possible to increase the convergence speed by reducing the number of convergence cycles of automatic gain control, improve the AD resolution per 1 dB, and reduce errors caused by hardware. An AGC circuit can be provided.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In the present invention, a circuit configuration similar to the AGC circuit described in Patent Document 1 shown in FIG.

  First, the setting of each part in the AGC circuit according to the present invention will be described. A calculation formula that gives an error signal to be input to the ROM (116R) when there is an input exceeding the dynamic range (variable range in 1 dB step) of the A / D converter 105 and the dynamic range is shown below.

Calculation is performed when the maximum variable range of the variable gain amplifier 101 shown in FIG. 1 is X, the dynamic range of the A / D converter 105 (variable range in 1 dB step) is A1, and the dynamic range of the A / D converter 105 is exceeded. If the level difference data given to the ROM (116R) is A0,
A0 = 2X / 3, A1 = X / 3
If A1 and A0 are not divisible, they are rounded off.

  Next, the setting of each part using A0 and A1 obtained by the above formula will be described.

  FIG. 12 is a diagram showing the relationship between the output of the variable gain amplifier 101 and the output of the logarithmic compression amplifier 103, and the output of the logarithmic compression amplifier 103 and the output of the A / D converter 105. In the figure, the outputs of the variable gain amplifier 101 and the logarithmic compression amplifier 103 need to operate linearly in the level range from the convergence level −A1−1 dB to A1 + 1 dB. The logarithmic compression amplifier 103 is at least the A / D converter 105. It is necessary to output a voltage in the operating voltage range. Further, the A / D converter 105 uses a signal that does not carry even when there is an input exceeding the operating voltage range.

  FIG. 13 is a diagram comparing the conventional AGC circuit and the AGC circuit according to the present invention for the output of the A / D converter 105 to the data of the error calculation circuit 116. In the figure, the calculation method of the logarithmic value / true value conversion circuit 106 and the true value / logarithmic value conversion circuit 114 is the same as that in the case where the prior art is reviewed. How to take is different. That is, in the prior art, the data of the true value / logarithmic value conversion circuit 114 is required for the number of steps of the convergence level + positive / negative variable range, but in the present invention, the variable range −A1 to + A1 ( A total of ± A1 + 3 steps of data including the convergence level “0” and the signals + A1 and + A1 when the dynamic range is exceeded is required.

  The output data of the true value / logarithmic value conversion circuit 114 is handled as level difference data (not input to the actual ROM), and is input as an address of the error calculation circuit 116 together with the current gain control signal. As data, the set value of the gain control signal to be set next is output. For example, when the level difference data is “0”, the same value as that of the current gain control signal is set as the gain control signal to be set next, and when the level difference data is “−10”, A value is given for all the level difference data so as to output a value obtained by subtracting 10 dB from the gain control signal.

  In the prior art, from the minimum value to the maximum value of the output data of the true value / logarithmic value conversion circuit 114, it is handled as level difference data that can be changed in 1 dB steps around the convergence level, and the data of the error calculation circuit 116 is output. Was. The output data of the true value / logarithmic value conversion circuit 114 in the present invention is treated as level difference data of “−A0” in the case of the minimum value and “+ A0” in the case of the maximum value, and the current set value − (− A0), The remaining value is treated as level difference data that can be changed in 1 dB steps around the convergence level so that the current set value is-(+ A0), and the data of the error calculation circuit 116 is output.

  Next, operations that characterize the AGC circuit according to the present invention will be described in detail with reference to the drawings.

  FIG. 14 shows the concept of the operation in the prior art and the operation in the present invention. In the figure, each cycle diagram represents the difference between the output level and the convergence level of the variable gain amplifier 101, and ± X indicates the maximum variable range of the variable gain amplifier 101 (the actual variable gain amplifier in this AGC circuit). The gain control of 101 is only in the positive direction of 0 to X, but in this figure, since the current gain control signal is not taken into account, both directions are positive and negative).

  The −side variable range in the prior art, the + side variable range, and −A1 and + A1 in the present invention indicate ranges in which the AGC circuit can be changed in 1 dB steps, and the output level of the variable gain amplifier 101 is within this range. If so, it is possible to reach the convergence level by a single AGC operation using the ROM table of the error calculation circuit 116.

  In the prior art, when there is a level difference exceeding the −side variable range and the + side variable range, it can be changed by the maximum value of the gain control signal that can be changed at a time in the first AGC operation. In the second AGC cycle, since the level difference is reduced by the amount changed by the first AGC cycle, the maximum value of the first variable range can be regarded as 0, and the second and third times and the convergence cycle It is possible to reach the convergence level by overlapping.

  In the case of the AGC cycle in the present invention, if there is a level difference exceeding -A1, + A1, all are detected as + A0, -A0. Since the values are determined so that ± A1 is ± X / 3 and ± A0 is ± 2X / 3, if the level difference is in the range of + A1 to + A0 in the first AGC cycle, the second AGC In the cycle, when the level difference is in the range of -A1 to 0, and in the range of + A0 to X in the first AGC cycle, the second AGC cycle is in the range of 0 to + A1, so that the maximum 2 It is possible to converge in a single time.

  In the above embodiment, the case where the logarithmic value / true value conversion circuit 106, the true value / logarithmic value conversion circuit 114, and the integration / average circuit 7 are used as shown in FIG. 1 has been described. Instead of these, the output of the A / D converter 105 can be directly input to the error calculation circuit 116, and the gain control signal can be switched at the sampling timing of the A / D converter 105.

  The variable gain amplifier 101 may be an analog variable gain amplifier or an attenuator, and can be controlled with an arbitrary variable width. Further, it is possible to control by an arbitrary setting step such as 0.5 dB or 2 dB instead of the 1 dB step.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. Also in this embodiment, the same circuit configuration as that of the AGC circuit described in Patent Document 1 shown in FIG. 1 is adopted, and each part is set as follows.

  As in the case where the prior art is reviewed, it is assumed that the dynamic range of the variable gain amplifier 101 converges at 25 dB and the output signal level of the variable gain amplifier 101 is −10 dBm, and the output of the logarithmic compression amplifier 103 at the convergence level is 2V. The A / D converter 105 has an operating voltage range of 1.5 to 2.5 V and an output bit number of 8 bits. The output does not carry even when the operating voltage range is exceeded (even if there is an input of 2.5 V or more, the output is In contrast, the output is 0 even when the input is 1.5 V or less.

  According to the calculation formula shown in the embodiment of the present invention, since the maximum variable range X of the variable gain amplifier 101 is 25 dB, the dynamic range (variable range in 1 dB step) A0 of the A / D converter 105 is 8 dB, dynamic The level difference data A1 when the range is exceeded is 17 dB. Further, since the number of steps for changing 1 dB necessary for the AGC operation is −A1 to + A1 and ± A0, a total of 19 steps are required.

  FIG. 15 is a diagram showing the relationship between the output of the variable gain amplifier 101 and the output of the logarithmic compression amplifier 103, and the output of the logarithmic compression amplifier 103 and the output of the A / D converter 105. In the figure, the outputs of the variable gain amplifier 101 and the logarithmic compression amplifier 103 are linearly operating up to about 0 dBm. The output of the A / D converter 105 needs to be able to express levels of 1 to A1 and A0 in positive and negative directions with the output value 127 as the center of the convergence level. Accordingly, the resolution per 1 dB of the A / D converter 105 divides the input voltage range 1V by 18 (the number of steps required for the AGC operation is 19 steps, but the output value 127 of the A / D converter 105 is the convergence level. Therefore, the steps at both ends are halved to 18), so that 55.5 mV / dB.

  FIG. 16 is a diagram showing the relationship between the output voltage of the A / D converter 105 and the output of the true value / logarithmic value conversion ROM 114. Since the input level 2V of the A / D converter 105 is centered at the convergence level and changes at 55.5 mV / dB, the relationship between the input voltage of the A / D converter 105 and the true value / logarithmic value conversion ROM 114 is shown in FIG. It becomes like this. 15 and 16, when the output of the variable gain amplifier 101 is −1 dBm or more and −19 dBm or less, the relative values to the convergence level are +9 dB or more and −9 dB or less, respectively. In the AGC circuit of the present invention, these values are used. Are considered as level difference data meaning + A0 (= + 17 dB) and -A0 (= -17 dB).

17 and 18 are diagrams showing ROM data set values of the logarithmic value / true value conversion circuit 106 and the true value / logarithmic value conversion circuit 114. FIG. Since the output of the true value / logarithmic value conversion circuit 114 requires data of a total of 19 steps and is the maximum value 18 of values from 0 to 18, as shown in FIG. 106 data is
Y = 10Λ (18 * ((X + 1) / 256) / 10) = 10Λ ((X + 1) × 0.00703)
Set to be. Here, since the address is X, the data is Y, and the ROM data is an integer, the obtained Y is rounded off. The contents of the true value / logarithmic value conversion circuit 114 are as shown in FIG. 18 because the true value that can be output from the true value / logarithmic value conversion circuit 114 is converted into logarithm.

  FIG. 19 is a diagram showing the contents of the ROM (116R) of the error calculation circuit 116. The output values 1 to 17 of the true value / logarithmic value conversion circuit 114 in the figure are ranges representing the error data -A1 to + A1 (= -8 to +8), and are changed in 1 dB steps as in the prior art. ROM data that can be stored. The output values 0 and 18 of the true value / logarithmic value conversion circuit 114 are set so that the gain control signal to be output becomes data when there is a level difference of −A0 and + A0 (−17 and +17). For example, if the current gain control signal is 3 dB and the output of the true value / logarithmic value conversion circuit 114 is 18, it recognizes that the level difference is +17 dB, and outputs “20” with the gain reduced by 17 dB. Set the data as follows.

  Next, the operation of the AGC circuit having the above configuration will be described. In the following description, a case where the current gain control signal is 17 dB will be described.

  When the output signal level of the variable gain amplifier 101 can be changed in 1 dB steps (-A1 to + A1), for example, when the output signal level of the variable gain amplifier 101 is -18 dBm, in FIG. The output voltage of the amplifier 103 becomes 1.555V, and is quantized by the A / D converter 105 to become the output value “12”. From FIG. 16, the output value “12” of the A / D converter 105 is converted into “1” which means −A1 (= −8 dB) at the output of the true value / logarithmic value conversion ROM 114 through the process of integration and averaging. .

  The converted data is input to “1” in the upper 5 bits (row) of the error calculation ROM (114R) of FIG. 19, and “9” indicated by the intersection with the current gain control signal (column) 17 dB is selected. And output to the F / F 117 as the next gain control signal. As a result, the output level increases by 17−9 = 8 dB gain and becomes −10 dBm, which is the convergence level, and the first AGC operation is completed.

  Next, a case where the output signal level of the variable gain amplifier 101 is outside the range that can be changed in 1 dB steps (greater than -A1 to + A1), for example, the case where the output signal level of the variable gain amplifier 101 is -25 dBm will be described. To do.

  In FIG. 15, since the output voltage of the logarithmic compression amplifier 103 is −19 dBm or less, a voltage of 1.5 V or less is output. Since the A / D converter 105 has an input signal of 1.5 V or less, the quantum value is limited and output by the minimum value “0”. From FIG. 16, the output value “0” of the A / D converter 105 is converted into “0”, which means −A 0, through the integration / average process and the output of the true value / logarithmic value conversion ROM 114.

  As the converted data, “0” given at the intersection of the upper 5 bits (row) of the error calculation ROM (114R) of FIG. 19 and the current gain control signal (column) 17 dB is selected. Then, it is output to the F / F 117 as the next gain control signal. As a result, in the first AGC operation, the output level is increased by 17−0 = 17 dB, and the output level of the variable gain amplifier 101 is −25 − (− 17) = − 8 dBm. In the second AGC operation, the gain control signal is 0 dB and the output is -8 dBm. Therefore, the gain control signal is changed from 0 dB to 2 dB through the same operation as the first operation because it is 2 dB higher than the target convergence level. To -10 dBm.

  As described above, according to this embodiment, since the dynamic range of the A / D converter 105 is set to be approximately 1/3 of the entire variable region of the AGC circuit, the AD resolution per 1 dB can be improved. This reduces errors caused by hardware and improves setting accuracy.

  In addition, when the A / D converter 105 has an input with a level exceeding the dynamic range, the A / D converter 105 has a function of detecting it and outputting a specific output. In the arithmetic ROM (116R), the A / D converter 105 If there is a specific output detected, a table that forcibly converts it to a level that falls within the dynamic range of the A / D converter 105 in the next AGC cycle has been added. The convergence speed can be increased by reducing the number of AGC convergence cycles.

  The above two effects have contradictory properties. Generally, if the resolution of the A / D converter 105 is improved to reduce errors caused by hardware, the number of convergence increases, and it takes a long time to converge. On the contrary, if the number of times of convergence is reduced and the time until the convergence is shortened, the resolution of the A / D converter 105 is lowered. In the present invention, based on the conventional technique with a resolution of 50 mV / dB for the A / D converter with 3 convergence times, the resolution for the A / D converter can be 55 mV / dB with 2 convergence times. The effect could be obtained at the same time.

  FIG. 20 compares the resolution of the A / D converter 105 according to the prior art and the present invention with the convergence cycle fixed to two. From the figure, as the dynamic range of the variable gain amplifier 101 increases, the effect of the present invention becomes more significant, and the resolution of the A / D converter 105 can be improved by about 50% at the maximum. On the other hand, FIG. 21 shows the number of convergence cycles when the conventional technique is set to the resolution of the A / D converter 105 of the present invention. From the figure, when the dynamic range of the variable gain amplifier 101 is 6 dB or more, three convergence cycles are necessarily required, so that the convergence speed of the present invention is improved by 33% compared to the prior art. I understand that.

It is a block diagram of a conventional AGC circuit according to the present invention. It is a timing diagram for demonstrating operation | movement of the conventional AGC circuit. It is a figure which shows the characteristic of the logarithmic compression amplifier when the output value of the variable gain amplifier of the conventional AGC circuit is 40 dB. It is a figure which shows the example of data of ROM used for the logarithm value / true value conversion circuit of the conventional AGC circuit. It is a figure which shows the example of data of ROM used for the true value / logarithm conversion circuit of the conventional AGC circuit. It is a figure which shows the example of data of ROM used for the error calculating circuit of the conventional AGC circuit. It is the figure which showed the relationship between the output of a variable gain amplifier and a logarithmic compression amplifier when the setting of each part was reviewed in the conventional AGC circuit, and the output of a logarithmic compression amplifier, and the output of an A / D converter. It is a figure which shows the example of data of ROM used for the logarithm value / true value conversion circuit at the time of reviewing the setting of each part in the conventional AGC circuit. It is a figure which shows the example of data of ROM used for the true value / logarithm value conversion circuit at the time of reviewing the setting of each part in the conventional AGC circuit. It is the figure which showed the relationship between the input voltage of an A / D converter when the setting of each part is reviewed in the conventional AGC circuit, and the output of a true value / logarithmic value conversion ROM. It is a figure which shows the data example of ROM used for the error calculating circuit at the time of reviewing the setting of each part in the conventional AGC circuit. It is the figure which showed the relationship between the output of a variable gain amplifier in this invention, the output of a logarithmic compression amplifier, and the output of a logarithmic compression amplifier, and the output of an A / D converter. It is the figure which compared the conventional AGC circuit and the AGC circuit concerning this invention about the data of the output of an A / D converter-an error calculating circuit. It is a conceptual diagram of operation | movement of the AGC circuit concerning the past and this invention. It is the figure which showed the relationship between the output of a variable gain amplifier and a logarithmic compression amplifier at the time of reviewing the setting of each part in the AGC circuit in the Example of this invention, and the output of a logarithmic compression amplifier, and the output of an A / D converter. It is the figure which showed the relationship between the output value of an A / D converter when the setting of each part was reviewed in the AGC circuit in the Example of this invention, and the output of a true value / logarithm conversion ROM. It is a figure which shows the example of data of ROM used for the logarithm value / true value conversion circuit in the Example of this invention. It is a figure which shows the example of data of ROM used for the true value / logarithm value conversion circuit in the Example of this invention. It is a figure which shows the example of data of ROM used for the error calculating circuit in the Example of this invention. It is the graph which compared the A / D resolution of the conventional AGC circuit when the frequency | count of convergence is fixed to 2, and the AGC circuit concerning this invention. It is a graph which shows the frequency | count of convergence of a prior art at the time of uniting the A / D resolution of the conventional AGC circuit with the A / D resolution in this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Signal output part 101 Variable gain amplifier 102 Coupler 103 Logarithmic compression amplifier 104 Detector 105 A / D converter 106 Logarithmic value / true value conversion circuit 107 Adder 108 Full adder 109 Flip-flop circuit (F / F)
110 Counter 112 Divider 114 True / Logarithmic Value Conversion Circuit 116 Error Calculation Circuit 117 Flip-Flop Circuit (F / F)

Claims (4)

An automatic gain control circuit for controlling the level of a received signal by a gain control signal,
An analog / digital conversion circuit that converts logarithmic data obtained by logarithmically compressing the received signal into digital data;
Gain control signal generating means for generating the gain control signal for canceling an error component between logarithmic data digitally converted by the analog / digital conversion circuit and predetermined reference data;
A dynamic range of the analog / digital conversion circuit is set narrower than a gain control range of the automatic gain control circuit;
When there is an input having a level exceeding the dynamic range of the analog / digital conversion circuit, control is performed so as to forcibly enter the dynamic range of the analog / digital conversion circuit in the next automatic gain control cycle. An automatic gain control circuit. The analog / digital conversion circuit samples logarithmic data within a predetermined period and converts it into digital data,
Logarithm data digitally converted by the analog / digital conversion circuit is averaged based on the number of sampling times,
2. The automatic gain control circuit according to claim 1, wherein the gain control signal generating means generates the gain control signal for canceling an error component between the averaged logarithmic data and the predetermined reference data. .   The gain control signal generating means includes a ROM that records a relational value between the signal level of the current received signal and the previous gain control signal, and there is an input having a level exceeding the dynamic range of the analog / digital conversion circuit. 3. The automatic gain control circuit according to claim 1, further comprising a table for controlling to force the dynamic range of the analog / digital conversion circuit to enter in a next automatic gain control cycle.   4. The automatic gain control circuit according to claim 1, wherein a dynamic range of the analog / digital conversion circuit is set to approximately 1/3 of a gain control range of the automatic gain control circuit.