JP3951992B2 - Defective pixel correction circuit - Google Patents

Description

  The present invention relates to a defective pixel correction circuit that corrects pixel defects existing in a solid-state image sensor in an image pickup apparatus using a solid-state image sensor such as a CCD.

  In recent years, solid-state imaging devices, especially CCD (Charge Coupled Device) type imaging devices (hereinafter simply referred to as “CCD”) have come to be most widely used as imaging devices, and are used for broadcasting, commercial use, and consumer use. In many types of video cameras, an imaging method called a three-plate type using three CCDs is often used. In this method, an optical signal incident from a lens is separated into optical signals of three primary colors of R, G, and B by a color separation prism, and each is converted into an electric signal by a solid-state imaging device.

  In many cases, a defective pixel is generated in a CCD due to a manufacturing process or the like, and it is difficult to obtain a CCD having no defective pixel at a sufficient yield at present. For this reason, usually, a CCD including a defective pixel is often used as an imaging device. In this case, an output signal corresponding to the defective pixel is corrected by a defective pixel correction circuit.

As conventional defect compensation device are those disclosed in, for example, Japanese Unexamined Patent Publication No. 9-284783, shows the configuration in FIG. In FIG. 7 , 1a, 1b, and 1c are video signal input terminals, 2a, 2b, and 2c are average value calculation circuits, 71 is a channel switching circuit, 4 is a selection circuit, 72 and 73 are subtractors, 74 is a selection circuit, and 8 is a selection circuit. An adder, 9 is a clip circuit, 10 is an output switching circuit, 75 is a control circuit, and 20a, 20b, and 20c are output terminals. FIG. 2 shows the configuration of the average value calculation circuits 2a, 2b, and 2c. 51 and 52 are delay elements, 53 is an adder, and 54 is a gain circuit.

  The operation of the conventional defective pixel correction circuit configured as described above will be described below.

  In this conventional defect correction apparatus, when there is defect data (hereinafter referred to as “defect channel”) in a certain color channel, another color channel without defect data (hereinafter referred to as “correction channel”) is input. Correction data is generated using the signal, and the defect data is replaced with the correction data.

In FIG. 7 , video signal input terminals 1a, 1b, and 1c are input terminals of a defective pixel correction circuit, and a digital signal obtained by converting a CCD analog output signal corresponding to R, G, and B primary colors into a digital value is input. The Here, since the signal data is generally output from the CCD for each pixel, this digital signal is usually discretized at a period corresponding to one pixel.

  The R, G, B input signals are input to the average value calculation circuits 2a, 2b, 2c, respectively. In the average value calculation circuit shown in FIG. 2, the delay element 51 delays the input signal Xin by one data. The output signal of the delay element 51 is output as the center pixel signal Xcnt.

  The delay element 52 further delays the output signal of the delay element 51 by one data. The adder 53 adds the input signal Xin and the output signal of the delay element 52, and the gain circuit 54 multiplies the gain by 1/2 by bit shift or the like. In other words, the output of the gain circuit 54 is a signal obtained by adding and averaging the previous pixel and the subsequent pixel with respect to the central pixel signal Xcnt, and outputs this as an interpolation average signal Xav. Note that the delay elements 51 and 52 described above can be configured by, for example, D flip-flops.

  Among the output signals of the average value calculation circuits 2a, 2b, and 2c, the center pixel signals Rcnt, Gcnt, and Bcnt are input to the selection circuit 4 and the output switching circuit 10. Interpolated average signals Rav, Gav, and Bav are input to the channel switching circuit 71.

  Here, a channel signal C input from an external defect detection means (not shown) is input to the control circuit 75 to generate a channel signal ch1 designating the defective channel, and a channel indicating the other two channels. Signals chJ and chL are generated. These channel signals chJ, ch1, and chL are input to the channel switching circuit 71.

The configuration of the channel switching circuit 71, shown in FIG. In FIG. 8 , reference numerals 81, 82, and 83 denote selectors, and three signals Rav, Gav, and Bav are input to each selector. Each selector selects a signal of a color channel specified by the channel signal chJ, ch1, or chL, and outputs it as signals SJ, SK, SL. Here, as described above, ch1 is a channel signal indicating a defective channel, and signal SK is a signal of a defective channel corresponding thereto. Further, chJ and chL are two channel signals other than the defective channel, and signals SJ and SL correspond to these, respectively. The subtracter 72 in FIG. 7 generates the difference signal DJ by the operation “DJ = SK−SJ”. The subtractor 73 generates the difference signal DL by the calculation of “DL = SK−SL”.

  The difference signals DJ and DL are input to the control circuit 75, and a control signal CD that specifies the smaller absolute value is output. That is, 0 is designated as the control signal CD when | DJ | <| DL |, and 0 is designated as the control signal CD when | DJ |> | DL |. Further, as the channel signal ch2, the channel signal chJ is selected when CD = 0, and the channel signal chL is selected and output when CD = 1. The selection circuit 74 outputs the smaller one of the difference signals DJ and DL as DM based on the control signal CD.

  The selection circuit 4 outputs a correction channel signal Fcnt based on the channel signal ch2, and the adder 8 adds it to the difference signal DM. Further, the clip circuit 9 outputs the clipped data within the video signal level as the correction data Dc.

  The output switching circuit 10 selects and outputs the correction data Dc to the channel having the defective pixel among the central pixel signals Rcnt, Gcnt, Bcnt according to the channel signal ch1 designating the defective channel. Note that the signals of the other two channels having no defective pixel are output as they are.

This conventional defective pixel correction circuit, Figure 7 and its detailed operation will be described with reference to FIG. As shown in FIG. 9 , it is assumed that signal data R (i), G (i), and B (i) are input from input terminals 1a, 1b, and 1c, but G (i) is defective data.

First, at time (i-1), an input terminal 1a of FIG. 9, 1b, to 1c, the signal R (i-1), G (i-1), B (i-1) is input. Next, at time i, signals R (i), G (i), and B (i) are input to the input terminals 1a, 1b, and 1c, respectively, and outputs Rcnt, Gcnt, As Bcnt, R (i-1), G (i-1), and B (i-1), which are signals one pixel before, are output. Since there is no defective pixel at the position corresponding to (i-1), the signals R (i-1), G (i-1), and B (i-1) are output from the output switching circuit 10 as they are. The

Next, the operation at time (i + 1) will be described. At time (i + 1), signals R (i + 1), G (i + 1), and B (i + 1) are input to the input terminals 1a, 1b, and 1c, respectively, and the signal R (i) is input to the output switching circuit 10 and the selection circuit 4. , G (i), B (i) are input. In the average value calculation circuits 2a, 2b, and 2c, the interpolation average signals RAV, GAV, and BAV represented by the formula (Equation 1) are calculated and input to the channel switching circuit 71.
Rav = 1/2 * {R (i + 1) + R (i-1)}
Gav = 1/2 * {G (i + 1) + G (i-1)}
Bav = 1/2 * {B (i + 1) + B (i-1)} (Equation 1)
On the other hand, at the time (i + 1), the control circuit 75 inputs the G channel code corresponding to the defect data G (i) as the channel signal C as described above. As a result, a channel signal corresponding to G is output as the channel signal ch1. In addition, channel signals corresponding to R and B are output as channel signals chJ and chL, respectively. That is, the channel switching circuit 71 outputs SJ = Rav, SK = Gav, and SL = Bav.

Here, the difference signals DJ and DL are respectively generated as shown by the equation (Equation 2) and input to the selection circuit 74 and the control circuit 75.
DJ = SK-SJ = Gav-Rav
DL = SK-SL = Gav-Bav ―――― (Equation 2)
As can be seen from FIG. 9 , the following equation (Equation 3) holds.
DL = Gav-Bav <DJ = Gav-Rav ―――― (Equation 3)
Therefore, the control circuit 75 outputs 1 that designates the L side as the control signal CD, and the selection circuit 74 outputs the difference signal DM represented by (Equation 4).
DM = Gav-Bav
= 1/2 * {G (i + 1) + G (i-1)}-1/2 * {B (i + 1) + B (i-1)}
―――― (Equation 4)
Further, the selection circuit 4 outputs a signal B (i) based on the channel signal ch2, and the adder 8 generates a signal G ′ (i) represented by the following equation (Equation 5).
G ′ (i) = B (i) + DM = B (i) + Gav−Bav
= B (i) + 1/2 * {G (i + 1) + G (i-1)}-1/2 * {B (i + 1) + B (i-1)} (Equation 5)
Thus, the correction data Dc is output from the clip circuit 9. In the output switching circuit 10, the defect data G (i) is output after being replaced with the correction data represented by (Equation 5). That is, as shown in FIG. 9 (a), by the G channel of the defective pixel data G (i) is replaced by G '(i), even highly accurate defect correction in an image including a high frequency component can be carried out .
Japanese Patent Laid-Open No. 9-284783 (page 7-9)

  However, the above technique has a problem that it is easily affected by noise. Since the output signal level of the normal B signal is about 1/3 of that of the G signal, the S / N ratio is about 9 dB worse. In the above-described example of defective pixel correction, since the G signal is corrected using the information of the B signal, the noise component of the B signal often appears as a correction result of the G signal. That is, the defect-corrected G signal may show flickering and weakness due to the noise of the B signal.

To avoid the influence of noise may have to use B signals but, G in the example of FIG. 9, when the G signal of the defective pixel is corrected by the R signal, the correction results are shown in Fig. 9 (b) "(I), the high-frequency component of the defective pixel portion is extremely reduced, and there is a possibility of coloring.

Further, in the example of FIG. 9 (c), as the signal level, the largest is the R signal, G signal is most small, and it is when there is a defective pixel G signal. In this case, if the G signal is corrected with the R signal in order to avoid the influence of noise, a correction result protruding like G ″ (i) shown in the figure is obtained. That is, in an actual image, In the reddish image, the correction part appears as a white bright spot, which is very noticeable.

  The present invention solves the above-described conventional problems. In the defective pixel correction in the imaging apparatus, even when the video signal pattern around the defective data has a high frequency, the defective data is corrected correctly and the influence of noise is reduced. An object of the present invention is to provide a defective pixel correction circuit that is difficult to receive.

  In order to solve this problem, the present invention corrects defect data by changing the gain of a high-frequency component to be corrected according to the signal level of a color channel having defect data and the signal level of a reference color channel for generating correction data. To do.

In other words, the defective pixel correction circuit of the present invention receives pixel signals of a plurality of channels output from a plurality of channels of solid-state imaging devices each outputting a pixel signal in time series, and has pixel defects existing in the solid-state imaging device. A defective pixel correction circuit that corrects the pixel signal and is adjacent to the pixel signal of the defective channel having a pixel defect when focusing on the pixel signal at the position having the pixel defect among the pixel signals of the plurality of channels input in time series. A first interpolation average signal Zav, which is an average value of pixel signals to be corrected, is generated using Fcnt as the pixel signal of the correction channel and an average value of pixel signals adjacent to the pixel signal of the correction channel used for defective pixel correction. A signal Fdef which is a difference from a certain second interpolation average signal Fav is generated, and the first interpolation average signal Zav and the second interpolation average signal Fav are Generating a correction factor Kdef as, which is characterized by replacing the pixel signal of the defective channel correction signal obtained by Zav + Fdef × Kdef, high-frequency component of the pixel signal of the correction channel by this arrangement, reference Since the defective pixel correction is performed by changing the correction coefficient of the high-frequency signal corresponding to the above , that is, the gain, the defect data can be used even when the video signal pattern around the defect data is high frequency or high saturation. Can be corrected correctly.

  As described above, according to the present invention, it is possible to perform defective pixel correction with high accuracy even in an image with many high-frequency components, and it is possible to perform defective pixel correction with little correction error even in an image with high saturation. .

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a defective pixel correction circuit according to Embodiment 1 of the present invention.

  In FIG. 1, 1a, 1b, and 1c are video signal input terminals, 2a, 2b, and 2c are average value calculation circuits, 3 is a channel switching circuit, 4 is a selection circuit, 5 is a coefficient determination circuit, 6 is a subtractor, and 7 is A multiplier, 8 is an adder, 9 is a clip circuit, 10 is an output switching circuit, 11 is a control circuit, and 20a, 20b, and 20c are output terminals.

  The operation of the signal processing circuit according to the first embodiment configured as described above will be described below. In addition, about the same component as background art, the same code | symbol is used and description is abbreviate | omitted.

  In FIG. 1, video signal input terminals 1a, 1b and 1c are input terminals of a defective pixel correction circuit, and a digital signal obtained by converting a CCD analog output signal corresponding to the three primary colors R, G and B into a digital value is input. The Here, since the signal data is generally output from the CCD for each pixel, this digital signal is usually discretized at a period corresponding to one pixel.

  R, G, and B input signals are respectively input to average value calculation circuits 2a, 2b, and 2c having the configuration shown in FIG. Among the output signals of the average value calculation circuits 2a, 2b, and 2c, the center pixel signals Rcnt, Gcnt, and Bcnt are input to the selection circuit 4 and the output switching circuit 10. Interpolated average signals Rav, Gav, and Bav are input to the channel switching circuit 3. Here, a channel signal C input from an external defect detection means (not shown) is input to the control circuit 11 to generate a channel signal ch1 designating the defective channel, and to the channel switching circuit 3 and the output switching circuit 10. Entered. Further, a correction channel signal ch2 used for correcting the defective pixel is generated and input to the channel switching circuit 3 and the selection circuit 4.

The configuration of the channel switching circuit 3 is shown in FIG. In FIG. 3, reference numerals 61 and 62 denote selectors, and three signals Rav, Gav, and Bav are input to each selector. The selector 61 selects a color channel signal designated by the channel signal ch2 and outputs it as a signal Fav.
The selector 62 selects a color channel signal designated by the channel signal ch1 and outputs it as a signal Zav.

  Here, as described above, ch1 is a channel signal indicating a defective channel to be corrected, and signal Zav is a signal of a defective channel corresponding to this. Further, ch2 is a correction channel signal to be referred to for correcting the defective channel, and the signal Fav corresponds to this. The interpolated average signal Fav is input to the coefficient determining circuit 5 and the subtracter 6, and the interpolated average signal Zav is input to the coefficient determining circuit 5 and the adder 8. The coefficient determination circuit 5 calculates a correction coefficient Kdef from the interpolation average signal Zav of the defective channel and the interpolation average signal Fav of the correction channel, and outputs it to the multiplier 7. Here, the configuration of the coefficient determination circuit 5 is assumed to comprise a divider 66 as shown in FIG.

  The selection circuit 4 outputs the center pixel signal Fcnt of the correction channel based on the channel signal ch2, and the subtracter 6 subtracts it from the interpolation average signal Fav. The subtraction result Fdef is multiplied by the coefficient Kdef in the multiplier 7 and further added to the interpolation average signal Zav of the defective channel in the adder 8.

  Further, the clipping circuit 9 performs a clipping process so that the correction signal does not exceed the upper limit value and the lower limit value, and is output as correction data Dc. The output switching circuit 10 selects and outputs the correction data Dc to the channel having the defective pixel among the central pixel signals Rcnt, Gcnt, and Bcnt in accordance with the channel signal ch1 designating the defective channel. Note that the signals of the other two channels having no defective pixel are output as they are.

  The operation of the embodiment configured as described above will be described with reference to FIGS. Assume that signal data R (i), G (i), and B (i) shown in FIG. 5 are input from the input terminals 1a, 1b, and 1c, and G (i) is defective data.

  First, at time (i-1), signals R (i-1), G (i-1), and B (i-1) are input to the input terminals 1a, 1b, and 1c in FIG. Next, at time i, signals R (i), G (i), and B (i) are input to the input terminals 1a, 1b, and 1c, respectively, and outputs Rcnt, Gcnt, As Bcnt, R (i-1), G (i-1), and B (i-1), which are signals one pixel before, are output. Since there is no defective pixel at the position corresponding to (i-1), the signals R (i-1), G (i-1), and B (i-1) are output from the output switching circuit 10 as they are. The

Next, the operation at time (i + 1) will be described. At time (i + 1), signals R (i + 1), G (i + 1), and B (i + 1) are input to the input terminals 1a, 1b, and 1c, respectively, and the signal R (i) is input to the output switching circuit 10 and the selection circuit 4. , G (i), B (i) are input. In the average value calculation circuits 2a, 2b, and 2c, interpolation average signals Rav, Gav, and Bav represented by the equation (Equation 6) are calculated, and these are input to the channel switching circuit 3.
Rav = 1/2 * {R (i + 1) + R (i-1)}
Gav = 1/2 * {G (i + 1) + G (i-1)}
Bav = 1/2 * {B (i + 1) + B (i-1)} (Equation 6)
On the other hand, at the time (i + 1), the control circuit 11 receives the G channel code corresponding to the defect data G (i) as the channel signal C as described above. As a result, a channel signal corresponding to G is output as the channel signal ch1. Further, a channel signal corresponding to R is output as the channel signal ch2. That is, the channel switching circuit 3 outputs Fav = Rav and Zav = Gav.

Next, the coefficient determination circuit 5 calculates the correction coefficient Kdef by the following equation (Equation 7) and outputs it to the multiplier 7.
Kdef = Zav / Fav = Gav / Rav
= [1/2 * {G (i + 1) + G (i-1)}] / [1/2 * {R (i + 1) + R (i-1)}] ――――― (Equation 7)
The selection circuit 4 outputs a signal R (i) based on the channel signal ch2, and the adder 8 generates a signal G ′ (i) represented by the following equation (Equation 8).
G ′ (i) = Zav + Kdef × (Fcnt−Fav)
= Gav + Gav / Rav × (R (i) −Rav) (Equation 8)
Thus, the correction data Dc is output from the clip circuit 9. In the output switching circuit 10, the defect data G (i) is output after being replaced with the correction data represented by (Equation 8).

  Here, FIG. 5A and FIG. 5B show operations when there is a large difference between the signal levels of the G channel having defect data and the R channel used as a reference for defect correction.

  In FIG. 5A, the signal level of the R channel used as a reference for defect correction is small, but the defect corrected G channel has a large amplitude as a high frequency component. In FIG. 5B, the signal level of the R channel used as a reference for defect correction is large, but the high-frequency component is suppressed small in the defect corrected G channel.

Figure 9 (b) (c) in comparison to clear and, R in each pixel, G, the ratio of the signal level of B, ie the hue does not change significantly at 3 adjacent pixels. This is close to the nature of the actual image, and the correction error due to defect correction is small.

  That is, even in an image having a high saturation and a high frequency component, highly accurate defect correction can be performed according to the present embodiment.

The coefficient determination circuit 5 may be configured by a divider 66 and a multiplier 67 as shown in FIG. 6, and may be multiplied by the coefficient K1. In this case, the calculation result Kdef of the coefficient determination circuit 5 is as shown in (Equation 9).
Kdef = K1 × Zav / Fav (Equation 9)

  The defective pixel correction circuit according to the present invention is useful as defective pixel correction in a device that handles a video signal, and is particularly suitable for pixel defect correction in an imaging apparatus using a solid-state imaging device.

1 is a block diagram showing a configuration of a defective pixel correction circuit according to Embodiment 1 of the present invention. The figure which shows the structure of the average value calculation circuit by Embodiment 1 of this invention. The figure which shows the structure of the channel switching circuit by Embodiment 1 of this invention. The figure which shows the structure of the coefficient determination circuit by Embodiment 1 of this invention. The figure which shows operation | movement of the defective pixel correction circuit by Embodiment 1 of this invention. The figure which shows the structure of the coefficient determination circuit by Embodiment 1 of this invention. The block diagram which shows the structure of the signal processing circuit of the conventional defective pixel correction circuit A block diagram showing the configuration of a channel switching circuit of a conventional defective pixel correction circuit. Figure The figure which shows operation | movement of the defective pixel correction circuit of the conventional defective pixel correction circuit

Explanation of symbols

1a, 1b, 1c Video signal input terminals 2a, 2b, 2c Average value calculation circuit 3 Channel switching circuit 4 Selection circuit 5 Coefficient determination circuit
6 subtractor 7 multipliers 8 adder 9 clipping circuit 10 output switching circuit 11 control circuit 20a, 20b, 20c output terminals 51 and 52 delay elements 53 adder 54 gain circuits 61 and 62 the selector 66 divider 67 multipliers
7 1 Channel switching circuit 72, 73 Subtractor 74 Selection circuit 75 Control circuit 81, 82, 83 Selector

Claims (5)

A defective pixel correction circuit that receives pixel signals of a plurality of channels output from a plurality of channels of solid-state imaging devices each outputting a pixel signal in time series, and corrects pixel defects existing in the solid-state imaging device,
When focusing on pixel signals at positions having pixel defects among the plurality of channels of pixel signals input in time series ,
Generating a first interpolated average signal Zav that is an average value of pixel signals adjacent to pixel signals of a defective channel having pixel defects ;
A high-frequency signal Fdef that is a difference between a pixel signal Fcnt of a correction channel used for defective pixel correction and a second interpolation average signal Fav that is an average value of pixel signals adjacent to the pixel signal of the correction channel is generated. ,
Generating a correction coefficient Kd ef as a ratio of the first interpolation average signal Zav and the second interpolation average signal Fav ;
Zav + Fdef × Kdef
A defective pixel correction circuit, wherein the pixel signal of the defective channel is replaced with a correction signal obtained in (1 ). And x (i), y (i ) when the value of the pixel signal and the pixel signal of the correction channel of the defective channel in time i, respectively,
It said first interpolation average signal Zav and the high frequency signal Fdef is,
Zav = {x (i−1) + x (i + 1)} / 2, Fdef = y (i) − {y (i−1) + y (i + 1)} / 2
Defective pixel correction circuit according to claim 1, characterized in that. And x (i), y (i ) when the value of the pixel signal and the pixel signal of the correction channel of the defective channel in time i, respectively,
It said first interpolation average signal Zav and said second interpolated average signal Fav is,
Zav = {x (i−1) + x (i + 1)} / 2, Fav = {y (i−1) + y (i + 1)} / 2
The defective pixel correction circuit according to claim 1, wherein: A defective pixel correction circuit that receives pixel signals of a plurality of channels output from a plurality of channels of solid-state imaging devices each outputting a pixel signal in time series, and corrects pixel defects existing in the solid-state imaging device,
First computing means for generating a first interpolation average signal Zav that is an average value of pixel signals adjacent to pixel signals of a defective channel having pixel defects ;
A high-frequency signal Fdef that is a difference between the pixel signal Fnt of the correction channel and the second interpolation average signal Fav that is an average value of pixel signals adjacent to the pixel signal of the correction channel used for defective pixel correction is generated. A second computing means;
A correction coefficient generation means for generating a correction coefficient Kdef as the first interpolation average signal Zav and said second interpolated average signal Fav ratio,
Third arithmetic means for generating a correction signal from the first interpolation average signal Zav, the high-frequency signal Fdef, and the correction coefficient Kdef ;
And an output switching circuit for switching and outputting a said correction signal to the pixel signal of the defective channel out of the pixel signals of the plurality of channels,
The third calculating means is
A multiplier for multiplying the high-frequency signal Fdef and the correction coefficient Kdef ;
Defect pixel correction circuit you, comprising an adder for adding the output and the first interpolated average signal Zav of the multiplier. Before Symbol correction coefficient generation means,
5. The defective pixel correction circuit according to claim 4 , further comprising a divider that divides the first interpolation average signal Zav by the second interpolation average signal Fav .

Images