JPH06165044A - Correcting device doe solid-state imaging device - Google Patents

Abstract

PURPOSE:To prevent the degradation of picture quality by reproducing the image data of fine longitudinal stripes, for example, by estimating the output of the defective picture element of a CCD element from the output of the other CCD element. CONSTITUTION:This device is provided with CDS circuits 8, 9 and 10 for respectively sampling the outputs of CCD elements 1, 2 and 3, defective position signal generating circuit 19 for generating the position signal of the defective picture element and various control signals, timing generation circuit 4 for supplying timing signals to the CCD elements 1, 2 and 3 and supplying sampling signals to the CDS circuits 8, 9 and 10, estimating arithmetic circuit 17 for respectively providing the correcting signals of the picture element as a correcting object based on outputs from the CDS circuits 8, 9 and 10, and switches 20, 22 and 24 for switching and outputting a main line signal and a correcting signal based on a switching signal from the defective position signal generating circuit 19.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image sensor correction apparatus suitable for application to, for example, a video camera camera using a CCD element.

[0002]

2. Description of the Related Art Conventionally, for example, in a video camera using a CCD element, an image is picked up by a so-called defective pixel which outputs a signal of a specific level in a state where no light is incident, among the pixels of the CCD element. There is a problem that the quality of the obtained image deteriorates.

Therefore, conventionally, a correction circuit for correcting the signal output by the defective pixel is mounted on the video camera, and before the video camera is shipped to the user, the C of the video camera is mounted.
After inspecting which pixel of the CD element is the defective pixel and storing the information indicating the defective pixel obtained as a result of the inspection in the storage area of the correction circuit of the video camera, etc., after passing to the user's hand The correction circuit corrects the signal output from the defective pixel.

As this correction method, a defect correction method such as so-called 0th-order interpolation and 1st-order interpolation and a so-called RPN (residual pattern noise) correction method have been put into practical use.

Among the former correction methods, the 0th-order interpolation is a method of holding a signal output from a defective pixel in a sampling circuit and replacing the signal output from the defective pixel with the signal of the immediately preceding pixel.

In the former correction method, the primary interpolation obtains the average of the signal output from the pixel immediately preceding the defective pixel and the signal output from the pixel next to the defective pixel, and calculates the average from the defective pixel. This is a method of replacing the output signal with an average signal.

In the latter method, that is, RPN (residual pattern noise) correction, a signal corresponding to the signal output from the defective pixel is generated inside the video camera, and the signal output from the defective pixel is generated. This is a method of subtracting the signal to cancel the signal output from the defective pixel.

[0008]

By the way, in the method of holding the signal output from the defective pixel in the sampling circuit and replacing the signal output from the defective pixel with the signal of the previous pixel, the correction point is set. Since the frequency band of 1 is halved, information loss occurs, which makes it impossible to reproduce image data such as fine vertical stripes, resulting in a very poor image quality.

The present invention has been made in view of the above point, and is intended to propose a correction device for a CCD element which can reproduce image data such as fine vertical stripes and thereby prevent deterioration of image quality. is there.

[0010]

According to the present invention, a plurality of sampling means 8, 9 and 10 for sampling output signals from a plurality of solid-state image pickup devices 1, 2 and 3, respectively, and solid-state image pickup devices 1, 2 and 3 are provided. Among the respective pixels, control means 18 and 19 for generating a signal indicating the position of the pixel to be corrected and various control signals corresponding to the position of the pixel, and a plurality of solid-state imaging devices 1, 2, 3, and timing generating means 4, 5, 6, 7 for supplying the sampling signals to the plurality of sampling means 8, 9, 10 based on the control signals from the control means 18, 19 respectively.
Correction means 11, 12, 13, 14, 15, 16, 17 for respectively obtaining correction signals of pixels to be corrected based on the plurality of output signals from the plurality of sampling means 8, 9, 10.
And output means 20, 22, 24 for selectively outputting the output signals or correction signals from the sampling means 8, 9, 10 based on the control signals from the control means 18, 19.

Further, in the above description of the present invention, the plurality of sampling means 8, 9, 10 are connected to the plurality of solid-state image pickup elements 1,
The outputs from the timing generators 2, 5, 6,
This is a correlated double sampling means for performing sample and hold based on the plurality of first and second sample and hold signals from 7.

Further, the present invention is based on the above description, the control means 1
Reference numerals 8 and 19 denote at least a plurality of solid-state image pickup elements 1, 2, 3
The storage means 18 for indicating the position of the correction target pixel is included.

Further, in the above description of the present invention, the timing generating means 4, 5, 6, 7 are the sampling means 8, 9, 1
It has a plurality of selection means 5, 6, and 7 for selecting the supply of a plurality of sampling signals to 0 based on the control signals from the control means 18 and 19.

Further, the present invention is based on the above description.
A plurality of conversion means 11, 12, 13 for converting the outputs from the plurality of sampling means 8, 9, 10 into digital signals from 1, 12, 13, 14, 15, 16, 17 and these conversion means 11 , 12, 13 for delaying the respective outputs from the respective output means 12, 15, 13 and the respective output from the plurality of conversion means 14, 15, 16 and the control means 18, 19.
The estimation calculation means 17 estimates the correction signal of the pixel to be corrected based on the control signal from.

Further, according to the present invention described above, in the estimation calculation means 17, the pixels of the first and second solid-state image pickup devices 1 and 2 among the plurality of solid-state image pickup devices 1 and 2 are shifted. The estimation of the correction signal of the correction target pixel of the output of the third solid-state image sensor 3,
It is performed by using the output of the first or second solid-state imaging device 1 or 2 of the 2 and 3.

Further, according to the present invention described above, the estimation calculation means 17 performs a plurality of estimations of the correction signal of the correction target pixel of the output of the first solid-state image sensor 1, among the plurality of solid-state image sensors 1, 2, and 3. The output of the second solid-state image sensor 2 among the solid-state image sensors 1, 2, and 3 is used.

Further, according to the present invention, in the above-mentioned estimation calculation means 17, a plurality of estimations of the correction signal of the correction target pixel of the output of the second solid-state image pickup device 2 among the plurality of solid-state image pickup devices 1, 2, 3 are performed. The output of the first solid-state image pickup device 1 among the solid-state image pickup devices 1, 2, and 3 is used.

Further, according to the present invention described above, in the estimation calculation means 17, the correction signal of the correction target pixel of the output of one of the plurality of solid-state image pickup devices 1, 2 and 3 is corrected. In the case of obtaining based on the output of the other plurality of solid-state image pickup devices 1, 2 or 3, the one having a high level is selected.

Further, according to the present invention, in the above-mentioned estimation calculation means 17, the correction signal of the pixel to be corrected, which is the output of the third solid-state image pickup device 3 among the plurality of solid-state image pickup devices 1, 2, and 3, is first and second corrected. When obtaining based on the outputs of the second solid-state image pickup devices 1 and 2, the one having a high level is selected.

Further, according to the present invention, in the above description, the estimation calculation means 17 is configured to control the output of the first solid-state image pickup device 1 and the first and second solid-state image pickup devices 1, among the plurality of solid-state image pickup devices 1, 2, and 3.
First computing means 27, 2 for performing computation with the computation output of 2.
8, 29, 30 and the output of the second solid-state image sensor 2 out of the plurality of solid-state image sensors 1, 2, 3 and the operation output of the second and first solid-state image sensors 2, 1 Second computing means 33, 34, 35, 36 and a plurality of solid-state image pickup devices 1,
The output of the third solid-state image sensor 3 and the average output of the second solid-state image sensor 2 that are pixel-shifted with respect to the pixels of the first and second solid-state image sensors 1 and 2 Third computing means 38, 39, 41, 42, 43, 4 for computing
It is composed of 4 and.

Further, in the present invention described above, the first arithmetic means 27, 28, 29 and 30 are the first latch means 27 for latching the output of the first solid-state image pickup device 1, and the first latch means. Second latch means 28 for latching the output from 27, the output of the second solid-state image sensor 2 from the second computing means 33, 34, 35, 36 and the first latch means 27.
It is composed of a multiplication means 29 for multiplying the output from the above and a division means 30 for performing division by the output from the second latch means 28 and the multiplication output from the multiplication means 29.

Further, in the present invention, in the above description, the second arithmetic means 33, 34, 35 and 36 are the first latch means 33 for latching the output of the second solid-state image pickup device 2 and the first latch means. Second latch means 34 for latching the output from 33, the output of the first solid-state image sensor 1 from the first computing means 27, 28, 29, 30 and the first latch means 33.
It is composed of a multiplying means 35 for multiplying the output from the above and a dividing means 36 for performing the division by the output from the second latch means 34 and the multiplication output from the multiplying means 35.

Further, in the present invention, in the above description, the third arithmetic means 38, 39, 41, 42, 43, 44 are used as the first latch means 41 for latching the output of the third solid-state image pickup device 3.
And the second from the second computing means 33, 34, 35, 36.
Current output of the solid-state image sensor 2 of
Averaging means 38 and 39 for adding and averaging the previous outputs,
A multiplication means 42 for multiplying the average output from the averaging means 38, 39 and an output of the third solid-state imaging device 3 from the first latch means 41, and a second means for latching the average output from the averaging means 38, 39. The latch means 43 and the division means 44 for performing division by the output from the second latch means 43 and the multiplication output from the multiplication means 42.

Further, in the present invention described above, the estimation calculation means 17 sets an arbitrary time as k and a time immediately before this arbitrary time as (k-1), and selects one of a plurality of solid-state image pickup devices.
If the output of the first solid-state image sensor is y and the output of the second solid-state image sensor is x, and the output of the second solid-state image sensor corresponding to time k is the output to be corrected, y (k) / Y (k
The correction signal of the output to be corrected is calculated by the equation (-1) .x (k-1).

Further, in the present invention described above, the estimation calculation means 17 corrects using the output of at least two solid-state image pickup devices 1, 2 or 3 among the outputs of the plurality of solid-state image pickup devices 1, 2, 3. A quadratic curve is applied to a plurality of neighboring pixels of the pixel corresponding to the power output, and the original image is locally quadratic-approximated, the time when the curve takes an extreme value is obtained, and the pixel corresponding to the output to be corrected is calculated. The correction signal of the output to be corrected is estimated based on a plurality of neighboring pixels and the time of taking the extreme value.

Further, in the present invention described above, the estimation calculation means 17 sets an arbitrary time as k and a time immediately before this arbitrary time as (k-1), and a plurality of solid-state image pickup devices 1,
The second solid-state image sensor corresponding to time k, where y is the output of the first solid-state image sensor 1, 2 or 3 and x is the output of the second solid-state image sensor 1, 2 or 3 If the output of 1, 2 or 3 is the output to be corrected, {x (k +
1) + x (k-1)} / 2-[{x (k + 1) -x (k
-1)} {y (k + 1) + y (k-1) -2y
(K)}] / 2 {y (k + 1) -y (k-1)} is used to obtain the correction signal of the output to be corrected.

Further, according to the present invention described above, the estimation calculation means 17 includes at least two solid-state image pickup devices 1, 2 or 3 which have offsets of at least a half pixel period from the outputs of the plurality of solid-state image pickup devices 1, 2, and 3. The output of is used to apply a quadratic curve to a plurality of neighboring pixels of the pixel corresponding to the output to be corrected, and the original image is locally quadratic-approximated. The correction signal of the output to be corrected is estimated based on a plurality of neighboring pixels of the pixel corresponding to the output to be corrected and the time of taking the extreme value.

Further, in the present invention described above, the estimation calculation means 17 sets k as an arbitrary time and (k-1) as a time immediately before the arbitrary time, and a plurality of solid-state image pickup devices 1,
The second solid-state image sensor corresponding to time k, where y is the output of the first solid-state image sensor 1, 2 or 3 and x is the output of the second solid-state image sensor 1, 2 or 3 If the output of 1, 2 or 3 is the output to be corrected, {x (k +
1) + x (k-1)} / 2-[{x (k + 1) -x (k
-1)} {y (k + 1) + y (k-1) -2y
(K)}] / 4 {y (k) -y (k-1)} is used to obtain the correction signal of the output to be corrected.

[0029]

According to the configuration of the present invention described above, the control means 1
Signals indicating the positions of the pixels to be corrected among the pixels of the solid-state image pickup devices 1, 2, and 3 are generated by the reference numerals 8 and 19, and the correction means 11, 12, 13, 14, 15, 16, and 17 generate the signals. Based on the signal and the plurality of output signals from the plurality of sampling means 8, 9, 10 respectively, the correction signals of the pixels to be corrected are obtained, and based on the control signals from the control means 18, 19, the sampling means 8, 9, The output signal or the correction signal from 10 is selectively output by the output means 20, 22, and 24.

Further, according to the structure of the present invention described above,
Correlated double sampling is performed on the outputs from the plurality of solid-state image pickup devices 1, 2, and 3 based on the plurality of first and second sample and hold signals from the timing generators 4, 5, 6, and 7.

Further, according to the structure of the present invention described above,
A plurality of solid-state imaging devices 1 stored in the storage unit 18,
The control unit 19 uses the positions of a few pixels to be corrected.

Further in the above, according to the configuration of the present invention,
The supply of the plurality of sampling signals to the sampling means 8, 9, 10 is selected by the plurality of selecting means 5, 6, 7 based on the control signals from the control means 18, 19.

Further in the above, according to the configuration of the present invention,
The plurality of converting means 11, 12, 13 convert the outputs from the plurality of sampling means 8, 9, 10 into digital signals, and the respective outputs from the plurality of converting means 11, 12, 13 are delayed by 14, 15, 16 and each output from a plurality of conversion means 14, 15, 16 and control means 18,
Based on the control signal from 19, the correction signal of the correction target pixel is estimated by the estimation calculation means 17.

Further, according to the configuration of the present invention described above,
The output of the third solid-state image sensor 3 in which the estimation calculation means 17 shifts the pixels with respect to the pixels of the first and second solid-state image sensors 1 and 2 among the plurality of solid-state image sensors 1, 2, and 3. Of the correction signal of the correction target pixel of the first solid-state image sensor 1, the second solid-state image sensor 1, or the second solid-state image sensor 1,
The output of 2 is used.

Further in the above, according to the configuration of the present invention,
The estimation calculation means 17 estimates the correction signal of the correction target pixel of the output of the first solid-state image sensor 1 among the plurality of solid-state image sensors 1, 2, and 3 from among the plurality of solid-state image sensors 1, 2, and 3. , The output of the second solid-state image sensor 2 is used.

Further in the above, according to the configuration of the present invention,
The estimation calculation means 17 estimates the correction signal of the correction target pixel of the output of the second solid-state image sensor 2 among the plurality of solid-state image sensors 1, 2, and 3 from among the plurality of solid-state image sensors 1, 2, and 3. , Using the output of the first solid-state image sensor 1.

Further in the above, according to the configuration of the present invention,
The estimation calculation means 17 outputs the correction signal of the correction target pixel output from one of the solid-state imaging devices 1, 2 or 3 among the plurality of solid-state imaging devices 1, 2, and 3 to the other plurality of solid-state imaging devices 1, 2
Or, if it is obtained based on the output of 3, the one with the higher level is selected.

Further, according to the configuration of the present invention described above,
The estimation calculation means 17 outputs the correction signal of the correction target pixel of the output of the third solid-state image sensor 3 among the plurality of solid-state image sensors 1, 2, and 3 to the output of the first and second solid-state image sensors 1 and 2. If you get based on, select the one with a higher level.

Further, according to the configuration of the present invention described above,
Of the plurality of solid-state image pickup devices 1, 2, and 3, first calculation means 27, 28 calculates the output of the first solid-state image pickup device 1 and the calculation output of the first and second solid-state image pickup devices 1, 2. , 29, 30
And the output of the second solid-state image sensor 2 and the second and first solid-state image sensors 2 among the plurality of solid-state image sensors 1, 2, and 3.
The calculation with the calculation output of 1 is performed by the second calculation means 33, 34, 3
5 and 36, and among the plurality of solid-state imaging devices 1, 2, and 3,
The calculation of the output of the third solid-state image sensor 3 and the average output of the second solid-state image sensor 2 which are pixel-shifted with respect to the pixels of the first and second solid-state image sensors 1 and 2 is performed by the third calculation. The calculation means 38, 39, 41, 42, 43, 44 are used.

Further in the above, according to the configuration of the present invention,
The output of the first solid-state imaging device 1 is latched by the first latch means 27, and the output from the first latch means 27 is used as the second output.
Latched by the latch means 28 of the second arithmetic means 33, 3
The multiplication means 29 performs multiplication of the output of the second solid-state imaging device 2 from 4, 35 and 36 and the output from the first latch means 27.
The division means 30 performs division with the output from the second latch means 28 and the multiplication output from the multiplication means 29.

Furthermore, according to the configuration of the present invention described above,
The output of the second solid-state imaging device 2 is latched by the first latch means 33, and the output from the first latch means 33 is used as the second output.
Latched by the latch means 34 of the first arithmetic means 27, 2
Multiplying means 35 performs multiplication of the output of the first solid-state image pickup device 1 from 8, 29 and 30 and the output from the first latch means 33.
The division by the output from the second latch means 34 and the multiplication output from the multiplication means 35 is performed by the division means 36.

Further, according to the configuration of the present invention described above,
The output of the third solid-state image sensor 3 is latched by the first latch means 41, and the current output of the second solid-state image sensor 2 from the second arithmetic means 33, 34, 35, 36 and 1 from this current time. The previous output is added and averaged by the averaging means 38 and 39, and the average output from the averaging means 38 and 39 and the output of the third solid-state image sensor 3 from the first latching means 41 are multiplied by the multiplying means 42. Then, the average output from the averaging means 38 and 39 is latched by the second latch means 43, and the division by the output from the second latch means 43 and the multiplication output from the multiplication means 42 is performed by the division means 44. To do.

Further, according to the structure of the present invention described above,
The estimation calculation means 17 sets an arbitrary time as k, sets a time immediately before this arbitrary time as (k-1), and outputs the output of the first solid-state imaging device among the plurality of solid-state imaging devices as y, If the output of the second solid-state image sensor is x, and the output of the second solid-state image sensor corresponding to time k is the output to be corrected, y
The correction signal of the output to be corrected is obtained by the equation shown by (k) / y (k-1) .x (k-1).

Further in the above, according to the configuration of the present invention,
The estimation calculation means 17 uses the outputs of at least two solid-state image pickup devices 1, 2 or 3 among the outputs of the plurality of solid-state image pickup devices 1, 2, 3 to determine the neighborhood of a pixel corresponding to the output to be corrected. A quadratic curve is applied to a pixel to locally quadratic approximate the original image, the time at which the curve takes an extreme value is obtained, and a plurality of neighboring pixels of the pixel corresponding to the output to be corrected and the time at which the extreme value is taken. Based on the above, the correction signal of the output to be corrected is estimated.

Further, according to the configuration of the present invention described above,
The estimation calculation means 17 sets an arbitrary time as k and a time immediately before this arbitrary time as (k−1), and selects the first solid-state image sensor among the plurality of solid-state image sensors 1, 2, and 3. The output of 1, 2 or 3 is y, the output of the second solid-state image sensor 1, 2 or 3 is x, and the output of the second solid-state image sensor 1, 2 or 3 corresponding to the time k should be corrected. If
{X (k + 1) + x (k-1)} / 2-[{x (k +
1) -x (k-1)} {y (k + 1) + y (k-1)-
2y (k)}] / 2 {y (k + 1) -y (k-1)} is used to obtain the correction signal of the output to be corrected.

Further, in the above, according to the configuration of the present invention,
The estimation calculation means 17 uses the outputs of at least two solid-state image pickup devices 1, 2 or 3 having offsets of at least half a pixel cycle among the outputs of the plurality of solid-state image pickup devices 1, 2 and 3 and outputs to be corrected. A quadratic curve is applied to a plurality of neighboring pixels of the pixel corresponding to, the original image is locally quadratic-approximated, the time when the curve takes an extreme value is obtained, and a plurality of pixels of the pixel corresponding to the output to be corrected are obtained. The correction signal of the output to be corrected is estimated based on the time of taking the extreme value with the neighboring pixels.

Further, according to the configuration of the present invention described above,
The estimation calculation means 17 sets an arbitrary time as k and a time immediately before this arbitrary time as (k−1), and selects the first solid-state image sensor among the plurality of solid-state image sensors 1, 2, and 3. The output of 1, 2 or 3 is y, the output of the second solid-state image sensor 1, 2 or 3 is x, and the output of the second solid-state image sensor 1, 2 or 3 corresponding to the time k should be corrected. If
{X (k + 1) + x (k-1)} / 2-[{x (k +
1) -x (k-1)} {y (k + 1) + y (k-1)-
2y (k)}] / 4 {y (k) -y (k-1)} is used to obtain the correction signal of the output to be corrected.

[0048]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a solid-state image pickup device correction apparatus according to the present invention will be described in detail below with reference to FIG.

In FIG. 1, 1 is a CCD for blue (B)
Elements, 2 is CCD element for red (R), 3 is CC for green (G)
In the D element, each of the CCD elements 1, 2 and 3 converts light from an optical system of a video camera (not shown) into an electric signal, and outputs it as a video signal by a control signal from a timing generation circuit 4 which will be described later.

Video signals from these CCD elements 1, 2 and 3 are supplied to correlated double sampling circuits (hereinafter referred to as CDS circuits) 8, 9 and 10, respectively. These CDs
The S circuits 8, 9 and 10 respectively sample the video signals from the CCD elements 1, 2 and 3 based on the two sample and hold signals from the timing generation circuit 4, and the video signals obtained by sampling are AD respectively. Converter 11, 12
And 13 (including preprocessing for AD conversion) to the delay circuits 14, 15 and 16 and the estimation calculation circuit 17.

The timing generation circuit 4 is, as described above,
A control signal is supplied to the CCD element, and the CDS circuits 8, 9 and 10 are connected via switches 5, 6 and 7, respectively.
In addition to directly supplying two sample hold signals, a timing signal is supplied to a defect position signal generating circuit 19 described later.

The defect position signal generation circuit 19 reads the defect position data from the defect position memory 18, obtains the defect position signal based on the read defect position data and the timing signal from the timing generation circuit 4, and the defect position signal. The signal is supplied to the estimation arithmetic circuit 17, and the defect position signal is supplied to the switches 5, 6 and 7 as a switching signal.

Here, the defect position memory 18 is, for example, EE.
As described above, the three CCD elements 1 and 2 each composed of a PROM, an EPROM, a one-time ROM, a RAM with a backup, and the like are detected in advance by a defective pixel inspection or the like.
The position data of the defective pixels 3 and 3 are written.

Based on the position data of the defective pixels of the three CCD elements 1, 2 and 3 read from the defect position memory 18, the defect position signal generation circuit 19 detects the CCD elements 1, 2 and 3.
By switching the switches 5, 6 and 7 corresponding to 3 and 3, respectively, the sampling operation in the three CDS circuits 8, 9 and 10 corresponding to these CCD elements 1, 2 and 3 can be controlled. The necessity of these switches 5, 6 and 7 will be described later in detail.

The delay circuits 14, 15 and 16 are provided for the AD converter 1 by the amount of the signal delayed by the estimation operation circuit 17.
The video signals from 1, 12, and 13 are delayed, and the delayed video signals are fixed contacts 2 of the switches 20, 22, and 24.
Supply to 0a, 22a and 24a respectively.

As will be described in detail later, the estimation calculation circuit 17 performs a predetermined calculation process on the video signals (corresponding to blue, red and green, respectively) from the AD converters 11, 12 and 13. , The correction signal for the defective pixel is obtained, and the correction signal is supplied to each of the fixed contacts 20b, 2 of the switches 20, 22 and 24.
2b and 24b, respectively.

Therefore, in the switch 20, the movable contact 20c is selectively connected to the fixed contact 20a or 20b by the switching signal from the defect position signal generating circuit 19, so that the video signal corresponding to red from the delay circuit 14 is produced. , Or the correction signal for the defective pixel from the estimation calculation circuit 17 is selectively supplied to another signal processing circuit or the like of the video camera (not shown) via the output terminal 21.

In the switch 22, the movable contact 2 is driven by the switching signal from the defect position signal generating circuit 19.
By selectively connecting 2c to the fixed contact 22a or 22b, the video signal corresponding to red from the delay circuit 14 or the correction signal for the defective pixel from the estimation arithmetic circuit 17 is selectively output through the output terminal 23. Are supplied to other signal processing circuits of the video camera (not shown).

In the switch 24, the movable contact 2 is driven by the switching signal from the defect position signal generating circuit 19.
By selectively connecting 4c to the fixed contact 24a or 24b, the video signal corresponding to red from the delay circuit 14 or the correction signal for the defective pixel from the estimation arithmetic circuit 17 is selectively supplied through the output terminal 25. Are supplied to other signal processing circuits of the video camera (not shown).

Next, the estimation calculation circuit 17 shown in FIG. 1 will be described in more detail with reference to FIG.

In FIG. 2, reference numeral 26 denotes A shown in FIG.
An input terminal to which a video signal corresponding to blue from the -D converter 11 is supplied. The input terminal 26 is connected to the input terminal of the division circuit 30 via a flip-flop circuit 27 and a flip-flop circuit 28. The connection point of the flip-flop circuits 27 and 28 is connected to the input terminal of the multiplication circuit 29, and the output terminal of the multiplication circuit 29 is connected to the input terminal of the division circuit 30. Further, the output terminal of the flip-flop circuit 34 of the processing system of the video signal corresponding to red, which will be described later, is connected to the input terminal of the multiplication circuit 29.

Reference numeral 32 denotes the AD converter 12 shown in FIG.
Input terminal to which the video signal corresponding to red from is supplied,
The input terminal 32 is connected to the input terminal of the division circuit 36 via the flip-flop circuit 33 and the flip-flop circuit 34, and the connection point of the flip-flop circuits 33 and 34 is connected to the input terminal of the multiplication circuit 35. Further, the output terminal of the multiplication circuit 35 is connected to the input terminal of the division circuit 36. Further, the output terminal of the flip-flop circuit 28 of the video signal processing system corresponding to red is connected to the input terminal of the multiplication circuit 35.

Reference numeral 40 denotes the AD converter 13 shown in FIG.
Input terminal to which the video signal corresponding to green from is supplied,
This input terminal 40 is connected to the input terminal of the multiplication circuit 42 via a flip-flop circuit 42, and the multiplication circuit 4
The output terminal of 2 is connected to the input terminal of the division circuit 44.

On the other hand, the input terminal 32 to which the video signal corresponding to red is supplied is connected to the input terminal of the adding circuit 38, and the output terminal of the flip-flop circuit 33 is connected to the input terminal of the adding circuit 38. The output terminal of the adding circuit 38 is connected to the multiplying circuit 3
9 and the output terminal of the multiplication circuit 39 is connected to the input terminal of the flip-flop circuit 43 and the multiplication circuit 42.
, And the output end of the flip-flop circuit 43 is connected to the input end of the division circuit 44.

Here, in the multiplication circuit 39, for example, the addition output from the addition circuit 38 is multiplied by a factor of 1/2, and the video signal corresponding to the current red from the input terminal 32 and the flip-flop circuit 33. The average with the video signal corresponding to the red one before the present is obtained.

Before explaining the operation of this circuit, referring to FIG. 3, among the CCD elements 1, 2 or 3, the healthy CCD element 1,
2 or 3 and CCD 1, 2 or 3 having a defective pixel will be described. For example, FIG. 3A shows a CCD without defective pixels.
The time at which the element is present (... k-3, k-2, k-1,
FIG. 3B shows output waveforms obtained by sampling for each pixel of k, k + 1, k + 2, ..., At a certain time (... K-3, k-2, k-) of the CCD element having the defective pixel. 1, k,
The output waveforms obtained by sampling are shown for each pixel (k + 1, k + 2, ...).

FIG. 4A shows output waveforms of CCD elements having no defective pixels, and FIG. 4B shows output waveforms obtained by sampling the CCD elements having defective pixels at times k−1 and k, respectively. If the defective pixel is x (k), y (n) and x
(N) is calculated to estimate x (k), which is used as a correction signal.

Although various estimation algorithms can be considered, the case of performing the first-order estimation will be described here as an example.

The defective pixel x (k) can be estimated by the following equation (1).

[0070]

## EQU00001 ## x (k) = {y (k) / y (k-1)}. X (k-1)

That is, this is based on the rate of change between adjacent pixels in the CCD element having no defective pixel shown in FIG.
It is shown that even in the CCD device having the defective pixel shown in (4), the estimation is performed on the assumption that the rate of change between adjacent pixels is the same.

Now, as described above, the CCD elements are blue, red,
When three are used for green, the geometrical positions of pixels in the blue and red channels are the same, so the above-mentioned so-called local tracking of the signal is assumed, and the estimations according to Equation 1 are mutually performed. You can

However, in order to increase the resolution of the green channel, the pixel position is set to a state in which the pixels are shifted by 1/2 in the horizontal direction with respect to the blue and red channels.
Therefore, it is slightly dangerous to use the above tracking as it is.

FIG. 5 shows an arrangement of pixels and an example of an incident image when the pixels are shifted. In FIG. 5, the shaded portion is a portion where no light is incident, the non-hatched portion is a portion where light is incident, and the green CC is shown in the upper row.
Pixels of the D element, and pixels of the blue and red CCD elements in the lower stage are shown with reference numerals indicating time (k, k + 1, ... K + 9 ...). As shown in FIG. 5, a green CCD
The geometrical positions of the pixels of the device and the geometrical positions of the pixels of the blue and red CCD devices are shifted by 1/2 pitch.

FIG. 6A shows the green CCD element in this case, and FIG. 6B shows the output waveforms of the blue and red CCD elements. As shown in FIG. 6, the output corresponding to green shown in FIG. 6A and the outputs corresponding to blue and red are displaced from each other by about 1/2 pitch in terms of time.

The average of two blue or red pixels B or R located on the left and right of the pixel of the green CCD element is G '(FIG. 6C).
As a reference), when the estimation shown in Formula 1 is performed based on this, it can be expressed by the following Formula 2.

[0077]

## EQU00002 ## G '(k) = 1/2 {R (k) + R (k-1)}

When the equation shown in the equation 2 is applied to the equation shown in the equation 1, the following equation 3 is obtained.

[0079]

## EQU00003 ## G (k) = {G '(k) / G' (k-1)}. G (k-1)

In this way, the value of any channel can be estimated using any of the blue, red, and green channels. Then, by this estimation, the value of the defective pixel can be estimated and the defect can be corrected. There are various possible methods for deciding which channel to select for the data to be estimated. For example, when a channel with a high signal level is selected, it is advantageous in terms of S / N.

That is, since the circuit configuration shown in FIG. 1 can perform the operation of switching the original signal and the estimated signal at the defective pixel position, and the nonlinear processing is required in the more advanced estimation algorithm, it can be used as a digital signal system. It was realized. Estimating arithmetic circuit 17 shown in FIG.
Is a part for performing the calculation of the formulas shown in Formula 1, Formula 2 and Formula 3, and the switches 20, 22 and 24 switch between the main line signal and the estimated signal at the defect position.
Further, the delay circuits 14, 15 and 16 compensate for the delay due to the estimation calculation (for example, two clocks) so that the main line signal and the estimated signal are timed.

FIG. 2 shows a configuration example for performing the calculation of the formulas shown in Formula 1, Formula 2 and Formula 3, and as shown in Formula 1, Formula 2 and Formula 3, corresponds to red as an example. The video signal corresponding to blue is estimated from the video signal corresponding to the above, and the video signal corresponding to red is estimated from the video signal corresponding to blue.
Based on the signal of the red channel, which is more advantageous than the blue channel in terms of N, the green channel is estimated from the equation shown in Equation 3 to obtain the above-mentioned G ′, and this G ′ is used as the correction signal G I try to estimate the signal.

By the way, when the correction signal is obtained by the estimation and is switched to the main line signal in this manner, the front of the CDS circuits 8, 9 and 10 and the A / D converters 11, 12 and 13 shown in FIG. The response of the process causes the defect signal, which is an impulse, to spread, and the spread of the signal corresponding to the defective pixel may cause an error in the subsequent process.

Therefore, in this example, as described above,
The defect position signal generation circuit 1 is provided with switches 5, 6 and 7.
When the defective pixel is output by the switching signal from 9, the switches 5, 6 and 7 are turned off to turn on the CDS.
Sampling of the output signal by defective pixels in circuits 8, 9 and 10 is prevented.

By doing so, the signal is muted when the defective pixel is output, and it does not affect the subsequent processing.

Next, the operation of the circuit shown in FIG. 1 will be described, centering on the operation of the estimation operation circuit 17 shown in FIG.

First, the blue component light is applied to the CCD element 1 and the red component light is applied to the CCD element 2 through an optical system (not shown).
The light of the green component is incident on the element 3, respectively.
The D elements 1, 2 and 3 output the received light as a video signal by the timing signal from the timing generation circuit 4 by photoelectric conversion. The blue channel (B channel) image signal, the red channel (R channel) image signal and the green channel (G channel) image signal output from the CCD elements 1, 2 and 3 are respectively supplied to the CDS circuit 8,
9 and 10 respectively.

The B, R and G channel video signals supplied to the CDS circuits 8, 9 and 10 are sampled and held, respectively, and then converted into digital signals by the AD converters 11, 12 and 13, and the delay circuit 14, 15 and 1
6 and is output after being delayed by, for example, 2 clocks, and the fixed contacts 20a of the switches 20, 22 and 24,
22a and 24a, respectively.

On the other hand, the AD converters 11, 12 and 1
The digital video signals of the B, R and G channels respectively output from 3 are also supplied to the estimation calculation circuit 17.

The B-channel digital video signal supplied to the estimation calculation circuit 17 through the input terminal 26 is latched by the flip-flop circuit 27 and then multiplied by the multiplication circuit 29.
Is supplied to.

The R channel digital video signal supplied to the estimation calculation circuit 17 through the input terminal 32 is sequentially latched by the flip-flop circuits 33 and 34 and supplied to the division circuit 36.

Since the output of the flip-flop circuit 34 is supplied to the multiplication circuit 29 of the B-channel processing system, the flip-flop circuit 2 is used in the multiplication circuit 29.
7 and the latch output from the flip-flop circuit 34 (k-1), that is,
The (k) time output of the B channel is multiplied by the (k-1) time output of the R channel.

The multiplication output B (k) × R (k-
1) is divided by the output of the flip-flop circuit 28, that is, the output at the time of (k-1) of the B channel in the division circuit 30, and as a correction signal (estimated signal) of the R channel from the output terminal 31. It is output and supplied to the fixed contact 20b of the switch 20 shown in FIG.

On the other hand, the output of the flip-flop circuit 33, that is, the output of the R channel at time (k), is the output of the B channel flip-flop circuit 28 in the multiplication circuit 35, that is, the time of the B channel (k- It is multiplied by the output of 1) and supplied to the division circuit 36.

Therefore, in the division circuit 36, the output R (k) × B (k−1) of the multiplication circuit 35 is divided by the output R (k−1) from the flip-flop circuit 34, and the output terminal 37. Is output as a B-channel correction signal (estimation signal) and is supplied to the fixed contact 22b of the switch 22 shown in FIG.

Further, in the adder circuit 38, the R channel digital video signal (at the time of k + 1) supplied to the input terminal 32 and the flip-flop circuit 33.
Output (assumed to be time of k) is added and R (k + 1) +
R (k), this signal is supplied to the multiplication circuit 39 and averaged to {R (k + 1) + R (k)} / 2.
The signals obtained by this averaging are supplied to the multiplication circuit 42 and the flip-flop circuit 43, respectively. Here, this averaged output {R (k + 1) + R (k)} / 2 is defined as G ′ (k).

In the multiplication circuit 42, the output of the flip-flop circuit 41, that is, G (k-1) is multiplied by the output G '(k) from the multiplication circuit 39 to obtain the output G (k-
1) × G ′ (k), and this output is supplied to the division circuit 44.

On the other hand, the output G '(k) of the multiplication circuit 39 is latched by the flip-flop circuit 43, that is, G'.
(K-1) is supplied to the division circuit 44. Therefore, in the division circuit 44, the output G from the multiplication circuit 42
(K−1) × G ′ (k) is the flip-flop circuit 43
Output G ′ (k−1) divided by output {G (k−
1) · G ′ (k)} / G ′ (k−1), and this output is output as a G channel correction signal (estimated signal) via the output terminal 45, and the fixed contact of the switch 24 shown in FIG. 24b. In addition, G channel and B and R
The time difference between channels is due to pixel shift, as described in FIGS. 3 and 4.

Now, in the switches 20, 22 and 24 shown in FIG. 1, B and R generated as described above are used.
And G channel correction signals (estimated signals) and B, R and G from the delay circuits 14, 15 and 16 which are main line signals.
The signal of the channel is switched by the switching signal from the defect position signal generating circuit 19, and the output terminal 21,
23 and 25 are supplied to the video camera main body circuit (not shown), respectively. That is, when the defective position is in the B channel, the movable contact 20c of the switch 20 is connected to the fixed contact 20b by the switching signal from the defective position signal generating circuit 19, whereby the correction signal of the B channel is output terminal 21. When the defect position is output in the R channel, the movable contact 22c of the switch 22 is connected to the fixed contact 22b by the switching signal from the defect position signal generation circuit 19, and the correction signal of the R channel is thereby generated. Is output via the output terminal 23 and the defect position is in the G channel, the movable contact 24c of the switch 24 is fixed by the switching signal from the defect position signal generating circuit 19.
, So that the G channel correction signal is output via the output terminal 25.

As described above, in this example, the estimation arithmetic circuit 17 estimates the output of the defective pixel of the B channel by calculating the outputs of the B and R channels to obtain a correction signal, and outputs the defective pixel of the R channel. Is calculated by estimating the outputs of the R and B channels to obtain a correction signal, and the output of the defective pixel of the G channel is estimated by calculating with the B or R channel to obtain a correction signal. , 22 and 24, the switching signal from the defect position signal generating circuit 19 for switching to these signals at the time of the defect position is switched to the main line signal for output, so that image data such as fine vertical stripes is generated. Can be faithfully reproduced, which can improve the image quality.

Further, the switches 5, 6 and 7 are provided, and at the time of outputting a defective pixel, the switches 5, 6 and 7 are turned off by the switching signal from the defective position signal generating circuit 19 and the CDS circuits 8, 9 and Since the sampling at 10 is not performed, the influence of the spread of the output signal due to the defective pixel can be eliminated.

Next, another example of the estimation operation circuit 17 shown in FIG. 2 will be described with reference to FIGS. 7 and 8.

FIG. 7 shows the configuration of another example of the estimation calculation circuit 17 as a whole. In FIG. 7, reference numeral 46 is an input terminal to which an output at time (k-1) of a channel having a defective pixel is supplied, and this input terminal 46 is connected to the input terminal of the adder circuit 51 and the input terminal of the adder circuit 53, respectively. Connecting. 47
Is an input terminal to which the output at the time (k + 1) of the channel having the defective pixel is supplied, and the input terminal 47 is connected to the input terminal of the adder circuit 51 and the input terminal of the adder circuit 53, respectively.

48 is the channel (k-
This is an input terminal to which the output at time 1) is supplied, and this input terminal 48 is connected to the input terminal of the adder circuit 54 and the input terminal of the adder circuit 57, respectively. Reference numeral 49 is an input terminal to which an output at time (k) of the channel having no defective pixel is supplied, and this input terminal 49 is connected to the input terminal of the multiplication circuit 55. Reference numeral 50 denotes an input terminal to which an output at time (k + 1) of a channel having no defective pixel is supplied.
And an input end of the adder circuit 57, respectively.

The output end of the addition circuit 51 is connected to the input end of the multiplication circuit 52, and the output end of the multiplication circuit 52 is added to the addition circuit 6.
0 is connected to the input terminal, and the output terminal of the adder circuit 60 is connected to the output terminal 61. The output end of the addition circuit 53 is connected to the input end of the multiplication circuit 56, the output end of the multiplication circuit 55 is connected to the input end of the addition circuit 54, and the output end of the addition circuit 54 is input end of the multiplication circuit 56. Connected to this multiplication circuit 5
The output terminal of 6 is connected to the input terminal of the dividing circuit 59, and the output terminal of the dividing circuit 59 is connected to the input terminal of the adding circuit 60.
The output end of the adder circuit 57 is connected to the input end of the multiplication circuit 58, and the output end of the multiplication circuit 58 is connected to the input end of the division circuit 59.

Here, the multiplication circuit 52 multiplies the output from the addition circuit 51 by a coefficient to halve, and
The multiplying circuit 55 multiplies the signal y (k) supplied through the input terminal 49 by a coefficient to double the multiplication, and the multiplying circuit 58 multiplies the output from the adding circuit 57 by a coefficient. It doubles by.

Next, the operation of the estimation operation circuit 17 shown in FIG. 7 will be described.

First, in the adder circuit 51, the input terminal 4
Signal x (k-1) supplied via 6 and input terminal 47
The signal x (k + 1) supplied via the above is added to form a signal x (k−1) + x (k + 1), which is supplied to the multiplying circuit 52, and is averaged to ½ in this multiplying circuit 52 to obtain the signal. {X (k−1) + x (k + 1)} / 2, which is supplied to the adder circuit 60.

The adder circuit 53 receives the signal x (k-1) via the input terminal 46 and the signal x (k-1) via the input terminal 47.
(K + 1) are respectively supplied, and added by this addition circuit 53 to become x (k + 1) -x (k-1), and the multiplication circuit 56
Is supplied to.

On the other hand, the signal y (k) is supplied to the multiplication circuit 55 via the input terminal 49, and the multiplication circuit 55 multiplies the signal by 2y (k) and supplies it to the addition circuit 54. The addition circuit 54 also receives the signal y (k-1) via the input terminal 48 and the signal y via the input terminal 50.
(K + 1) are respectively supplied, and therefore the output of the adding circuit 54 becomes y (k-1) + y (k + 1) -2 (k).
This addition output is supplied to the multiplication circuit 56 and the addition circuit 53.
Output x (k + 1) -x (k-1) of {y
(K-1) + y (k + 1) -2y (k)} · {x (k +
1) −x (k−1)}, which is then supplied to the division circuit 59.

Now, to the adder circuit 57, the signal y (k-1) is input via the input terminal 48, and y (k +) is input via the input terminal 50.
1) are respectively supplied and added in this addition circuit 57 to be y (k + 1) -y (k-1), and the multiplication circuit 58
Are multiplied by the coefficient in the multiplication circuit 58 to obtain 2 {y (k + 1) -y (k-1)}, which is then supplied to the division circuit 59.

In the division circuit 59, {y (k-1)
+ Y (k + 1) -2y (k)} · {x (k + 1) -x
(K-1)} / [2 {y (k + 1) -y (k-1)}]
Is performed and the result is supplied to the adder circuit 60.

Then, in the adder circuit 60, the output of the multiplier circuit 52 is {x (k-1) + x (k + 1)} / 2.
To {y (k-1) + y (k + 1) -2y (k)}.
{X (k + 1) -x (k-1)} / [2 {y (k + 1)
-Y (k-1)}] is subtracted, and the subtraction result is supplied as a correction signal (estimated signal) to the video camera main body circuit (not shown) via the output terminal 61.

That is, x (n) (n = ... k-2, k
−1, k, k + 1, k + 2, ...) As the output of the CCD element having the defective pixel, a correction signal (estimated signal) for the output of the defective pixel can be obtained by the following equation (4). it can.

[0115]

X * (k) = {x (k-1) + x (k + 1)} / 2-[{y (k-1) + y (k + 1) -2y (k)} {x (k + 1) -x (K-1)}] / [2 {y (k + 1) -y (k-1)}]

This will be described in more detail with reference to FIG. FIG. 8A shows the output for each pixel of the CCD element having no defective pixel, and FIG. 8B shows the output for each pixel of the CCD element having a defective pixel. Further, in FIG. 8A, p1, p2, and p3 are outputs at times (k−1), (k), and (k + 1) corresponding to pixels, and s1 can be approximated by these outputs.
The next curve, t1 is the time when the quadratic curve by this approximation takes the extreme value d, and in FIG. 8B, p10, p11 and p1
2 is the output at times (k-1), (k) and (k + 1) corresponding to each pixel (note that p11 is the output due to the defective pixel), s10 is a quadratic curve that can be approximated by these outputs,
t10 is the time when the quadratic curve based on this approximation has the extreme value d.

As shown in FIGS. 8A and 8B, in this example, the quadratic curve s10 is applied to the three pixels in the vicinity of the defective pixel x * (k). This is a local second-order approximation of the original image. Time t10 when this curve s10 takes the extreme value d is obtained, and since it is the same pixel, the time t10 when the extreme value d is obtained with two points in the vicinity of the defective pixel p11 of the defective channel.
, The defective pixel x * (k) is estimated in the defective channel.

As described above, in this example, since the estimation is performed by the equation shown in Formula 4, it is certain that
In addition, the estimation calculation can be realized with a simple circuit configuration. The signals supplied to the input terminals 46, 47, ... 50 are flip-flops as described with reference to FIG.
It shall be obtained by a flop circuit or the like.

FIGS. 9 and 10 show still another example of the estimation operation circuit 17 described with reference to FIGS. 9 and 10, parts corresponding to those in FIGS. 7 and 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

FIG. 9 shows a configuration example of the estimation calculation circuit 17. Since the estimation calculation circuit 17 shown in FIG. 9 has substantially the same configuration as the estimation calculation circuit 17 shown in FIG. 7, only different parts will be described.

The estimation operation circuit 17 shown in FIG. 9 differs from the estimation operation circuit 17 shown in FIG. 7 in that the input terminal 49 to which the signal y (k) is supplied is connected to the addition circuit 57.
That is, the circuit configuration shown in FIG. 9 is for estimating between the channels to which the spatial pixel shift has been applied.

The operation of the estimation operation circuit 17 shown in FIG. 9 will be described. First, in the adder circuit 51, the input terminal 4
Signal x (k-1) supplied via 6 and input terminal 47
The signal x (k + 1) supplied via the above is added to form a signal x (k−1) + x (k + 1), which is supplied to the multiplying circuit 52, and is averaged to ½ in this multiplying circuit 52 to obtain the signal. {X (k−1) + x (k + 1)} / 2, which is supplied to the adder circuit 60.

The addition circuit 53 receives the signal x (k-1) via the input terminal 46 and the signal x (k-1) via the input terminal 47.
(K + 1) are respectively supplied, and added by this addition circuit 53 to become x (k + 1) -x (k-1), and the multiplication circuit 56
Is supplied to.

On the other hand, the signal y (k) is supplied to the multiplication circuit 55 via the input terminal 49, and the multiplication circuit 55 multiplies the signal by 2y (k) and supplies it to the addition circuit 54. The addition circuit 54 also receives the signal y (k-1) via the input terminal 48 and the signal y via the input terminal 50.
(K + 1) are respectively supplied, and therefore the output of the adding circuit 54 becomes y (k-1) + y (k + 1) -2 (k).
This addition output is supplied to the multiplication circuit 56 and the addition circuit 53.
Output x (k + 1) -x (k-1) of {y
(K-1) + y (k + 1) -2y (k)} · {x (k +
1) −x (k−1)}, which is then supplied to the division circuit 59.

The adder circuit 57 receives the signal y (k-1) via the input terminal 48 and y (k) via the input terminal 49.
Are respectively supplied, and are added in the adding circuit 57 to be y (k) -y (k-1), which are supplied to the multiplying circuit 58, which is multiplied by the coefficient in the multiplying circuit 58 to obtain 2 {y.
(K) -y (k-1)}, which is then supplied to the division circuit 59.

In the division circuit 59, {y (k-1)
+ Y (k + 1) -2y (k)} · {x (k + 1) -x
The calculation of (k-1)} / [2 {y (k) -y (k-1)}] is performed, and the result is supplied to the adder circuit 60.

Then, in the adder circuit 60, the output of the multiplier circuit 52 is {x (k-1) + x (k + 1)} / 2.
To {y (k-1) + y (k + 1) -2y (k)}.
{X (k + 1) -x (k-1)} / [2 {y (k) + y
(K-1)}] is subtracted, and the subtraction result is supplied as a correction signal (estimated signal) to the video camera body circuit (not shown) via the output terminal 61.

That is, x (n) (n = ... K-2, k
−1, k, k + 1, k + 2, ...) As the output of the CCD element having the defective pixel, a correction signal (estimated signal) for the output of the defective pixel can be obtained by the following equation (5). it can.

[0129]

## EQU00005 ## x * (k) = {x (k-1) + x (k + 1)} / 2-[{y (k-1) + y (k + 1) -2y (k)} {x (k + 1) -x (K-1)}] / [2 {y (k) -y (k-1)}]

This will be described in more detail with reference to FIG. FIG. 10A is similar to FIG. 8, and C without defective pixels
Output for each pixel of the CD element, FIG. 10B shows C with defective pixel
The output for each pixel of the CD element is shown. Also, FIG.
, P1, p2, and p3 are outputs at times (k−1), (k), and (k + 1) corresponding to pixels, s1 is a quadratic curve that can be approximated by these outputs, and t1 is a quadratic curve obtained by this approximation. It is the time at which the extreme value d is taken, and in FIG. 10B, p10, p11, and p12 are the outputs at the times (k−1), (k), and (k + 1) (note that p1) corresponding to the pixels, respectively.
1 is the output by the defective pixel), s10 is a quadratic curve that can be approximated by these outputs, and t10 is the time when the quadratic curve by this approximation takes the extreme value d.

As shown in FIG. 10, in this example, the sample time is offset by a half cycle with the actual time. That is, the time at which the extreme value d is obtained is the same regardless of whether or not there is a defect, but in terms of the time difference from the sample time k, there is a difference of half pixel period in the output of each pixel shown in FIGS. 10A and 10B. This is taken into consideration by the equation shown in the equation 5.

As described above, in this example, since the estimation is performed by the equation shown in the equation 5, it is certain that
In addition, CC having different pixel positions with a simple circuit configuration
An estimation calculation between D elements can be realized. It is assumed that the signals supplied to the input terminals 46, 47, ... 50 are obtained by, for example, the flip-flop circuit described in FIG.

The above embodiment is an example of the present invention.
It goes without saying that various other configurations can be adopted without departing from the scope of the present invention.

[0134]

According to the present invention described above, the control means generates a signal indicating the position of the pixel to be corrected among the pixels of the solid-state image pickup element, and the correction means and the plurality of sampling means. The correction signals of the pixels to be corrected are respectively obtained based on the plurality of output signals from the output means, and the output signal or the correction signal from the sampling means is selectively output by the output means based on the control signal from the control means. Therefore, for example, image data such as fine vertical stripes can be reproduced, and thus deterioration of image quality can be prevented.

Further, according to the present invention described above, the outputs from the plurality of solid-state image pickup devices are subjected to correlated double sampling based on the plurality of first and second sample and hold signals from the timing generating means. Therefore, in addition to the above effects, better estimation calculation can be performed.

Further, according to the present invention described above, the control means uses the positions of the correction target pixels of the plurality of solid-state image pickup elements stored in the storage means. It is possible to perform reliable control according to.

Further in the above, according to the present invention, the supply of a plurality of sampling signals to the sampling means is
Since the selection is made by a plurality of selection means based on the control signal from the control means, the execution of sampling can be controlled in addition to the above-mentioned effect, whereby the output by the defective pixel can be surely muted, and the defective pixel can be surely muted. Output is expanded by the pre-processing of sampling and AD conversion, and does not affect the subsequent processing.

Further, according to the present invention described above, the outputs from the plurality of sampling means are converted into digital signals by the plurality of conversion means, and the respective outputs from the plurality of conversion means are delayed by the delay means to make a plurality of conversions. Since the estimation calculation means estimates the correction signal of the correction target pixel based on each output from the means and the control signal from the control means, in addition to the above-described effects, the estimation signal corresponding to the defective pixel is satisfactorily obtained. be able to.

Further, according to the present invention as described above, the estimation calculation means is the third solid-state image pickup device in which the pixel shift is performed with respect to the pixels of the first and second solid-state image pickup devices.
The correction signal of the correction target pixel of the output of the solid-state image sensor is estimated using the output of the first or second solid-state image sensor of the plurality of solid-state image sensors. , Highly accurate estimation can be performed corresponding to the defective pixel of the third solid-state imaging device.

Further, according to the present invention described above, the estimation calculation means estimates the correction signal of the pixel to be corrected of the output of the first solid-state image sensor among the plurality of solid-state image sensors. Since the output of the second solid-state image sensor is used, in addition to the above-described effect, highly accurate estimation can be performed corresponding to the defective pixel of the first solid-state image sensor.

Further, according to the present invention described above, the estimation calculation means estimates the correction signal of the correction target pixel of the output of the second solid-state image pickup device among the plurality of solid-state image pickup devices. Since the output of the first solid-state image sensor is used, in addition to the above-described effects, highly accurate estimation can be performed corresponding to the defective pixel of the second solid-state image sensor.

Furthermore, according to the present invention described above, the estimation calculation means outputs the correction signal of the correction target pixel of the output of one of the solid-state image pickup elements to the output of the other plurality of solid-state image pickup elements. In addition to the above-mentioned effects, S
A good output of / N can be obtained.

Furthermore, according to the present invention described above, the estimation calculation means outputs the correction signal of the pixel to be corrected, which is the output of the third solid-state image pickup element, from among the plurality of solid-state image pickup elements, to the first and second solid-state image pickup elements. In the case of obtaining based on the output of, the higher level is selected, so that in addition to the above-mentioned effect, an output with better S / N can be obtained.

Further, according to the present invention described above, the calculation of the output of the first solid-state image pickup device and the calculation output of the first and second solid-state image pickup devices among the plurality of solid-state image pickup devices is performed by the first calculation means. In the plurality of solid-state image pickup elements, the second calculation means performs the calculation of the output of the second solid-state image pickup element and the calculation outputs of the second and first solid-state image pickup elements. In the third calculation means, the output of the third solid-state image sensor and the average output of the second solid-state image sensor, which are pixel-shifted with respect to the pixels of the first and second solid-state image sensors, are calculated. Since this is done, in addition to the above-mentioned effects, a better estimation can be performed.

Further, according to the present invention described above, the output of the first solid-state image pickup device is latched by the first latch means, and the output from the first latch means is latched by the second latch means, The output of the second solid-state imaging device from the second computing means and the output from the first latching means are multiplied by the multiplying means, and the output from the second latching means and the multiplication output from the multiplying means are divided. Since the calculation is performed by the division means, in addition to the above-mentioned effects, the circuit configuration is simplified and the reliable arithmetic processing can be performed.

Further, according to the present invention described above, the output of the second solid-state image pickup device is latched by the first latch means, and the output from the first latch means is latched by the second latch means. The multiplication of the output of the first solid-state imaging device from the first calculation means and the output from the first latch means is performed by the multiplication means, and the multiplication by the output from the second latch means and the multiplication output from the multiplication means is performed. Since the calculation is performed by the division means, in addition to the above-mentioned effects, the circuit configuration is simplified and the reliable arithmetic processing can be performed.

Further, according to the present invention described above, the output of the third solid-state image pickup device is latched by the first latch means, and the current output of the second solid-state image pickup device from the second arithmetic means and the present output. The previous output is added and averaged by the averaging means, and the average output from this averaging means and the output of the third solid-state imaging device from the first latching means are multiplied by the multiplying means, and the averaging from the averaging means is performed. The output is latched by the second latching means, and the division by the output from the second latching means and the multiplication output from the multiplying means is performed by the dividing means. Is simple, and moreover, reliable arithmetic processing can be performed.

Further, according to the present invention described above, the estimation calculation means sets k as an arbitrary time, and (k-1) is a time immediately before this arbitrary time, and among the plurality of solid-state image pickup elements,
If the output of the first solid-state image sensor is y and the output of the second solid-state image sensor is x, and the output of the second solid-state image sensor corresponding to time k is the output to be corrected, y (k) / Y (k
Since the correction signal of the output to be corrected is obtained by the formula shown by −1) · x (k−1), the estimation process can be simplified in addition to the above effect.

Further, according to the present invention described above, the estimation calculation means has at least two of the outputs of the plurality of solid-state image pickup devices.
The time at which the original image is locally quadratic-applied by applying a quadratic curve to a plurality of neighboring pixels of the pixel corresponding to the output to be corrected using the outputs of the one solid-state image sensor, and the curve takes an extreme value. Is calculated and the correction signal of the output to be corrected is estimated based on the time when the extreme value is obtained with a plurality of neighboring pixels of the pixel corresponding to the output to be corrected. By doing so, the image quality of the output image can be improved.

Further, according to the present invention described above, the estimation calculation means sets k as an arbitrary time, and (k−1) is a time immediately before the arbitrary time, and among the plurality of solid-state image pickup devices,
When the output of the first solid-state image sensor is y and the output of the second solid-state image sensor is x, and the output of the second solid-state image sensor corresponding to time k is an output to be corrected, {x (k + 1 ) +
x (k-1)} / 2-[{x (k + 1) -x (k-
1)} {y (k + 1) + y (k-1) -2y (k)}]
Since the correction signal of the output to be corrected is obtained by the formula shown by / 2 {y (k + 1) -y (k-1)}, the estimation accuracy of the correction signal can be improved in addition to the above effect. .

Further, according to the present invention described above, the output to be corrected by the estimation calculation means using the outputs of at least two solid-state image pickup devices having offsets of at least half a pixel period from the outputs of the plurality of solid-state image pickup devices. A quadratic curve is applied to a plurality of neighboring pixels of the pixel corresponding to, the original image is locally quadratic-approximated, the time when the curve takes an extreme value is obtained, and a plurality of pixels of the pixel corresponding to the output to be corrected are obtained. Since the correction signal of the output to be corrected is estimated based on the time of taking the extreme value with the neighboring pixels, in addition to the above effect, a good correction signal can be obtained even if the pixel position is geometrically displaced. It is possible to obtain good correction and improve the quality of the output image.

Further, according to the present invention described above, the estimation calculation means sets k as an arbitrary time and (k-1) as a time immediately before the arbitrary time, and among the plurality of solid-state image pickup devices,
If the output of the first solid-state image sensor is y and the output of the second solid-state image sensor is x, and the output of the second solid-state image sensor corresponding to time k is an output to be corrected, {x (k + 1 ) +
x (k-1)} / 2-[{x (k + 1) -x (k-
1)} {y (k + 1) + y (k-1) -2y (k)}]
Since the correction signal of the output to be corrected is obtained by the formula shown by / 4 {y (k) -y (k-1)}, the estimation accuracy of the correction signal can be improved in addition to the above effect. .

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 2 is a configuration diagram showing a main part of an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 3 is an explanatory diagram for explaining a first-order estimation used for describing an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 4 is an explanatory diagram showing an example of an output waveform of a CCD element, which is used for explaining an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 5 is an explanatory diagram showing an example of a pixel arrangement and an incident image used for describing an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 6 is a waveform diagram provided for explaining one embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 7 is a configuration diagram showing another example of a main part of an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 8 is an explanatory diagram for explaining the estimation of the correction, which is used in the description of another example of the main part of the embodiment of the correction apparatus for the solid-state imaging device of the present invention.

FIG. 9 is a configuration diagram showing still another example of a main part of an embodiment of a correction device for a solid-state image sensor according to the present invention.

FIG. 10 is an explanatory diagram for explaining the estimation of the correction, which is used for explaining still another example of the main part of the embodiment of the correction apparatus for a solid-state imaging device of the present invention.

[Explanation of symbols]

1, 2, 3 CCD element 4 Timing generation circuit 5, 6, 7 Switch 8, 9, 10 Correlation double sampling circuit 11, 12, 13 A-D converter 14, 15, 16 Delay circuit 17 Estimating arithmetic circuit 18 Defect position Memory 19 Defect position signal generating circuit 20, 22, 24 Switch 27, 28, 33, 34, 41, 43 Flip-flop circuit 29, 35, 42, 52, 55, 56, 58 Multiplying circuit 30, 36, 44, 59 Division circuit 38, 51, 53, 54, 57, 60 Addition circuit

Claims (19)

[Claims] 1. A plurality of sampling means for sampling output signals from a plurality of solid-state image pickup devices, respectively, and a signal indicating a position of a pixel to be corrected in each pixel of the solid-state image pickup device, Control means for generating various control signals corresponding to positions, timing signals for the plurality of solid-state image pickup devices, and sampling signals for the plurality of sampling means based on the control signals from the control means, respectively. Timing generating means for supplying, correcting means for respectively obtaining a correction signal of the pixel to be corrected based on the plurality of output signals from the plurality of sampling means, and the sampling means based on the control signal from the control means Of the solid-state image pickup device, and an output unit for selectively outputting the output signal from the Location. 2. Correlation double for sampling and holding the outputs from the plurality of solid-state image pickup devices based on the plurality of first and second sample and hold signals from the timing generating means. The correction circuit for a solid-state image pickup device according to claim 1, wherein the correction circuit is sampling means. 3. The solid-state image sensor correction apparatus according to claim 1, wherein the control means includes at least a storage means that indicates the position of the correction target pixel of the plurality of solid-state image sensors. 4. The timing generation means includes a plurality of selection means for selecting the supply of the plurality of sampling signals to the sampling means based on a control signal from the control means. A solid-state image sensor correction device as described above. 5. The correction means includes a plurality of conversion means for converting the outputs from the plurality of sampling means into digital signals, a delay means for delaying each output from the plurality of conversion means, and a plurality of the plurality of conversion means. 3. An estimation calculation means for estimating the correction signal of the correction target pixel based on each output from the conversion means and the control signal from the control means.
A solid-state image sensor correction device as described above. 6. The estimation calculation means corrects the output of a third solid-state imaging device, of the plurality of solid-state imaging devices, which is pixel-shifted with respect to pixels of the first and second imaging devices. The correction apparatus for a solid-state image sensor according to claim 5, wherein the correction signal of the target pixel is estimated by using the output of the first or second solid-state image sensor among the plurality of solid-state image sensors. 7. The estimation calculation means estimates the correction signal of the correction target pixel of the output of the first solid-state image pickup device among the plurality of solid-state image pickup devices from among the plurality of solid-state image pickup devices. 7. The solid-state image sensor correction apparatus according to claim 6, wherein the correction is performed using the output of the second solid-state image sensor. 8. The estimation calculation means estimates the correction signal of the correction target pixel of the output of the second solid-state image pickup device among the plurality of solid-state image pickup devices among the plurality of solid-state image pickup devices. 7. The solid-state image sensor correction apparatus according to claim 6, wherein the correction is performed using the output of the solid-state image sensor 1. 9. The estimation calculation means obtains a correction signal of a correction target pixel of an output of one of the plurality of solid-state image pickup devices based on outputs of the other plurality of solid-state image pickup devices. The correction device for a solid-state image pickup device according to claim 5, wherein one having a high level is selected in this case. 10. The estimation calculation means outputs a correction signal of a correction target pixel of an output of a third solid-state imaging device among the plurality of solid-state imaging devices to outputs of the first and second solid-state imaging devices. 7. The correction device for a solid-state image pickup device according to claim 6, wherein a high-level one is selected when obtained based on the above. 11. A first calculation, wherein the estimation calculation means calculates by the output of the first solid-state image sensor and the calculation outputs of the first and second solid-state image sensors of the plurality of solid-state image sensors. Means for calculating the output of the second solid-state imaging device and the outputs of the second and first solid-state imaging devices among the plurality of solid-state imaging devices; A third solid-state image sensor, in which pixel shift is performed with respect to the pixels of the first and second solid-state image sensors.
6. The solid-state image sensor correction device according to claim 5, comprising a third arithmetic means for performing an arithmetic operation based on the output of the solid-state image sensor and the average output of the second solid-state image sensor. 12. The first computing means comprises first latching means for latching an output of the first solid-state imaging device, and second latching means for latching an output from the first latching means. A multiplying unit that multiplies the output of the second solid-state imaging device from the second computing unit and the output from the first latching unit; and an output from the second latching unit and the multiplying unit 7. The correction device for a solid-state image sensor according to claim 6, further comprising: a division unit that performs division with the multiplication output of. 13. The second arithmetic means comprises: first latch means for latching an output of the second solid-state image sensor; and second latch means for latching an output from the first latch means. A multiplying unit that multiplies the output of the first solid-state imaging device from the first computing unit and the output from the first latching unit; and an output from the second latching unit and the multiplying unit 7. The correction device for a solid-state image sensor according to claim 6, further comprising: a division unit that performs division with the multiplication output of. 14. The third arithmetic means is a first latch means for latching an output of the third solid-state imaging device, and a current state of the second solid-state imaging device from the second arithmetic means. An averaging means for adding and averaging the output and the output immediately before the present time, and a multiplying means for multiplying the average output from the averaging means and the output of the third solid-state imaging device from the first latch means. And second latching means for latching the average output from the averaging means, and division means for performing division by the output from the second latching means and the multiplication output from the multiplying means. The solid-state image sensor correction device according to claim 6. 15. The estimation calculation means sets an arbitrary time as k and a time immediately before the arbitrary time as (k−1), and selects a first one of the plurality of solid-state image pickup devices.
Let y be the output of the solid-state image sensor and x be the output of the second solid-state image sensor, and if the output of the second solid-state image sensor corresponding to time k is the output to be corrected, then y (k) / 6. The correction device for a solid-state image pickup device according to claim 5, wherein the correction signal of the output to be corrected is obtained by an expression represented by y (k-1) .x (k-1). 16. The estimation calculation means uses outputs of at least two solid-state image pickup devices out of outputs of the plurality of solid-state image pickup devices, with respect to a plurality of neighboring pixels of a pixel corresponding to the output to be corrected. Then, a quadratic curve is applied to locally quadratic approximate the original image, the time at which the curve takes an extreme value is determined, and a plurality of neighboring pixels of the pixel corresponding to the output to be corrected and the time at which the extreme value is taken. The correction device for a solid-state image pickup device according to claim 5, wherein the correction signal of the output to be corrected is estimated based on the above. 17. The estimation calculation means sets an arbitrary time as k and a time immediately before the arbitrary time as (k−1), and selects a first one of the plurality of solid-state imaging devices.
Let y be the output of the solid-state image sensor of, and x be the output of the second solid-state image sensor, and if the output of the second solid-state image sensor corresponding to time k is the output to be corrected, {x (k + 1) + X (k-1)} / 2-[{x (k + 1) -x (k-1)} {y (k + 1) + y (k-1) -2y (k)}] / 2 {y (k + 1)- The correction device for a solid-state image pickup device according to claim 5, wherein a correction signal of the output to be corrected is obtained by an expression represented by y (k-1)}. 18. The estimation calculation means corresponds to the output to be corrected by using the outputs of at least two solid-state image pickup devices having an offset of at least a half pixel period among the outputs of the plurality of solid-state image pickup devices. A quadratic curve is applied to a plurality of neighboring pixels of the pixel to locally quadratic approximate the original image, the time when the curve takes an extreme value is obtained, and a plurality of neighborhoods of the pixel corresponding to the output to be corrected are obtained. The correction apparatus for a solid-state image pickup device according to claim 5, wherein the correction signal of the output to be corrected is estimated based on a pixel and a time when the extreme value is obtained. 19. The estimation calculation means sets an arbitrary time to k.
The time immediately before this arbitrary time is defined as (k−1), and the output of the first solid-state image sensor is y and the output of the second solid-state image sensor is x among the plurality of solid-state image sensors. When the output of the second solid-state imaging device corresponding to time k is an output to be corrected, {x (k + 1) + x (k-1)} / 2-[{x (k + 1) -x ( k-1)} {y (k + 1) + y (k-1) -2y (k)}] / 4 {y (k) -y (k-1)} The correction signal of the output to be corrected by the formula The correction device for a solid-state image pickup device according to claim 5, wherein