JP4099010B2

JP4099010B2 - Signal processing circuit

Info

Publication number: JP4099010B2
Application number: JP2002187943A
Authority: JP
Inventors: 保福島; 勝次國末
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 2002-06-27
Filing date: 2002-06-27
Publication date: 2008-06-11
Anticipated expiration: 2022-06-27
Also published as: JP2004032514A

Description

【０００１】
【発明の属する技術分野】
本発明は信号処理回路に関し、より特定的には、いわゆる空間画素ずらし法が採用された固体撮像装置で特に有彩色の被写体を撮像した場合に生じるモアレ現象を抑圧するための信号処理回路に関する。
【０００２】
【従来の技術】
いわゆる３板式の固体撮像装置では、Ｒ（赤），Ｇ（緑），Ｂ（青）の各色用の固体撮像素子（例えばＣＣＤ（ＣｈａｒｇｅＣｏｕｐｌｅｄＤｅｖｉｃｅ））が光学的に映像信号をサンプリングする際に、折り返し歪み（エリアシング）が発生する。
【０００３】
ここで、固体撮像素子が光学的に映像信号をサンプリングする際のサンプリング周波数ｆｓが十分高くない場合、折り返し歪が映像信号帯域内に入り込み、再生画像中にモアレを発生させて画質を劣化させる。すなわち、図１１に示すように、固体撮像素子が光学的にサンプリングする映像信号が波形ａで示す周波数特性を有する場合、サンプリング周波数ｆｓの半分の周波数０．５ｆｓに対して対称的に、波形ｂで示すような折り返し歪みが発生する。原信号ａと折り返し歪みｂは同じ帯域内に重なって存在するため、その両者を分離する事は難しい。
【０００４】
図１１の波形ｂで示すような折り返し歪を低減する方法としては、従来、テレビジョンカメラ装置におけるマトリクス演算機能を用いた、いわゆる「空間画素ずらし」と呼ばれる方法が知られている。この方法では図１２に示すように、例えばＧチャンネルのＣＣＤの受光部（撮像部）の各画素を、ＲチャンネルおよびＢチャンネルのＣＣＤの受光部（撮像部）の各画素に対して、水平走査方向の画素間隔Ｐｘの１／２だけ水平走査方向にずらして配置する。
【０００５】
このように各ＣＣＤを配置することにより、ＲチャンネルおよびＢチャンネルの映像信号の位相がＧチャンネルの映像信号に対してそれぞれ１８０度ずれる。その結果、図１１の波形ｂおよび波形ｃで示すように、ＲチャンネルおよびＢチャンネルについて発生する折り返し歪の位相も、Ｇチャンネルについて発生する折り返し歪みの位相に対してそれぞれ１８０度ずれることになる。
【０００６】
ここで、Ｇ，Ｒ，Ｂの信号をマトリクス演算することにより得られる輝度信号Ｙは、例えば下記の式で表わされる。
Ｙ＝０．５９Ｇ＋０．３０Ｒ＋０．１１Ｂ
ここで、上記の式におけるＧ，Ｒ，Ｂは、それぞれＧチャンネル，Ｒチャンネル，Ｂチャンネルの信号レベルを示す。なお、これらＧチャンネル，Ｒチャンネル，Ｂチャンネルの白レベル（白基準位レベル）のレベル比（白レベル比）は同一（つまり１対１対１）であるとする。
【０００７】
従って、このマトリクス演算により得られる輝度信号Ｙについては、Ｇチャンネルの折り返し歪成分（図１１の波形ｂで示される）と、それとは逆位相のＲチャンネルおよびＢチャンネルの折り返し歪成分（図１１の波形ｃで示される）とが部分的にキャンセルされ、その結果、折り返し歪成分が低減することになる。しかしながらこの場合には、図１１の波形ｄで示される輝度信号Ｙの折返し歪成分Ｙｄが、下記の式が示すように輝度信号Ｙの１８％だけ残ってしまう。
Ｙｄ＝Ｇ―Ｒ―Ｂ＝０．５９―０．３０―０．１１＝０．１８
【０００８】
そこで、映像信号をより高解像度にする方法として、輝度信号の高域成分についてのみマトリクス比を代える方法がある。例えば次の式
ＹＨ＝０．５Ｇ＋０．５Ｒ
により高域輝度信号ＹＨを算出すれば、Ｇ信号（Ｇチャンネルの映像信号）とＲ信号（Ｒチャンネルの映像信号）の比が１：１であるため、折り返し歪成分はキャンセルされる。特にＧ信号とＲ信号の信号レベルが等しい場合には折り返し歪成分は完全にキャンセルされる。
【０００９】
また例えば高域輝度信号ＹＨを次の式
ＹＨ＝０．５Ｇ＋０．３Ｒ＋０．２Ｂ
により算出しても、Ｇ信号と、Ｒ信号およびＢ信号を足し合わせた信号との比が１：１であるため、折り返し歪成分はキャンセルされる。特にＧ信号とＲ信号とＢ信号の信号レベルが等しい場合には折り返し歪成分は完全にキャンセルされる。
【００１０】
【発明が解決しようとする課題】
しかしながら上記の方法では、Ｇ信号と、Ｒ信号および／またはＢ信号とにより折り返し歪成分をキャンセルしているので、彩度の高い被写体については、その効果を十分に得ることができない。例えば赤色の被写体の場合には、Ｒ信号と比較してＧ信号が非常に小さいので、折り返し歪み成分の打ち消し効果が弱くなり、映像の再生時にモアレ現象が画面に強く現れてしまう。
【００１１】
それゆえに本発明の目的は、空間画素ずらし法が採用された固体撮像装置で特に有彩色の被写体を撮像した場合に生じるモアレ現象を抑圧するための信号処理回路を提供することである。また本発明の他の目的は、この信号処理回路の回路規模の増大を抑制することである。
【００１２】
【課題を解決するための手段および発明の効果】
本発明は、上記の目的を達成するために、以下のように構成される。ただし、括弧内の参照符号等は、本発明の理解を助けるために示したものであって、本発明を何ら限定するものではない。
本発明の信号処理回路は、空間画素ずらし法が採用された固体撮像装置において生成された映像信号を処理するためのものであって、固体撮像装置において生成された第１〜第３の映像信号（実施形態との対応関係を示せば、例えばＲ信号，Ｇ信号，Ｂ信号）がそれぞれ入力され、これら第１〜第３の映像信号の低周波領域（Ｒ１Ｌ，Ｇ１Ｌ，Ｂ１Ｌ）をそれぞれ通過させる第１〜第３のローパスフィルタ（１１Ｒ，１１Ｇ，１１Ｂ）と、少なくとも第１および第２の映像信号に基づいて、折り返し雑音を低減した高域信号（ＹＨ１）を生成する高域信号処理回路（５０ａ）と、高域信号処理回路によって生成された高域信号を、第１〜第３のローパスフィルタの出力信号（Ｒ１Ｌ，Ｇ１Ｌ，Ｂ１Ｌ）にそれぞれ加算する第１〜第３の加算器（１５Ｒ，１５Ｇ，１５Ｂ）とを備え、高域信号処理回路は、少なくとも第１および第２の映像信号の信号レベルに基づいて高域信号の信号レベルを調整するゲイン制御回路（５３ａ）を含み、ゲイン制御回路は、高域信号に含まれる折り返し雑音の低減度合いが小さいほど高域信号の信号レベルが小さくなるように、高域信号の信号レベルを調整することを特徴とする。これにより、少なくとも第１および第２の映像信号の信号レベルに基づいて高域信号の信号レベルを適宜に調整することが可能となり、その結果、空間画素ずらしの効果が十分に得られない彩度の強い画像において、モアレの発生を抑圧することができる。
【００１３】
なお、上記のゲイン制御回路の説明において「少なくとも第１および第２の映像信号の信号レベルに基づいて高域信号の信号レベルを調整する」とあるが、これは、第１および第２の映像信号自体に限らず、例えばローパスフィルタを通過後の第１および第２の映像信号に基づいて高域信号の信号レベルを調整する場合も含まれる。
【００１４】
また、本発明の信号処理回路は、固体撮像装置の内部に設けられても構わないし、固体撮像装置の外部に独立して設けられても構わない。
【００１５】
【発明の実施の形態】
以下、本発明の種々の実施形態について、図面を参照して説明する。
（第１の実施形態）
図１に、本発明の第１の実施形態に係る信号処理回路の構成を示す。図１において、入力端子１Ｒ，１Ｇ，１Ｂには、図示しないＣＣＤなどの固体撮像素子からの撮像信号に、相関二重サンプリング（ＣＤＳ）やオフセット調整やゲイン調整などの信号処理が施されたアナログ映像信号Ｒ０，Ｇ０，Ｂ０がそれぞれ入力される。なおここでは、上記の固体撮像素子には前述の空間画素ずらし法が適用されており、Ｇチャンネルの固体撮像素子の受光部（撮像部）の各画素が、ＲチャンネルおよびＢチャンネルの固体撮像素子の受光部（撮像部）の各画素に対して、水平走査方向の画素間隔の１／２だけ水平走査方向にずらして配置されているものとする。
【００１６】
アナログ映像信号Ｒ０，Ｇ０，Ｂ０は、それぞれ、Ａ／Ｄ（アナログ・ディジタル）変換回路１０Ｒ，１０Ｇ，１０Ｂにおいてディジタル信号Ｒ１，Ｇ１，Ｂ１へと変換され、ローパスフィルタ（ＬＰＦ）１１Ｒ，１１Ｇ，１１Ｂにおいて映像信号の低域成分のみが取り出される。Ａ／Ｄ変換回路１０Ｒ，１０Ｇの出力信号Ｒ１，Ｇ１は、それぞれ、高域信号処理回路５０ａにおけるハイパスフィルタ（ＨＰＦ）５１Ｒ，５１Ｇにも入力され、Ｒ信号およびＧ信号の高域成分のみが取り出される。なお、一般的には各ローパスフィルタとハイパスフィルタの通過特性は相互補完となる特性とし、この両者の出力信号を加算すれば、元の入力信号が復元されるような特性とする。
【００１７】
ハイパスフィルタ５１Ｒ，５１Ｇの出力である、Ｒ信号およびＧ信号の高域成分は、平均回路５２において両者の加算平均が演算される。なお、平均回路５２は、例えば加算器とビットシフタから構成することができる。これらハイパスフィルタ５１Ｒ，５１Ｇおよび平均回路５２によって、折り返し雑音が低減された高域信号ＹＨ０が生成されることになる。この高域信号ＹＨ０は、ゲイン制御回路５３ａにおいてそのゲインを制御された後、高域信号ＹＨ１として、加算器１５Ｒ，１５Ｇ，１５Ｂへと出力される。加算器１５Ｒ，１５Ｇ，１５Ｂでは、ローパスフィルタ１１Ｒ，１１Ｇ，１１Ｂの出力であるＲＧＢ各チャンネルの映像信号の低域成分Ｒ１Ｌ，Ｇ１Ｌ，Ｂ１Ｌに、高域信号処理回路５０ａの出力である共通の高域信号ＹＨ１がそれぞれ加算され、ディジタルプロセス回路１６へと供給される。
【００１８】
ディジタルプロセス回路１６では、ガンマ補正やニー補正や輪郭強調処理など、カメラに必要なディジタル信号処理が行われる。さらに、マトリクス変換回路１７では、ＲＧＢの３原色信号から例えばＹＰｂＰｒといった輝度色差信号へ変換するためのマトリクス変換処理が行われ、その変換結果が、Ｄ／Ａ（ディジタル・アナログ）変換回路１８およびパラレル・シリアル（Ｐ／Ｓ）変換回路１９へと出力する。Ｄ／Ａ変換回路１８では、ディジタル信号をアナログ信号へと変換し、出力端子２Ｙ、２Ｐｂ、２Ｐｒと出力し、Ｐ／Ｓ変換回路１９では、ディジタル信号がパラレル／シリアル変換され、ディジタル・シリアル信号として、出力端子３へと出力される。
【００１９】
ここで、高域信号処理回路５０ａにおけるゲイン制御回路５３ａの構成と動作について詳細に説明する。判定回路１０１には、ローパスフィルタ１１Ｒ，１１Ｇの出力信号Ｒ１Ｌ，Ｇ１Ｌが入力される。判定回路１０１では、入力された信号Ｒ１Ｌと信号Ｇ１Ｌの大小関係が判定され、レベルの高い方が信号Ｌ、低い方が信号Ｓとして出力される。すなわち、Ｒ１Ｌ≧Ｇ１Ｌの場合には、Ｌ＝Ｒ１Ｌ、Ｓ＝Ｇ１Ｌとなり、Ｒ１Ｌ＜Ｇ１Ｌの場合には、Ｌ＝Ｇ１Ｌ、Ｓ＝Ｒ１Ｌとなる。
【００２０】
除算器１０２では、判定回路１０１から出力された信号Ｌおよび信号Ｓに対して、Ｓ／Ｌの除算処理が行われ、信号Ｒ１Ｌと信号Ｇ１Ｌの比Ｋｒが求められる。さらに、ゲイン生成回路１０３では、比ＫｒからゲインＫＧが生成され、乗算器１０４へと出力される。乗算器１０４では、ゲイン制御回路５３ａに入力される高域信号ＹＨ０に対してゲインＫＧが乗算され、高域信号ＹＨ１が生成される。
【００２１】
図２に、ゲイン生成回路１０３の入出力特性の例を示す。
特性ａは、ＫＧ＝Ｋｒであり、Ｇ信号とＲ信号の比に比例して共通高域信号のゲインＫＧを制御する場合の例を示している。
Ｋｒ＝１、すなわちＲ１Ｌ＝Ｇ１Ｌの場合には、Ｒ信号とＧ信号はほぼ等しい振幅レベル（白色に近い画像）であるため、高域信号ＹＨ０（＝０．５Ｒ１Ｌ＋０．５Ｇ１Ｌ）に含まれるＧ信号とＲ信号の比がほぼ１：１となり、折り返し歪成分はほとんどキャンセルされる。つまり、Ｋｒ＝１の場合には空間画素ずらしの効果が十分に発揮されるので、モアレ現象が問題になることはない。したがって、この場合には共通高域信号のゲインＫＧを１とし、ゲイン制御回路５３ａに入力された高域信号をそのまま出力する。
一方、極端な例として、Ｋｒ＝０、すなわちＲ１Ｌ＝０またはＧ１Ｌ＝０の場合には、Ｒ信号およびＧ信号のいずれか一方しか存在しない（原色に近い画像）ので、折り返し歪成分はキャンセルされない。つまり、Ｋｒ＝０の場合には空間画素ずらしの効果を全く得ることができないので、ゲイン制御回路５３ａに入力された高域信号をそのまま出力してしまうとモアレ現象が大きく問題となる。したがって、この場合には共通高域信号のゲインＫＧを０とし、ゲイン制御回路５３ａからは高域信号を全く出力しない（言い換えると、信号レベルが０の高域信号ＹＨ１を出力する）。
Ｋｒの値が上記以外の場合には、Ｋｒの値が小さいほどゲインＫＧを小さくし、ゲイン制御回路５３ａから出力される共通高域信号ＹＨ１のレベルを小さくする。
【００２２】
図３に、信号Ｒ１Ｌ，Ｇ１Ｌに対するゲインＫＧの出力特性を等高線状に示す。Ｒ１Ｌ＝Ｇ１Ｌの場合にはＫＧ＝１となり、Ｒ１Ｌ＝０、またはＧ１Ｌ＝０の場合には、ＫＧ＝０となることがわかる。また、直線Ｒ１Ｌ＝Ｇ１Ｌから離れる（これは被写体の彩度が強まることに相当する）に従い、ゲインＫＧは１から小さな値となる。このように、モアレが目立つような原色に近い画像になるほど共通高域信号のゲインを小さくすることにより、モアレの発生を抑圧している。
【００２３】
なお、図２に示す特性ａは単なる一例であって、本発明はこれに限らない。例えば、図２の特性ｂのように、比Ｋｒが１に近い場合には、ゲインＫＧを１に保つようにしてもよい。これにより、Ｒ信号とＧ信号のバランスが多少異なる場合にも、共通高域信号のゲインを１に保つことができる。
【００２４】
以上のように、第１の実施形態によれば、Ｒ信号とＧ信号のレベルの比に応じて共通高域信号のゲインを変化させるので、特に空間画素ずらしの効果が十分に得られない彩度の強い画像において、モアレの発生を抑圧することができる。
【００２５】
なお、本実施形態では、ハイパスフィルタ５１Ｒ，５１Ｇおよび平均回路５２によって、折り返し雑音が低減された高域信号ＹＨ０が生成される場合について説明したが、本発明はこれに限らず、他の方法により高域信号ＹＨ０を生成しても構わない。例えば、ハイパスフィルタによって映像信号Ｒ１，Ｇ１，Ｂ１の高域成分Ｒ１Ｈ，Ｇ１Ｈ，Ｂ１Ｈをそれぞれ取り出し、これら高域成分を用いて、高域信号ＹＨ０を、ＹＨ０＝０．５Ｇ１Ｈ＋０．３Ｒ１Ｈ＋０．２Ｂ１Ｈにより演算しても構わない。この場合、ゲイン制御回路５３ａにおいて、０．５Ｇ１Ｌと、０．３Ｒ１Ｌ＋０．２Ｂ１Ｌとの比Ｋｒに基づいてゲインＫＧを決定するようにすれば、本実施形態と同様の効果を得ることができる。
【００２６】
（第２の実施形態）
図４に、本発明の第２の実施形態に係る信号処理回路の構成を示す。なお図４において、図１に示した第１の実施形態と同様の部分については同一の参照符号を付し、詳しい説明を省略する。
【００２７】
第２の実施形態では、図４に示す高域信号処理回路５０ｂにおけるゲイン制御回路５３ｂの構成が、図１に示した第１の実施形態のゲイン制御回路５３ａとは異なっている。具体的には、判定回路１０１と乗算器１０４については第１の実施形態と同様であるが、減算器１０５を有することと、ゲイン生成回路１０６の入出力特性が第１の実施形態とは異なる。
【００２８】
判定回路１０１は、第１の実施形態と同じく、入力された信号Ｒ１Ｌと信号Ｇ１Ｌの大小関係を判定し、レベルの高い方を信号Ｌ、低い方を信号Ｓとして出力する。次に、減算器１０５は、Ｌ−Ｓの減算処理を行い、信号Ｒ１Ｌと信号Ｇ１Ｌの信号差Ｋｄを求める。さらに、ゲイン生成回路１０６は、信号差ＫｄからゲインＫＧを生成し、乗算器１０４へと出力する。乗算器１０４は、ゲイン制御回路５３ｂに入力される高域信号ＹＨ０に対してゲインＫＧを乗算して、高域信号ＹＨ１を生成する。
【００２９】
図５に、ゲイン生成回路１０６の入出力特性の例を示す。ただし、ここで信号差Ｋｄは、信号Ｒ１Ｌと信号Ｇ１Ｌを各々最大値を１に正規化した値について演算したものとする。
特性ａは、ＫＧ＝１−Ｋｄであり、Ｇ信号とＲ信号の差に対応して共通高域信号のゲインＫＧを制御する場合の例を示している。
Ｋｄ＝０、すなわちＲ１Ｌ＝Ｇ１Ｌの場合には、Ｒ信号とＧ信号はほぼ等しい振幅レベル（白色に近い画像）である。そこで、空間画素ずらしの効果が十分に発揮されるので、共通高域信号のゲインＫＧを１とし、ゲイン制御回路５３ｂに入力された高域信号をそのまま出力する。
一方、極端な例として、Ｋｄ＝１、すなわちＲ１Ｌ＝０かつＧ１Ｌ＝１、またはＧ１Ｌ＝０かつＲ１Ｌ＝１の場合には、Ｒ信号およびＧ信号のいずれか一方しか存在しない（原色に近い画像）。そこで、空間画素ずらしの効果を得ることができないので、共通高域信号のゲインＫＧを０とし、ゲイン制御回路５３ｂからは高域信号を全く出力しない。
Ｋｄの値が上記以外の場合には、Ｋｄの値が大きいほどゲインＫＧを小さくし、ゲイン制御回路５３ｂから出力される共通高域信号ＹＨ１のレベルを小さくする。
【００３０】
図６に、信号Ｒ１Ｌ，Ｇ１Ｌに対するゲインＫＧの出力特性を等高線状に示す。Ｒ１Ｌ＝Ｇ１Ｌの場合にはＫＧ＝１となり、Ｒ１Ｌ＝０かつＧ１Ｌ＝１、またはＧ１Ｌ＝０かつＲ１Ｌ＝１の場合には、ＫＧ＝０となることがわかる。また、直線Ｒ１Ｌ＝Ｇ１Ｌから離れる（これは被写体の彩度が強まる事に相当する）に従い、ゲインＫＧは１から小さな値となる。このように、モアレが目立つような原色に近い画像になるほど共通高域信号のゲインを小さくすることにより、モアレの発生を抑圧している。
【００３１】
本実施形態では、信号Ｒ１Ｌや信号Ｇ１Ｌが０に近い場合（画像が暗い場合）に、第１の実施形態とは異なる効果を得ることができる。すなわち、第１の実施形態では、図３に示したように、信号Ｒ１Ｌや信号Ｇ１Ｌが０に近い場合にＫＧの等値線が接近しているので、ノイズの影響等によりＫＧが大きく変動することとなる。しかしながら、本実施形態では、図６に示すように、信号Ｒ１Ｌや信号Ｇ１Ｌが０に近い場合でもＫＧの等値線が接近していないので、ノイズの影響等を受けにくい。
【００３２】
なお、図５に示す特性ａは単なる一例であって、本発明はこれに限らない。例えば、図５の特性ｂのように、差Ｋｄが０に近い場合には、ゲインＫＧを１に保つようにしてもよい。これにより、Ｒ信号とＧ信号のバランスが多少異なる場合にも、共通高域信号のゲインを１に保つことができる。
【００３３】
以上のように、第２の実施形態によれば、Ｒ信号とＧ信号のレベルの差に応じて共通高域信号のゲインを変化させるので、特に空間画素ずらしの効果が十分に得られない彩度の強い画像において、モアレの発生を抑圧することができる。また特に、第１の実施形態で用いた除算器の代わりに減算器を用いてゲイン制御回路を構成しているので、第１の実施形態に比べて回路規模の増大を抑制することができる。さらに、Ｒ信号やＧ信号が０に近い、すなわち暗い被写体の時に、ノイズ等に対してゲインＫＧが多大に影響されない構成とすることができる。
【００３４】
なお、本実施形態では、ハイパスフィルタ５１Ｒ，５１Ｇおよび平均回路５２によって、折り返し雑音が低減された高域信号ＹＨ０が生成される場合について説明したが、本発明はこれに限らず、他の方法により高域信号ＹＨ０を生成しても構わない。例えば、ハイパスフィルタによって映像信号Ｒ１，Ｇ１，Ｂ１の高域成分Ｒ１Ｈ，Ｇ１Ｈ，Ｂ１Ｈをそれぞれ取り出し、これら高域成分を用いて、高域信号ＹＨ０を、ＹＨ０＝０．５Ｇ１Ｈ＋０．３Ｒ１Ｈ＋０．２Ｂ１Ｈにより演算しても構わない。この場合、ゲイン制御回路５３ｂにおいて、０．５Ｇ１Ｌと、０．３Ｒ１Ｌ＋０．２Ｂ１Ｌとの差Ｋｄに基づいてゲインＫＧを決定するようにすれば、本実施形態と同様の効果を得ることができる。
【００３５】
（第３の実施形態）
図７に、本発明の第３の実施形態に係る信号処理回路の構成を示す。なお図７において、図４に示した第２の実施形態と同様の部分については同一の参照符号を付し、詳しい説明を省略する。
【００３６】
第３の実施形態では、図７に示す高域信号処理回路５０ｃにおけるゲイン制御回路５３ｃの構成が、図４に示した第２の実施形態のゲイン制御回路５３ｂとは異なっている。具体的には、判定回路１０１、乗算器１０４および減算器１０５については第２の実施形態と同様であるが、加算器１０７を有すること、ゲイン生成回路１０８の入出力特性が第２の実施形態とは異なる。
【００３７】
判定回路１０１は、第２の実施形態と同じく、入力された信号Ｒ１Ｌと信号Ｇ１Ｌの大小関係を判定し、レベルの高い方を信号Ｌ、低い方を信号Ｓとして出力する。次に、減算器１０５は、Ｌ−Ｓの減算処理を行い、信号Ｒ１Ｌと信号Ｇ１Ｌの信号差Ｋｄを求める。また、加算器１０７は、Ｌ＋Ｓの加算処理を行い、信号Ｒ１Ｌと信号Ｇ１Ｌの信号和Ｋｓを求める。さらに、ゲイン生成回路１０８は、信号差Ｋｄおよび信号和ＫｓからゲインＫＧを生成し、乗算器１０４へと出力する。乗算器１０４は、ゲイン制御回路５３ｃに入力される高域信号ＹＨ０に対してゲインＫＧを乗算して、高域信号ＹＨ１を生成する。
【００３８】
ゲイン生成回路１０８は、信号差Ｋｄおよび信号和ＫｓからゲインＫＧを演算するが、その入出力特性は、例えばＫＧ＝１−Ｋｄ（２−Ｋｓ）とする。図８に、この入出力特性を示す。ただし、ここで信号差Ｋｄおよび信号和Ｋｓは、信号Ｒ１Ｌと信号Ｇ１Ｌを各々最大値を１に正規化した値について演算したものとする。また、ゲインＫＧはＫｄとＫｓの二つのパラメータを有するので、図８では横軸をＫｄとして、代表例としていくつかのＫｓに対してその特性を示している。なお、図８に示す入出力特性は単なる一例であって、本発明はこれに限らない。
【００３９】
図８から明らかなように、ゲイン生成回路１０８の出力ＫＧは、信号差Ｋｄが０の場合は１であり、信号差Ｋｄが大きくなるに従ってその値は１から小さくなる。なお、信号差Ｋｄに対する減少度合いは、信号和Ｋｓが大きいほど緩やかで、信号和Ｋｓが小さいほど急になる。
【００４０】
図９に、信号Ｒ１Ｌ，Ｇ１Ｌに対するゲインＫＧの出力特性を等高線状に示す。Ｒ１Ｌ＝Ｇ１Ｌの場合（すなわち被写体が無彩色で画素ずらしの効果が大きい場合）には、ＫＧ＝１となる。また、直線Ｒ１Ｌ＝Ｇ１Ｌから離れる（被写体の彩度が強まることに相当）に従い、ゲインＫＧは１から小さな値となる。
【００４１】
本実施形態では、図９に示したように、高輝度部では第１の実施形態に近い特性を、低輝度部では第２の実施形態に近い特性を有する。これは、画素ずらしの効果が十分に出ない有彩色の被写体において、特にモアレが目立つ高輝度時には、モアレの混在する高域信号を十分に抑圧することを意味する。また、低輝度時、すなわち図９における左下に近い領域では、ゲインＫＧの等値線が平行に近くなり、あまり接近していない。すなわち、第２の実施形態と同様に、ノイズや誤差によりゲインＫＧが不用に大きく変動することがない。また、除算処理を用いていないので、回路規模の増大が抑えられることは言うまでもない。
【００４２】
以上のように、第３の実施形態によれば、Ｒ信号とＧ信号のレベルの差および和に応じて共通高域信号のゲインを変化させるので、特に空間画素ずらしの効果が十分に得られない彩度の強い画像において、モアレの発生を抑圧することができる。また特に、第１の実施形態で用いた除算器の代わりに減算器および加算器を用いてゲイン制御回路を構成しているので、第１の実施形態に比べて回路規模の増大を抑制することができる。さらに、特に高輝度時において第１の実施形態とほぼ同様のモアレ抑圧効果を得ることができると同時に、Ｒ信号やＧ信号が０に近い、すなわち暗い被写体の時に、ノイズや誤差等に対してゲインＫＧが多大に影響されない構成とすることができる。
【００４３】
なお、本実施形態では、ハイパスフィルタ５１Ｒ，５１Ｇおよび平均回路５２によって、折り返し雑音が低減された高域信号ＹＨ０が生成される場合について説明したが、本発明はこれに限らず、他の方法により高域信号ＹＨ０を生成しても構わない。例えば、ハイパスフィルタによって映像信号Ｒ１，Ｇ１，Ｂ１の高域成分Ｒ１Ｈ，Ｇ１Ｈ，Ｂ１Ｈをそれぞれ取り出し、これら高域成分を用いて、高域信号ＹＨ０を、ＹＨ０＝０．５Ｇ１Ｈ＋０．３Ｒ１Ｈ＋０．２Ｂ１Ｈにより演算しても構わない。この場合、ゲイン制御回路５３ｃにおいて、０．５Ｇ１Ｌと、０．３Ｒ１Ｌ＋０．２Ｂ１Ｌとの差Ｋｄおよび和Ｋｓに基づいてゲインＫＧを決定するようにすれば、本実施形態と同様の効果を得ることができる。
【００４４】
（第４の実施形態）
上記第１〜第３の実施形態では、Ｒ信号の高域成分（Ｒ１Ｈ）およびＧ信号の高域成分（Ｇ１Ｈ）に基づいて、ＹＨ０＝０．５Ｒ１Ｈ＋０．５Ｇ１Ｈという関係式により共通高域信号（ＹＨ０）を生成していた。しかしながらこの場合、Ｒ信号が少ないシアン系の映像について、空間画素ずらしの効果が十分に得られないという欠点がある。そこで、第４の実施形態では、Ｒ信号が少ないシアン系の映像については、Ｂ信号の高域成分（Ｂ１Ｈ）およびＧ信号の高域成分（Ｇ１Ｈ）に基づいて、ＹＨ０＝０．５Ｂ１Ｈ＋０．５Ｇ１Ｈという関係式により高域信号（ＹＨ０）を生成することで、上記欠点を解決する。以下、この第４の実施形態について説明する。
【００４５】
図１０に、本発明の第４の実施形態に係る信号処理回路の構成を示す。なお図１０において、図７に示した第３の実施形態と同様の部分については同一の参照符号を付し、詳しい説明を省略する。
【００４６】
第４の実施形態では、図１０に示す高域信号処理回路５０ｄの構成が、図７に示した第３の実施形態の高域信号処理回路５０ｃとは異なっている。具体的には、ハイパスフィルタ５１Ｒ，５１Ｇに加えて、ハイパスフィルタ５１Ｂが存在し、さらにセレクタ５４を有することが第３の実施形態とは異なる。さらに、ゲイン制御回路５３ｄにおいて、図７に示した判定回路１０１の代わりに、判定回路１１０が設けられている点が第３の実施形態とは異なる。
【００４７】
図１０において、Ａ／Ｄ変換回路１０Ｒ，１０Ｇ，１０Ｂの出力信号Ｒ１，Ｇ１，Ｂ１は、それぞれ、高域信号処理回路５０ｄにおけるハイパスフィルタ（ＨＰＦ）５１Ｒ，５１Ｇ，５１Ｂに入力され、ＲＧＢ各信号の高域成分のみが取り出される。ハイパスフィルタ５１Ｒ，５１Ｂの出力であるＲ信号およびＢ信号の高域成分はセレクタ５４へと入力され、後述する判定回路１１０の出力である選択信号ＶＳＥＬに基づいていずれか一方の信号が選択されてセレクタ５４から出力される。セレクタ５４の出力信号は、ハイパスフィルタ５１Ｇの出力であるＧ信号の高域成分と共に平均回路５２へと入力され、両者の加算平均が演算される。
【００４８】
ゲイン制御回路５３ｄの判定回路１１０にはＲＧＢ各信号の低域成分Ｒ１Ｌ，Ｇ１Ｌ，Ｂ１Ｌが入力され、所定の判断基準に基づいてＲ信号（Ｒ１Ｌ）およびＢ信号（Ｂ１Ｌ）からいずれか一方の信号が選択される。判定回路１１０は、その選択結果を選択信号ＶＳＥＬによってセレクタ５４へ供給すると共に、選択したＲ，Ｂいずれかの信号とＧ信号（Ｇ１Ｌ）との大小関係を判定し、レベルの高い方をＬ信号、低い方をＳ信号として出力する。
【００４９】
判定回路１１０の出力である信号Ｌおよび信号Ｓは、第３の実施形態と同様の処理が施され、その結果、ゲインＫＧが決定される。乗算器１０４では、ゲイン制御回路５３ｄに入力される高域信号ＹＨ０に対して、ゲインＫＧが乗算され、高域信号ＹＨ１が生成される。
【００５０】
判定回路１１０においてＲ，Ｂいずれの信号を選択するかの判断基準としては、例えばＲおよびＢ信号のうち信号レベルの大きい方を選択する方法がある。これにより、無彩色から大きく外れた被写体においても、その色相に関わらず信号レベルの大きい信号から高域信号を生成することができる。すなわち、Ｒ信号の少ないシアン系の被写体や照明が存在するような映像においても、Ｂ信号およびＧ信号に基づいて共通高域信号を生成することで、画素ずらしの目的であるモアレ抑圧効果を大きくすることができる。
【００５１】
また、判定回路１１０においてＲ，Ｂいずれの信号を選択するかを判断するときに、単純にＲ信号とＢ信号の信号レベルを比較するのではなく、各信号に２倍や３倍の重み付けをして比較してもよい。例えば、Ｂ信号レベルがＲ信号レベルの２倍より大きい時はＢ信号を選択し、それ以下の時はＲ信号を選択するという方法がある。一般的にＲ信号よりＢ信号の方がノイズ成分が多いので、Ｂ信号から高域信号ＹＨ０を生成するとＳ／Ｎが不利となる。そこで、Ｂ信号がＲ信号に比べて十分な差を持って大きい時にのみ高域信号の源信号とすることで、Ｓ／Ｎの低下を抑えることができる。
【００５２】
なお、本実施形態では、第３の実施形態と同様に、映像信号の差および和に基づいてゲインＫＧを決定するとしたが、本発明はこれに限らない。つまり、第１の実施形態あるいは第２の実施形態のように、映像信号の比あるいは差のみに基づいてゲインＫＧを決定する場合にも、本実施形態と同様の効果を得ることができる。
【００５３】
以上のように、第４の実施形態では、Ｒ信号が少ないときにはＢ信号とＧ信号に基づいて高域信号を生成するので、Ｒ信号が少ないシアン系の映像についても、空間画素ずらしの効果を十分に得ることができる。
【００５４】
なお、以上の第１〜第４の実施形態の説明では、Ｇチャンネルの固体撮像素子（例えばＣＣＤ）を、Ｒ，Ｂチャンネルの固体撮像素子（例えばＣＣＤ）に対して、水平走査方向の画素間隔Ｐｘの１／２だけ水平走査方向にずらして配置した場合について述べたが、本発明はこれに限らず、一般的に、少なくとも２つの映像信号に基づいて折り返し雑音を低減した高域信号を生成することができるように配置された固体撮像素子からの撮像信号に対して本発明を適用することができる。
【００５５】
また、第１〜第４の実施形態では、判定回路への入力としてローパスフィルタの出力信号を用いたが、Ａ／Ｄ変換回路の出力信号を用いてもよい。あるいは、別個のローパスフィルタを設けてその出力信号を用いてもよい。例えば図１の例では、ゲイン制御回路５３ａは、Ａ／Ｄ変換回路１０Ｒ，１０Ｇの出力信号Ｒ１，Ｇ１に基づいてゲインＫＧを決定しても構わないし、さらには、Ａ／Ｄ変換回路１０Ｒ，１０Ｇの出力信号Ｒ１，Ｇ１を新たに設けた２つのローパスフィルタに供給し、この２つのローパスフィルタの出力信号に基づいてゲインＫＧを決定しても構わない。判定回路への入力としてローパスフィルタの出力信号を用いると、ＲＧＢ各信号のレベルの変動に対してゲインＫＧの値が過敏に反応するのを避けることができる。
【００５６】
また、第１〜第４の実施形態では、ハイパスフィルタおよびローパスフィルタを別個に設ける構成としたが、本発明はこれに限らず、例えば、もとの信号からローパスフィルタの出力を減算するような回路をハイパスフィルタとして設けてもよい。例えば図１の例では、ハイパスフィルタ５１Ｒの代わりに、Ａ／Ｄ変換回路１０Ｒの出力信号Ｒ１からローパスフィルタ１１Ｒの出力信号Ｒ１Ｌを減算する回路を設けてもよい。
【００５７】
また、第１〜第４の実施形態では、各映像信号に高域信号を加算するための加算器をディジタルプロセス回路の前段に配置したが、本発明はこれに限らず、ガンマ変換回路あるいはニー回路の後段に加算器を配置してもよい。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る信号処理回路の構成を示すブロック図である。
【図２】第１の実施形態におけるゲイン生成回路の入出力特性図である。
【図３】第１の実施形態におけるゲイン制御回路の制御特性図である。
【図４】本発明の第２の実施形態に係る信号処理回路の構成を示すブロック図である。
【図５】第２の実施形態におけるゲイン生成回路の入出力特性図である。
【図６】第２の実施形態におけるゲイン制御回路の制御特性図である。
【図７】本発明の第３の実施形態に係る信号処理回路の構成を示すブロック図である。
【図８】第３の実施形態におけるゲイン生成回路の入出力特性図である。
【図９】第３の実施形態におけるゲイン制御回路の制御特性図である。
【図１０】本発明の第４の実施形態に係る信号処理回路の構成を示すブロック図である。
【図１１】映像信号と折り返し歪みの相対利得の周波数特性を示す図である。
【図１２】空間画素ずらし法が採用された固体撮像装置における各チャンネルの撮像部間の関係を説明するための図である。
【符号の説明】
１Ｒ、１Ｇ、１Ｂ入力端子
２Ｙ、２Ｐｂ、２Ｐｒ出力端子
３出力端子
１０Ｒ、１０Ｇ、１０ＢＡ／Ｄ変換回路
１１Ｒ、１１Ｇ、１１Ｂローパスフィルタ
１５Ｒ、１５Ｇ、１５Ｂ加算器
１６ディジタルプロセス回路
１７マトリクス変換回路
１８Ｄ／Ａ変換回路
１９パラレル・シリアル変換回路
５０ａ、５０ｂ、５０ｃ、５０ｄ高域信号処理回路
５１Ｒ、５１Ｇ、５１Ｂハイパスフィルタ
５２平均回路
５３ａ、５３ｂ、５３ｃ、５４ｄゲイン制御回路
５４セレクタ
１０１、１１０判定回路
１０２除算器
１０３、１０６、１０８ゲイン生成回路
１０４乗算器
１０５減算器
１０７加算器[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a signal processing circuit, and more particularly to a signal processing circuit for suppressing a moiré phenomenon that occurs particularly when a chromatic subject is imaged by a solid-state imaging device employing a so-called spatial pixel shifting method.
[0002]
[Prior art]
In a so-called three-plate type solid-state imaging device, a solid-state imaging device (for example, a CCD (Charge Coupled Device)) for each color of R (red), G (green), and B (blue) optically samples a video signal. , Aliasing occurs.
[0003]
Here, when the sampling frequency fs when the solid-state imaging device optically samples the video signal is not sufficiently high, aliasing distortion enters the video signal band, and moire is generated in the reproduced image to deteriorate the image quality. That is, as shown in FIG. 11, when the video signal optically sampled by the solid-state imaging device has the frequency characteristic indicated by the waveform a, the waveform b is symmetrical with respect to the frequency 0.5fs which is half the sampling frequency fs. Folding distortion as shown in FIG. Since the original signal a and the aliasing distortion b overlap in the same band, it is difficult to separate them.
[0004]
As a method for reducing the aliasing distortion as shown by the waveform b in FIG. 11, a so-called “spatial pixel shift” method using a matrix calculation function in a television camera device is conventionally known. In this method, as shown in FIG. 12, for example, each pixel of the light receiving unit (imaging unit) of the G channel CCD is horizontally scanned with respect to each pixel of the light receiving unit (imaging unit) of the R channel and B channel CCD. The pixels are arranged while being shifted in the horizontal scanning direction by 1/2 of the pixel interval Px in the direction.
[0005]
By arranging the CCDs in this way, the phase of the R channel and B channel video signals is shifted by 180 degrees with respect to the G channel video signal. As a result, as shown by the waveform b and the waveform c in FIG. 11, the phase of the aliasing distortion generated for the R channel and the B channel is also shifted by 180 degrees with respect to the phase of the aliasing distortion generated for the G channel.
[0006]
Here, the luminance signal Y obtained by performing a matrix operation on the G, R, and B signals is represented by the following equation, for example.
Y = 0.59G + 0.30R + 0.11B
Here, G, R, and B in the above equations indicate the signal levels of the G channel, R channel, and B channel, respectively. It is assumed that the level ratio (white level ratio) of the white level (white reference level) of the G channel, R channel, and B channel is the same (that is, one-to-one to one).
[0007]
Therefore, with respect to the luminance signal Y obtained by this matrix operation, the G channel aliasing distortion component (shown by the waveform b in FIG. 11) and the R channel and B channel aliasing distortion components (in FIG. (Shown by the waveform c) is partially canceled, and as a result, the aliasing distortion component is reduced. However, in this case, the aliasing distortion component Yd of the luminance signal Y indicated by the waveform d in FIG. 11 remains as much as 18% of the luminance signal Y as indicated by the following equation.
Yd = GRB = 0.59-0.30-0.11 = 0.18
[0008]
Therefore, as a method of increasing the resolution of the video signal, there is a method of changing the matrix ratio only for the high frequency component of the luminance signal. For example, the expression
YH = 0.5G + 0.5R
If the high-frequency luminance signal YH is calculated by the above, the ratio of the G signal (G channel video signal) to the R signal (R channel video signal) is 1: 1, so that the aliasing distortion component is cancelled. In particular, when the signal levels of the G signal and the R signal are equal, the aliasing distortion component is completely canceled.
[0009]
For example, the high-frequency luminance signal YH is expressed by the following formula:
YH = 0.5G + 0.3R + 0.2B
, The ratio of the G signal to the sum of the R signal and the B signal is 1: 1, so that the aliasing distortion component is cancelled. In particular, when the signal levels of the G signal, the R signal, and the B signal are equal, the aliasing distortion component is completely canceled.
[0010]
[Problems to be solved by the invention]
However, in the above method, since the aliasing distortion component is canceled by the G signal, the R signal, and / or the B signal, the effect cannot be sufficiently obtained for a subject with high saturation. For example, in the case of a red subject, since the G signal is very small compared to the R signal, the effect of canceling the aliasing distortion component is weakened, and the moire phenomenon appears strongly on the screen during video reproduction.
[0011]
Therefore, an object of the present invention is to provide a signal processing circuit for suppressing a moire phenomenon that occurs particularly when a chromatic subject is imaged by a solid-state imaging device employing a spatial pixel shifting method. Another object of the present invention is to suppress an increase in circuit scale of the signal processing circuit.
[0012]
[Means for Solving the Problems and Effects of the Invention]
In order to achieve the above object, the present invention is configured as follows. However, reference numerals and the like in parentheses are shown to help understanding of the present invention, and do not limit the present invention.
A signal processing circuit according to the present invention is for processing a video signal generated in a solid-state imaging device employing a spatial pixel shifting method, and includes first to third video signals generated in the solid-state imaging device. (If the correspondence with the embodiment is shown, for example, R signal, G signal, and B signal) are input, and the low frequency regions (R1L, G1L, B1L) of these first to third video signals are respectively passed. A high-frequency signal processing circuit that generates a high-frequency signal (YH1) with reduced aliasing noise based on the first to third low-pass filters (11R, 11G, and 11B) and at least the first and second video signals. 50a) and first to third adders for adding the high-frequency signal generated by the high-frequency signal processing circuit to the output signals (R1L, G1L, B1L) of the first to third low-pass filters, respectively. 15R, 15G, 15B) and provided with a high-frequency signal processing circuit, including a gain control circuit for adjusting the signal level of the high frequency signal (53a) based on the signal level of the at least first and second video signals Therefore, the gain control circuit adjusts the signal level of the high frequency signal so that the signal level of the high frequency signal becomes smaller as the degree of reduction of the aliasing noise included in the high frequency signal becomes smaller. It is characterized by that. This makes it possible to appropriately adjust the signal level of the high-frequency signal based on at least the signal levels of the first and second video signals, and as a result, saturation that does not provide a sufficient effect of shifting the spatial pixels. It is possible to suppress the occurrence of moire in a strong image.
[0013]
In the above description of the gain control circuit, there is “adjust the signal level of the high frequency signal based on at least the signal levels of the first and second video signals”. For example, the signal level of the high frequency signal is adjusted based on the first and second video signals after passing through the low-pass filter.
[0014]
Moreover, the signal processing circuit of the present invention may be provided inside the solid-state imaging device, or may be provided independently outside the solid-state imaging device.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, various embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 shows a configuration of a signal processing circuit according to the first embodiment of the present invention. In FIG. 1, input terminals 1R, 1G, and 1B are analog signals obtained by subjecting an imaging signal from a solid-state imaging device such as a CCD (not shown) to signal processing such as correlated double sampling (CDS), offset adjustment, and gain adjustment. Video signals R0, G0, and B0 are input, respectively. Here, the above-described spatial pixel shifting method is applied to the above-described solid-state imaging device, and each pixel of the light-receiving unit (imaging unit) of the G-channel solid-state imaging device has R-channel and B-channel solid-state imaging devices. It is assumed that the pixels of the light receiving unit (imaging unit) are shifted in the horizontal scanning direction by 1/2 of the pixel interval in the horizontal scanning direction.
[0016]
Analog video signals R0, G0, B0 are converted into digital signals R1, G1, B1 in A / D (analog / digital) conversion circuits 10R, 10G, 10B, respectively, and low-pass filters (LPF) 11R, 11G, 11B. Only the low frequency component of the video signal is extracted. The output signals R1 and G1 of the A / D conversion circuits 10R and 10G are also input to high-pass filters (HPF) 51R and 51G in the high-frequency signal processing circuit 50a, respectively, and only the high-frequency components of the R signal and the G signal are extracted. It is. In general, the pass characteristics of each low-pass filter and high-pass filter are mutually complementary characteristics, and the output signals of both are added to restore the original input signal.
[0017]
For the high frequency components of the R signal and the G signal, which are the outputs of the high pass filters 51R and 51G, the averaging circuit 52 calculates the addition average of both. The averaging circuit 52 can be composed of an adder and a bit shifter, for example. The high pass filters 51R and 51G and the averaging circuit 52 generate a high frequency signal YH0 with reduced aliasing noise. The high frequency signal YH0 is output to the adders 15R, 15G, and 15B as the high frequency signal YH1 after the gain is controlled by the gain control circuit 53a. In the adders 15R, 15G, and 15B, the low-frequency components R1L, G1L, and B1L of the RGB channel video signals that are the outputs of the low-pass filters 11R, 11G, and 11B are shared with the high-frequency signal processing circuit 50a. The band signals YH1 are added and supplied to the digital process circuit 16.
[0018]
The digital process circuit 16 performs digital signal processing necessary for the camera, such as gamma correction, knee correction, and edge enhancement processing. Further, the matrix conversion circuit 17 performs matrix conversion processing for converting RGB three primary color signals into luminance color difference signals such as YPbPr. The conversion result is converted into a D / A (digital / analog) conversion circuit 18 and a parallel signal. Output to serial (P / S) conversion circuit 19 The D / A conversion circuit 18 converts the digital signal into an analog signal and outputs it as output terminals 2Y, 2Pb, 2Pr, and the P / S conversion circuit 19 performs parallel / serial conversion of the digital signal to obtain a digital / serial signal. Is output to the output terminal 3.
[0019]
Here, the configuration and operation of the gain control circuit 53a in the high frequency signal processing circuit 50a will be described in detail. The determination circuit 101 receives the output signals R1L and G1L of the low-pass filters 11R and 11G. The determination circuit 101 determines the magnitude relationship between the input signal R1L and the signal G1L, and the higher level is output as the signal L and the lower level is output as the signal S. That is, when R1L ≧ G1L, L = R1L and S = G1L, and when R1L <G1L, L = G1L and S = R1L.
[0020]
In the divider 102, S / L division processing is performed on the signal L and the signal S output from the determination circuit 101, and a ratio Kr of the signal R1L and the signal G1L is obtained. Further, the gain generation circuit 103 generates a gain KG from the ratio Kr and outputs it to the multiplier 104. In the multiplier 104, the high frequency signal YH0 input to the gain control circuit 53a is multiplied by the gain KG to generate a high frequency signal YH1.
[0021]
FIG. 2 shows an example of input / output characteristics of the gain generation circuit 103.
The characteristic a shows an example in which KG = Kr and the gain KG of the common high frequency signal is controlled in proportion to the ratio of the G signal and the R signal.
When Kr = 1, that is, R1L = G1L, the R signal and the G signal have substantially the same amplitude level (image close to white), and therefore the G signal included in the high frequency signal YH0 (= 0.5R1L + 0.5G1L). And the ratio of the R signal is approximately 1: 1, and the aliasing distortion component is almost canceled. That is, when Kr = 1, the effect of shifting the spatial pixels is sufficiently exerted, so that the moire phenomenon does not become a problem. Accordingly, in this case, the gain KG of the common high frequency signal is set to 1, and the high frequency signal input to the gain control circuit 53a is output as it is.
On the other hand, as an extreme example, when Kr = 0, that is, when R1L = 0 or G1L = 0, only one of the R signal and the G signal exists (an image close to the primary color), and the aliasing distortion component is not canceled. . In other words, when Kr = 0, the effect of shifting the spatial pixels cannot be obtained at all. Therefore, if the high frequency signal input to the gain control circuit 53a is output as it is, the moire phenomenon becomes a serious problem. Accordingly, in this case, the gain KG of the common high frequency signal is set to 0, and no high frequency signal is output from the gain control circuit 53a (in other words, the high frequency signal YH1 having a signal level of 0 is output).
When the value of Kr is other than the above, the gain KG is decreased as the value of Kr is decreased, and the level of the common high-frequency signal YH1 output from the gain control circuit 53a is decreased.
[0022]
FIG. 3 shows the output characteristics of the gain KG with respect to the signals R1L and G1L in contour lines. It can be seen that KG = 1 when R1L = G1L, and KG = 0 when R1L = 0 or G1L = 0. Further, as the distance from the straight line R1L = G1L increases (this corresponds to an increase in the saturation of the subject), the gain KG decreases from 1. Thus, the occurrence of moire is suppressed by reducing the gain of the common high-frequency signal as the image becomes closer to the primary color where the moire is conspicuous.
[0023]
The characteristic a shown in FIG. 2 is merely an example, and the present invention is not limited to this. For example, the gain KG may be kept at 1 when the ratio Kr is close to 1 as in the characteristic b of FIG. As a result, even when the balance between the R signal and the G signal is slightly different, the gain of the common high frequency signal can be kept at 1.
[0024]
As described above, according to the first embodiment, the gain of the common high-frequency signal is changed in accordance with the ratio of the level of the R signal and the G signal. It is possible to suppress the occurrence of moire in a strong image.
[0025]
In the present embodiment, the case where the high-pass signal YH0 with reduced aliasing noise is generated by the high-pass filters 51R and 51G and the averaging circuit 52 has been described. However, the present invention is not limited to this, and other methods are used. The high frequency signal YH0 may be generated. For example, high-frequency components R1H, G1H, and B1H of the video signals R1, G1, and B1 are extracted by a high-pass filter, and the high-frequency signal YH0 is calculated by YH0 = 0.5G1H + 0.3R1H + 0.2B1H using these high-frequency components. It doesn't matter. In this case, if the gain control circuit 53a determines the gain KG based on the ratio Kr between 0.5G1L and 0.3R1L + 0.2B1L, the same effect as in the present embodiment can be obtained.
[0026]
(Second Embodiment)
FIG. 4 shows a configuration of a signal processing circuit according to the second embodiment of the present invention. In FIG. 4, the same parts as those in the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0027]
In the second embodiment, the configuration of the gain control circuit 53b in the high-frequency signal processing circuit 50b shown in FIG. 4 is different from the gain control circuit 53a of the first embodiment shown in FIG. Specifically, the determination circuit 101 and the multiplier 104 are the same as those in the first embodiment, but the subtractor 105 is included and the input / output characteristics of the gain generation circuit 106 are different from those in the first embodiment. .
[0028]
As in the first embodiment, the determination circuit 101 determines the magnitude relationship between the input signal R1L and the signal G1L, and outputs the higher level as the signal L and the lower level as the signal S. Next, the subtractor 105 performs an LS subtraction process to obtain a signal difference Kd between the signal R1L and the signal G1L. Further, the gain generation circuit 106 generates a gain KG from the signal difference Kd and outputs it to the multiplier 104. The multiplier 104 multiplies the high frequency signal YH0 input to the gain control circuit 53b by the gain KG to generate a high frequency signal YH1.
[0029]
FIG. 5 shows an example of input / output characteristics of the gain generation circuit 106. Here, it is assumed that the signal difference Kd is calculated with respect to values obtained by normalizing the signal R1L and the signal G1L to 1 respectively.
The characteristic a is KG = 1−Kd, and shows an example in the case of controlling the gain KG of the common high frequency signal corresponding to the difference between the G signal and the R signal.
When Kd = 0, that is, R1L = G1L, the R signal and the G signal have substantially the same amplitude level (image close to white). Therefore, since the effect of shifting the spatial pixels is sufficiently exhibited, the gain KG of the common high frequency signal is set to 1, and the high frequency signal input to the gain control circuit 53b is output as it is.
On the other hand, as an extreme example, when Kd = 1, that is, when R1L = 0 and G1L = 1, or G1L = 0 and R1L = 1, only one of the R signal and the G signal exists (an image close to the primary color). ). Therefore, since the effect of shifting the spatial pixels cannot be obtained, the gain KG of the common high frequency signal is set to 0, and no high frequency signal is output from the gain control circuit 53b.
When the value of Kd is other than the above, the gain KG is decreased as the value of Kd is increased, and the level of the common high-frequency signal YH1 output from the gain control circuit 53b is decreased.
[0030]
FIG. 6 shows the output characteristics of the gain KG with respect to the signals R1L and G1L in contour lines. It can be seen that KG = 1 when R1L = G1L, and KG = 0 when R1L = 0 and G1L = 1, or G1L = 0 and R1L = 1. Further, as the distance from the straight line R1L = G1L increases (this corresponds to an increase in the saturation of the subject), the gain KG decreases from 1. Thus, the occurrence of moire is suppressed by reducing the gain of the common high-frequency signal as the image becomes closer to the primary color where the moire is conspicuous.
[0031]
In the present embodiment, when the signal R1L and the signal G1L are close to 0 (when the image is dark), an effect different from that of the first embodiment can be obtained. That is, in the first embodiment, as shown in FIG. 3, when the signal R1L and the signal G1L are close to 0, the KG isolines are approaching, so that the KG varies greatly due to the influence of noise and the like. It will be. However, in the present embodiment, as shown in FIG. 6, even when the signal R1L and the signal G1L are close to 0, the KG isolines are not approaching, so that they are not easily affected by noise.
[0032]
The characteristic a shown in FIG. 5 is merely an example, and the present invention is not limited to this. For example, the gain KG may be kept at 1 when the difference Kd is close to 0 as in the characteristic b of FIG. As a result, even when the balance between the R signal and the G signal is slightly different, the gain of the common high frequency signal can be kept at 1.
[0033]
As described above, according to the second embodiment, the gain of the common high-frequency signal is changed in accordance with the difference between the levels of the R signal and the G signal. It is possible to suppress the occurrence of moire in a strong image. In particular, since the gain control circuit is configured using a subtracter instead of the divider used in the first embodiment, an increase in circuit scale can be suppressed as compared with the first embodiment. Furthermore, when the R signal and G signal are close to 0, that is, in a dark subject, the gain KG can be prevented from being greatly affected by noise or the like.
[0034]
In the present embodiment, the case where the high-pass signal YH0 with reduced aliasing noise is generated by the high-pass filters 51R and 51G and the averaging circuit 52 has been described. However, the present invention is not limited to this, and other methods are used. The high frequency signal YH0 may be generated. For example, high-frequency components R1H, G1H, and B1H of the video signals R1, G1, and B1 are extracted by a high-pass filter, and the high-frequency signal YH0 is calculated by YH0 = 0.5G1H + 0.3R1H + 0.2B1H using these high-frequency components. It doesn't matter. In this case, if the gain control circuit 53b determines the gain KG based on the difference Kd between 0.5G1L and 0.3R1L + 0.2B1L, the same effect as in the present embodiment can be obtained.
[0035]
(Third embodiment)
FIG. 7 shows a configuration of a signal processing circuit according to the third embodiment of the present invention. In FIG. 7, the same parts as those in the second embodiment shown in FIG. 4 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0036]
In the third embodiment, the configuration of the gain control circuit 53c in the high-frequency signal processing circuit 50c shown in FIG. 7 is different from the gain control circuit 53b of the second embodiment shown in FIG. Specifically, the determination circuit 101, the multiplier 104, and the subtractor 105 are the same as those in the second embodiment, but include the adder 107 and the input / output characteristics of the gain generation circuit 108 in the second embodiment. Is different.
[0037]
As in the second embodiment, the determination circuit 101 determines the magnitude relationship between the input signal R1L and the signal G1L, and outputs the higher level as the signal L and the lower level as the signal S. Next, the subtractor 105 performs an LS subtraction process to obtain a signal difference Kd between the signal R1L and the signal G1L. The adder 107 performs an L + S addition process to obtain a signal sum Ks of the signal R1L and the signal G1L. Further, the gain generation circuit 108 generates a gain KG from the signal difference Kd and the signal sum Ks and outputs the gain KG to the multiplier 104. The multiplier 104 multiplies the high frequency signal YH0 input to the gain control circuit 53c by the gain KG to generate a high frequency signal YH1.
[0038]
The gain generation circuit 108 calculates the gain KG from the signal difference Kd and the signal sum Ks, and the input / output characteristics thereof are, for example, KG = 1−Kd (2-Ks). FIG. 8 shows the input / output characteristics. Here, it is assumed that the signal difference Kd and the signal sum Ks are calculated with respect to values obtained by normalizing the signal R1L and the signal G1L to 1 respectively. Since the gain KG has two parameters, Kd and Ks, in FIG. 8, the horizontal axis is Kd, and the characteristic is shown for several Ks as a representative example. The input / output characteristics shown in FIG. 8 are merely examples, and the present invention is not limited to this.
[0039]
As is apparent from FIG. 8, the output KG of the gain generation circuit 108 is 1 when the signal difference Kd is 0, and the value decreases from 1 as the signal difference Kd increases. Note that the degree of decrease with respect to the signal difference Kd is more gradual as the signal sum Ks is larger, and becomes steeper as the signal sum Ks is smaller.
[0040]
FIG. 9 shows the output characteristics of the gain KG with respect to the signals R1L and G1L in contour lines. When R1L = G1L (that is, when the subject is achromatic and the effect of pixel shifting is large), KG = 1. Further, as the distance from the straight line R1L = G1L (corresponding to increasing the saturation of the subject), the gain KG becomes a small value from 1.
[0041]
In the present embodiment, as shown in FIG. 9, the high luminance portion has characteristics close to those of the first embodiment, and the low luminance portion has characteristics similar to those of the second embodiment. This means that a high-frequency signal mixed with moire is sufficiently suppressed in a chromatic color subject in which the effect of pixel shifting is not sufficiently produced, particularly at high luminance where moire is conspicuous. Further, at the time of low luminance, that is, in the region near the lower left in FIG. 9, the isolines of the gain KG are nearly parallel and are not so close. That is, as in the second embodiment, the gain KG does not fluctuate unnecessarily greatly due to noise or error. Further, since division processing is not used, it goes without saying that an increase in circuit scale can be suppressed.
[0042]
As described above, according to the third embodiment, since the gain of the common high-frequency signal is changed according to the difference and sum of the levels of the R signal and the G signal, the effect of shifting the spatial pixels can be sufficiently obtained. It is possible to suppress the occurrence of moire in an image having no strong saturation. In particular, since the gain control circuit is configured by using a subtractor and an adder instead of the divider used in the first embodiment, an increase in circuit scale can be suppressed as compared with the first embodiment. Can do. Furthermore, it is possible to obtain the same moire suppression effect as in the first embodiment, particularly at high luminance, and at the same time, against noise and errors when the R signal and G signal are close to 0, that is, in a dark subject. A configuration in which the gain KG is not greatly affected can be achieved.
[0043]
In the present embodiment, the case where the high-pass signal YH0 with reduced aliasing noise is generated by the high-pass filters 51R and 51G and the averaging circuit 52 has been described. However, the present invention is not limited to this, and other methods are used. The high frequency signal YH0 may be generated. For example, high-frequency components R1H, G1H, and B1H of the video signals R1, G1, and B1 are extracted by a high-pass filter, and the high-frequency signal YH0 is calculated by YH0 = 0.5G1H + 0.3R1H + 0.2B1H using these high-frequency components. It doesn't matter. In this case, if the gain control circuit 53c determines the gain KG based on the difference Kd and the sum Ks between 0.5G1L and 0.3R1L + 0.2B1L, the same effect as in this embodiment can be obtained. it can.
[0044]
(Fourth embodiment)
In the first to third embodiments, based on the high frequency component (R1H) of the R signal and the high frequency component (G1H) of the G signal, the common high frequency signal (YH0 = 0.5R1H + 0.5G1H) YH0). However, in this case, there is a drawback that the effect of shifting the spatial pixels cannot be sufficiently obtained for a cyan image with a small R signal. Therefore, in the fourth embodiment, for a cyan video with a small R signal, YH0 = 0.5B1H + 0.5G1H based on the high frequency component (B1H) of the B signal and the high frequency component (G1H) of the G signal. The above drawback is solved by generating a high-frequency signal (YH0) according to the relational expression: The fourth embodiment will be described below.
[0045]
FIG. 10 shows a configuration of a signal processing circuit according to the fourth embodiment of the present invention. In FIG. 10, the same parts as those in the third embodiment shown in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.
[0046]
In the fourth embodiment, the configuration of the high frequency signal processing circuit 50d shown in FIG. 10 is different from that of the high frequency signal processing circuit 50c of the third embodiment shown in FIG. Specifically, the high-pass filter 51B is present in addition to the high-pass filters 51R and 51G, and a selector 54 is provided, which is different from the third embodiment. Further, the gain control circuit 53d is different from the third embodiment in that a determination circuit 110 is provided instead of the determination circuit 101 shown in FIG.
[0047]
In FIG. 10, output signals R1, G1, and B1 of A / D conversion circuits 10R, 10G, and 10B are input to high-pass filters (HPF) 51R, 51G, and 51B in a high-frequency signal processing circuit 50d, respectively, and RGB signals Only the high frequency components of are extracted. The high-frequency components of the R and B signals that are the outputs of the high-pass filters 51R and 51B are input to the selector 54, and one of the signals is selected based on the selection signal VSEL that is the output of the determination circuit 110 described later. Output from the selector 54. The output signal of the selector 54 is input to the averaging circuit 52 together with the high frequency component of the G signal that is the output of the high pass filter 51G, and the addition average of both is calculated.
[0048]
The low frequency components R1L, G1L, and B1L of the RGB signals are input to the determination circuit 110 of the gain control circuit 53d, and one of the R signal (R1L) and the B signal (B1L) is input based on a predetermined determination criterion. Is selected. The determination circuit 110 supplies the selection result to the selector 54 by the selection signal VSEL, determines the magnitude relationship between the selected signal R or B and the G signal (G1L), and determines the higher level as the L signal. The lower one is output as the S signal.
[0049]
The signal L and the signal S that are the outputs of the determination circuit 110 are subjected to the same processing as in the third embodiment, and as a result, the gain KG is determined. In the multiplier 104, the high frequency signal YH0 input to the gain control circuit 53d is multiplied by the gain KG to generate a high frequency signal YH1.
[0050]
As a criterion for determining which signal R or B is to be selected in the determination circuit 110, for example, there is a method of selecting the higher signal level of the R and B signals. As a result, a high frequency signal can be generated from a signal having a high signal level regardless of the hue of a subject greatly deviated from the achromatic color. That is, even in an image where there is a cyan subject or illumination with a small R signal, a common high-frequency signal is generated based on the B signal and the G signal, so that the moire suppression effect that is the purpose of pixel shifting is greatly increased. can do.
[0051]
Further, when determining which signal R or B is selected in the determination circuit 110, the signal level of the R signal and the B signal is not simply compared, but each signal is weighted twice or three times. You may compare. For example, there is a method of selecting the B signal when the B signal level is larger than twice the R signal level and selecting the R signal when the B signal level is lower than the R signal level. In general, since the B signal has more noise components than the R signal, the S / N becomes disadvantageous when the high-frequency signal YH0 is generated from the B signal. Therefore, a decrease in S / N can be suppressed by using a high-frequency signal as a source signal only when the B signal is large enough with a sufficient difference from the R signal.
[0052]
In the present embodiment, as in the third embodiment, the gain KG is determined based on the difference and sum of video signals. However, the present invention is not limited to this. That is, as in the first embodiment or the second embodiment, even when the gain KG is determined based only on the ratio or difference of the video signals, the same effect as in this embodiment can be obtained.
[0053]
As described above, in the fourth embodiment, when the R signal is small, the high-frequency signal is generated based on the B signal and the G signal. You can get enough.
[0054]
In the above description of the first to fourth embodiments, the G-channel solid-state imaging device (for example, CCD) is arranged in the horizontal scanning direction with respect to the R and B-channel solid-state imaging devices (for example, CCD). Although the case where it is arranged by shifting in the horizontal scanning direction by 1/2 of Px has been described, the present invention is not limited to this, and in general, a high frequency signal with reduced aliasing noise is generated based on at least two video signals. The present invention can be applied to an imaging signal from a solid-state imaging device arranged so as to be able to.
[0055]
In the first to fourth embodiments, the output signal of the low-pass filter is used as the input to the determination circuit, but the output signal of the A / D conversion circuit may be used. Alternatively, a separate low-pass filter may be provided and the output signal may be used. For example, in the example of FIG. 1, the gain control circuit 53a may determine the gain KG based on the output signals R1 and G1 of the A / D conversion circuits 10R and 10G, and further, the A / D conversion circuit 10R, The 10G output signals R1 and G1 may be supplied to two newly provided low-pass filters, and the gain KG may be determined based on the output signals of the two low-pass filters. When the output signal of the low-pass filter is used as an input to the determination circuit, it is possible to avoid the sensitivity of the gain KG value to the fluctuation of the level of each RGB signal.
[0056]
In the first to fourth embodiments, the high-pass filter and the low-pass filter are separately provided. However, the present invention is not limited to this. For example, the output of the low-pass filter is subtracted from the original signal. The circuit may be provided as a high pass filter. For example, in the example of FIG. 1, a circuit that subtracts the output signal R1L of the low-pass filter 11R from the output signal R1 of the A / D conversion circuit 10R may be provided instead of the high-pass filter 51R.
[0057]
In the first to fourth embodiments, the adder for adding the high frequency signal to each video signal is arranged in the preceding stage of the digital process circuit. However, the present invention is not limited to this, and the gamma conversion circuit or the knee is added. An adder may be arranged after the circuit.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a signal processing circuit according to a first embodiment of the present invention.
FIG. 2 is an input / output characteristic diagram of a gain generation circuit according to the first embodiment.
FIG. 3 is a control characteristic diagram of a gain control circuit according to the first embodiment.
FIG. 4 is a block diagram showing a configuration of a signal processing circuit according to a second embodiment of the present invention.
FIG. 5 is an input / output characteristic diagram of a gain generation circuit according to a second embodiment.
FIG. 6 is a control characteristic diagram of a gain control circuit according to the second embodiment.
FIG. 7 is a block diagram showing a configuration of a signal processing circuit according to a third embodiment of the present invention.
FIG. 8 is an input / output characteristic diagram of a gain generation circuit according to a third embodiment.
FIG. 9 is a control characteristic diagram of a gain control circuit according to a third embodiment.
FIG. 10 is a block diagram showing a configuration of a signal processing circuit according to a fourth embodiment of the present invention.
FIG. 11 is a diagram illustrating frequency characteristics of a relative gain of a video signal and aliasing distortion;
FIG. 12 is a diagram for explaining a relationship between imaging units of respective channels in a solid-state imaging device adopting a spatial pixel shifting method.
[Explanation of symbols]
1R, 1G, 1B input terminals
2Y, 2Pb, 2Pr output terminals
3 Output terminals
10R, 10G, 10B A / D conversion circuit
11R, 11G, 11B Low-pass filter
15R, 15G, 15B Adder
16 Digital process circuit
17 Matrix conversion circuit
18 D / A converter circuit
19 Parallel-serial conversion circuit
50a, 50b, 50c, 50d High frequency signal processing circuit
51R, 51G, 51B High-pass filter
52 Average circuit
53a, 53b, 53c, 54d Gain control circuit
54 selector
101, 110 judgment circuit
102 Divider
103, 106, 108 Gain generation circuit
104 multiplier
105 Subtractor
107 adder

Claims

A signal processing circuit for processing a video signal generated in a solid-state imaging device employing a spatial pixel shifting method,
First to third low-pass filters that receive the first to third video signals generated in the solid-state imaging device and pass through the low-frequency regions of the first to third video signals, respectively.
A high-frequency signal processing circuit that generates a high-frequency signal with reduced aliasing noise based on at least the first and second video signals;
A first to a third adder for respectively adding the high-frequency signal generated by the high-frequency signal processing circuit to the output signals of the first to third low-pass filters;
The high frequency signal processing circuit, saw including a gain control circuit for adjusting the signal level of the high frequency signal based on the signal level of at least the first and second video signals,
The gain control circuit adjusts the signal level of the high-frequency signal so that the signal level of the high-frequency signal decreases as the degree of reduction of the aliasing noise included in the high-frequency signal decreases. Processing circuit.

The high-frequency signal processing circuit averages the outputs of the first and second high-pass filters that pass through the high-frequency regions of the first and second video signals and the outputs of the first and second high-pass filters, The signal processing circuit according to claim 1, further comprising an averaging circuit that outputs an addition average result as the high-frequency signal.

The gain control circuit has a multiplier for multiplying the output signal of the averaging circuit by a gain,
The signal processing circuit according to claim 2 , wherein the gain is determined based on a ratio of signal levels of the first and second video signals.

4. The signal processing circuit according to claim 3 , wherein the signal level ratio is calculated by a divider.

The gain control circuit further includes a determination circuit that compares and determines the signal levels of the first and second video signals.
4. The signal processing circuit according to claim 3 , wherein a ratio Kr of signal levels of the first and second video signals is calculated so that Kr ≦ 1 based on a determination result of the determination circuit. 5. .

The gain is calculated according to KG = K0 × Kr (K0 is a constant), where Kr is a ratio of signal levels of the first and second video signals and KG is the gain. Item 6. The signal processing circuit according to Item 5 .

4. The signal processing circuit according to claim 3 , wherein the gain is determined based on a ratio of signal levels of output signals of the first and second low-pass filters.

The gain control circuit has a multiplier for multiplying the output signal of the averaging circuit by a gain,
The signal processing circuit according to claim 2 , wherein the gain is determined based on a difference between signal levels of the first and second video signals.

9. The signal processing circuit according to claim 8, wherein the difference between the signal levels is calculated by a subtracter.

The gain control circuit further includes a determination circuit that compares and determines the signal levels of the first and second video signals.
9. The signal processing circuit according to claim 8 , wherein a difference Kd between signal levels of the first and second video signals is calculated so that Kd ≧ 0 based on a determination result of the determination circuit. .

When the difference between the signal levels of the first and second video signals is Kd and the gain is KG, the gain is calculated by KG = 1−K1 × Kd (K1 is a constant). The signal processing circuit according to claim 10 .

9. The signal processing circuit according to claim 8 , wherein the gain is determined based on a signal level difference between output signals of the first and second low-pass filters.

The gain control circuit has a multiplier for multiplying the output signal of the averaging circuit by a gain,
The signal processing circuit according to claim 2 , wherein the gain is determined based on a difference and a sum of signal levels of the first and second video signals.

14. The signal processing circuit according to claim 13 , wherein the difference between the signal levels is calculated by a subtracter, and the sum of the signal levels is calculated by an adder.

The gain control circuit further includes a determination circuit that compares and determines the signal levels of the first and second video signals.
14. The signal processing circuit according to claim 13 , wherein a difference Kd between the signal levels of the first and second video signals is calculated so that Kd ≧ 0 based on a determination result of the determination circuit. .

When the difference and sum of the signal levels of the first and second video signals are Kd and Ks, respectively, and the gain is KG, KG = 1−K1 × Kd × (K2−Ks) (K1 and K2 are constants) The signal processing circuit according to claim 15 , wherein the gain is calculated by:

The signal processing circuit according to claim 13 , wherein the gain is determined based on a difference and a sum of signal levels of output signals of the first and second low-pass filters.

A determination circuit for determining which of the first and third video signals is to be selected based on signal levels of the first and third video signals;
The high-frequency signal processing circuit is configured to reduce aliasing noise based on one of the first video signal and the second video signal selected by the determination by the determination circuit. Generate a signal
The gain control circuit is configured to select the high frequency band based on a signal level of one of the first and third video signals and a signal level of the second video signal selected by the determination by the determination circuit. 2. The signal processing circuit according to claim 1, wherein the signal level of the signal is adjusted.

The high-frequency signal processing circuit is
First to third high-pass filters that respectively pass the high-frequency regions of the first to third video signals;
A selector circuit that selects an output of one of the first and third high-pass filters based on a determination result of the determination circuit;
The signal processing circuit according to claim 18 , further comprising: an averaging circuit that averages the output of the selector circuit and the output of the second high-pass filter and outputs the addition average result as the high-frequency signal.

The gain control circuit has a multiplier for multiplying the output signal of the averaging circuit by a gain,
The gain is determined based on a ratio of the signal level of one of the first and third video signals selected by the determination circuit and the signal level of the second video signal. The signal processing circuit according to claim 19 , wherein the signal processing circuit is characterized in that:

The determination circuit determines which one of the first and third video signals to select based on a ratio of signal levels of output signals of the first and third low-pass filters;
Of the output signals of the first and third low-pass filters, the signal level of the output signal corresponding to the video signal selected by the determination circuit is determined, and the signal level of the output signal of the second low-pass filter 21. The signal processing circuit according to claim 20 , wherein the gain is determined based on a difference between the two.

The gain control circuit has a multiplier for multiplying the output signal of the averaging circuit by a gain,
The gain is determined based on the difference between the signal level of one of the first and third video signals selected by the determination circuit and the signal level of the second video signal. The signal processing circuit according to claim 19 , wherein the signal processing circuit is characterized in that:

The determination circuit determines which one of the first and third video signals to select based on a ratio of signal levels of output signals of the first and third low-pass filters;
Of the output signals of the first and third low-pass filters, the signal level of the output signal corresponding to the video signal selected by the determination circuit is determined, and the signal level of the output signal of the second low-pass filter 23. The signal processing circuit according to claim 22 , wherein the gain is determined based on a difference between the gain and the gain.

The gain control circuit has a multiplier for multiplying the output signal of the averaging circuit by a gain,
The gain is determined based on the difference and sum of the signal level of one of the first and third video signals selected by the determination circuit and the signal level of the second video signal. The signal processing circuit according to claim 19, wherein:

The determination circuit determines which one of the first and third video signals to select based on a ratio of signal levels of output signals of the first and third low-pass filters;
Of the output signals of the first and third low-pass filters, the signal level of the output signal corresponding to the video signal selected by the determination circuit is determined, and the signal level of the output signal of the second low-pass filter 25. The signal processing circuit according to claim 24 , wherein the gain is determined based on a difference and a sum thereof.